1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SiFive composable cache controller Driver 4 * 5 * Copyright (C) 2018-2022 SiFive, Inc. 6 * 7 */ 8 9 #define pr_fmt(fmt) "CCACHE: " fmt 10 11 #include <linux/debugfs.h> 12 #include <linux/interrupt.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_address.h> 15 #include <linux/device.h> 16 #include <asm/cacheinfo.h> 17 #include <soc/sifive/sifive_ccache.h> 18 19 #define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100 20 #define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104 21 #define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108 22 23 #define SIFIVE_CCACHE_DIRECCFAIL_LOW 0x120 24 #define SIFIVE_CCACHE_DIRECCFAIL_HIGH 0x124 25 #define SIFIVE_CCACHE_DIRECCFAIL_COUNT 0x128 26 27 #define SIFIVE_CCACHE_DATECCFIX_LOW 0x140 28 #define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144 29 #define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148 30 31 #define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160 32 #define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164 33 #define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168 34 35 #define SIFIVE_CCACHE_CONFIG 0x00 36 #define SIFIVE_CCACHE_WAYENABLE 0x08 37 #define SIFIVE_CCACHE_ECCINJECTERR 0x40 38 39 #define SIFIVE_CCACHE_MAX_ECCINTR 4 40 41 static void __iomem *ccache_base; 42 static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; 43 static struct riscv_cacheinfo_ops ccache_cache_ops; 44 static int level; 45 46 enum { 47 DIR_CORR = 0, 48 DATA_CORR, 49 DATA_UNCORR, 50 DIR_UNCORR, 51 }; 52 53 #ifdef CONFIG_DEBUG_FS 54 static struct dentry *sifive_test; 55 56 static ssize_t ccache_write(struct file *file, const char __user *data, 57 size_t count, loff_t *ppos) 58 { 59 unsigned int val; 60 61 if (kstrtouint_from_user(data, count, 0, &val)) 62 return -EINVAL; 63 if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF)) 64 writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR); 65 else 66 return -EINVAL; 67 return count; 68 } 69 70 static const struct file_operations ccache_fops = { 71 .owner = THIS_MODULE, 72 .open = simple_open, 73 .write = ccache_write 74 }; 75 76 static void setup_sifive_debug(void) 77 { 78 sifive_test = debugfs_create_dir("sifive_ccache_cache", NULL); 79 80 debugfs_create_file("sifive_debug_inject_error", 0200, 81 sifive_test, NULL, &ccache_fops); 82 } 83 #endif 84 85 static void ccache_config_read(void) 86 { 87 u32 cfg; 88 89 cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); 90 91 pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", 92 (cfg & 0xff), (cfg >> 8) & 0xff, 93 BIT_ULL((cfg >> 16) & 0xff), 94 BIT_ULL((cfg >> 24) & 0xff)); 95 96 cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); 97 pr_info("Index of the largest way enabled: %u\n", cfg); 98 } 99 100 static const struct of_device_id sifive_ccache_ids[] = { 101 { .compatible = "sifive,fu540-c000-ccache" }, 102 { .compatible = "sifive,fu740-c000-ccache" }, 103 { .compatible = "sifive,ccache0" }, 104 { /* end of table */ } 105 }; 106 107 static ATOMIC_NOTIFIER_HEAD(ccache_err_chain); 108 109 int register_sifive_ccache_error_notifier(struct notifier_block *nb) 110 { 111 return atomic_notifier_chain_register(&ccache_err_chain, nb); 112 } 113 EXPORT_SYMBOL_GPL(register_sifive_ccache_error_notifier); 114 115 int unregister_sifive_ccache_error_notifier(struct notifier_block *nb) 116 { 117 return atomic_notifier_chain_unregister(&ccache_err_chain, nb); 118 } 119 EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier); 120 121 static int ccache_largest_wayenabled(void) 122 { 123 return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF; 124 } 125 126 static ssize_t number_of_ways_enabled_show(struct device *dev, 127 struct device_attribute *attr, 128 char *buf) 129 { 130 return sprintf(buf, "%u\n", ccache_largest_wayenabled()); 131 } 132 133 static DEVICE_ATTR_RO(number_of_ways_enabled); 134 135 static struct attribute *priv_attrs[] = { 136 &dev_attr_number_of_ways_enabled.attr, 137 NULL, 138 }; 139 140 static const struct attribute_group priv_attr_group = { 141 .attrs = priv_attrs, 142 }; 143 144 static const struct attribute_group *ccache_get_priv_group(struct cacheinfo 145 *this_leaf) 146 { 147 /* We want to use private group for composable cache only */ 148 if (this_leaf->level == level) 149 return &priv_attr_group; 150 else 151 return NULL; 152 } 153 154 static irqreturn_t ccache_int_handler(int irq, void *device) 155 { 156 unsigned int add_h, add_l; 157 158 if (irq == g_irq[DIR_CORR]) { 159 add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH); 160 add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW); 161 pr_err("DirError @ 0x%08X.%08X\n", add_h, add_l); 162 /* Reading this register clears the DirError interrupt sig */ 163 readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT); 164 atomic_notifier_call_chain(&ccache_err_chain, 165 SIFIVE_CCACHE_ERR_TYPE_CE, 166 "DirECCFix"); 167 } 168 if (irq == g_irq[DIR_UNCORR]) { 169 add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_HIGH); 170 add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_LOW); 171 /* Reading this register clears the DirFail interrupt sig */ 172 readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_COUNT); 173 atomic_notifier_call_chain(&ccache_err_chain, 174 SIFIVE_CCACHE_ERR_TYPE_UE, 175 "DirECCFail"); 176 panic("CCACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l); 177 } 178 if (irq == g_irq[DATA_CORR]) { 179 add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH); 180 add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW); 181 pr_err("DataError @ 0x%08X.%08X\n", add_h, add_l); 182 /* Reading this register clears the DataError interrupt sig */ 183 readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT); 184 atomic_notifier_call_chain(&ccache_err_chain, 185 SIFIVE_CCACHE_ERR_TYPE_CE, 186 "DatECCFix"); 187 } 188 if (irq == g_irq[DATA_UNCORR]) { 189 add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH); 190 add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW); 191 pr_err("DataFail @ 0x%08X.%08X\n", add_h, add_l); 192 /* Reading this register clears the DataFail interrupt sig */ 193 readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT); 194 atomic_notifier_call_chain(&ccache_err_chain, 195 SIFIVE_CCACHE_ERR_TYPE_UE, 196 "DatECCFail"); 197 } 198 199 return IRQ_HANDLED; 200 } 201 202 static int __init sifive_ccache_init(void) 203 { 204 struct device_node *np; 205 struct resource res; 206 int i, rc, intr_num; 207 208 np = of_find_matching_node(NULL, sifive_ccache_ids); 209 if (!np) 210 return -ENODEV; 211 212 if (of_address_to_resource(np, 0, &res)) 213 return -ENODEV; 214 215 ccache_base = ioremap(res.start, resource_size(&res)); 216 if (!ccache_base) 217 return -ENOMEM; 218 219 if (of_property_read_u32(np, "cache-level", &level)) 220 return -ENOENT; 221 222 intr_num = of_property_count_u32_elems(np, "interrupts"); 223 if (!intr_num) { 224 pr_err("No interrupts property\n"); 225 return -ENODEV; 226 } 227 228 for (i = 0; i < intr_num; i++) { 229 g_irq[i] = irq_of_parse_and_map(np, i); 230 rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", 231 NULL); 232 if (rc) { 233 pr_err("Could not request IRQ %d\n", g_irq[i]); 234 return rc; 235 } 236 } 237 238 ccache_config_read(); 239 240 ccache_cache_ops.get_priv_group = ccache_get_priv_group; 241 riscv_set_cacheinfo_ops(&ccache_cache_ops); 242 243 #ifdef CONFIG_DEBUG_FS 244 setup_sifive_debug(); 245 #endif 246 return 0; 247 } 248 249 device_initcall(sifive_ccache_init); 250