1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2009-2017, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2017-2019, Linaro Ltd. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/err.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/random.h> 12 #include <linux/slab.h> 13 #include <linux/soc/qcom/smem.h> 14 #include <linux/string.h> 15 #include <linux/sys_soc.h> 16 #include <linux/types.h> 17 18 #include <asm/unaligned.h> 19 20 /* 21 * SoC version type with major number in the upper 16 bits and minor 22 * number in the lower 16 bits. 23 */ 24 #define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff) 25 #define SOCINFO_MINOR(ver) ((ver) & 0xffff) 26 #define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff)) 27 28 #define SMEM_SOCINFO_BUILD_ID_LENGTH 32 29 #define SMEM_SOCINFO_CHIP_ID_LENGTH 32 30 31 /* 32 * SMEM item id, used to acquire handles to respective 33 * SMEM region. 34 */ 35 #define SMEM_HW_SW_BUILD_ID 137 36 37 #ifdef CONFIG_DEBUG_FS 38 #define SMEM_IMAGE_VERSION_BLOCKS_COUNT 32 39 #define SMEM_IMAGE_VERSION_SIZE 4096 40 #define SMEM_IMAGE_VERSION_NAME_SIZE 75 41 #define SMEM_IMAGE_VERSION_VARIANT_SIZE 20 42 #define SMEM_IMAGE_VERSION_OEM_SIZE 32 43 44 /* 45 * SMEM Image table indices 46 */ 47 #define SMEM_IMAGE_TABLE_BOOT_INDEX 0 48 #define SMEM_IMAGE_TABLE_TZ_INDEX 1 49 #define SMEM_IMAGE_TABLE_RPM_INDEX 3 50 #define SMEM_IMAGE_TABLE_APPS_INDEX 10 51 #define SMEM_IMAGE_TABLE_MPSS_INDEX 11 52 #define SMEM_IMAGE_TABLE_ADSP_INDEX 12 53 #define SMEM_IMAGE_TABLE_CNSS_INDEX 13 54 #define SMEM_IMAGE_TABLE_VIDEO_INDEX 14 55 #define SMEM_IMAGE_VERSION_TABLE 469 56 57 /* 58 * SMEM Image table names 59 */ 60 static const char *const socinfo_image_names[] = { 61 [SMEM_IMAGE_TABLE_ADSP_INDEX] = "adsp", 62 [SMEM_IMAGE_TABLE_APPS_INDEX] = "apps", 63 [SMEM_IMAGE_TABLE_BOOT_INDEX] = "boot", 64 [SMEM_IMAGE_TABLE_CNSS_INDEX] = "cnss", 65 [SMEM_IMAGE_TABLE_MPSS_INDEX] = "mpss", 66 [SMEM_IMAGE_TABLE_RPM_INDEX] = "rpm", 67 [SMEM_IMAGE_TABLE_TZ_INDEX] = "tz", 68 [SMEM_IMAGE_TABLE_VIDEO_INDEX] = "video", 69 }; 70 71 static const char *const pmic_models[] = { 72 [0] = "Unknown PMIC model", 73 [1] = "PM8941", 74 [2] = "PM8841", 75 [3] = "PM8019", 76 [4] = "PM8226", 77 [5] = "PM8110", 78 [6] = "PMA8084", 79 [7] = "PMI8962", 80 [8] = "PMD9635", 81 [9] = "PM8994", 82 [10] = "PMI8994", 83 [11] = "PM8916", 84 [12] = "PM8004", 85 [13] = "PM8909/PM8058", 86 [14] = "PM8028", 87 [15] = "PM8901", 88 [16] = "PM8950/PM8027", 89 [17] = "PMI8950/ISL9519", 90 [18] = "PMK8001/PM8921", 91 [19] = "PMI8996/PM8018", 92 [20] = "PM8998/PM8015", 93 [21] = "PMI8998/PM8014", 94 [22] = "PM8821", 95 [23] = "PM8038", 96 [24] = "PM8005/PM8922", 97 [25] = "PM8917", 98 [26] = "PM660L", 99 [27] = "PM660", 100 [30] = "PM8150", 101 [31] = "PM8150L", 102 [32] = "PM8150B", 103 [33] = "PMK8002", 104 [36] = "PM8009", 105 [38] = "PM8150C", 106 [41] = "SMB2351", 107 }; 108 #endif /* CONFIG_DEBUG_FS */ 109 110 /* Socinfo SMEM item structure */ 111 struct socinfo { 112 __le32 fmt; 113 __le32 id; 114 __le32 ver; 115 char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH]; 116 /* Version 2 */ 117 __le32 raw_id; 118 __le32 raw_ver; 119 /* Version 3 */ 120 __le32 hw_plat; 121 /* Version 4 */ 122 __le32 plat_ver; 123 /* Version 5 */ 124 __le32 accessory_chip; 125 /* Version 6 */ 126 __le32 hw_plat_subtype; 127 /* Version 7 */ 128 __le32 pmic_model; 129 __le32 pmic_die_rev; 130 /* Version 8 */ 131 __le32 pmic_model_1; 132 __le32 pmic_die_rev_1; 133 __le32 pmic_model_2; 134 __le32 pmic_die_rev_2; 135 /* Version 9 */ 136 __le32 foundry_id; 137 /* Version 10 */ 138 __le32 serial_num; 139 /* Version 11 */ 140 __le32 num_pmics; 141 __le32 pmic_array_offset; 142 /* Version 12 */ 143 __le32 chip_family; 144 __le32 raw_device_family; 145 __le32 raw_device_num; 146 /* Version 13 */ 147 __le32 nproduct_id; 148 char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH]; 149 /* Version 14 */ 150 __le32 num_clusters; 151 __le32 ncluster_array_offset; 152 __le32 num_defective_parts; 153 __le32 ndefective_parts_array_offset; 154 /* Version 15 */ 155 __le32 nmodem_supported; 156 }; 157 158 #ifdef CONFIG_DEBUG_FS 159 struct socinfo_params { 160 u32 raw_device_family; 161 u32 hw_plat_subtype; 162 u32 accessory_chip; 163 u32 raw_device_num; 164 u32 chip_family; 165 u32 foundry_id; 166 u32 plat_ver; 167 u32 raw_ver; 168 u32 hw_plat; 169 u32 fmt; 170 u32 nproduct_id; 171 u32 num_clusters; 172 u32 ncluster_array_offset; 173 u32 num_defective_parts; 174 u32 ndefective_parts_array_offset; 175 u32 nmodem_supported; 176 }; 177 178 struct smem_image_version { 179 char name[SMEM_IMAGE_VERSION_NAME_SIZE]; 180 char variant[SMEM_IMAGE_VERSION_VARIANT_SIZE]; 181 char pad; 182 char oem[SMEM_IMAGE_VERSION_OEM_SIZE]; 183 }; 184 #endif /* CONFIG_DEBUG_FS */ 185 186 struct qcom_socinfo { 187 struct soc_device *soc_dev; 188 struct soc_device_attribute attr; 189 #ifdef CONFIG_DEBUG_FS 190 struct dentry *dbg_root; 191 struct socinfo_params info; 192 #endif /* CONFIG_DEBUG_FS */ 193 }; 194 195 struct soc_id { 196 unsigned int id; 197 const char *name; 198 }; 199 200 static const struct soc_id soc_id[] = { 201 { 87, "MSM8960" }, 202 { 109, "APQ8064" }, 203 { 122, "MSM8660A" }, 204 { 123, "MSM8260A" }, 205 { 124, "APQ8060A" }, 206 { 126, "MSM8974" }, 207 { 130, "MPQ8064" }, 208 { 138, "MSM8960AB" }, 209 { 139, "APQ8060AB" }, 210 { 140, "MSM8260AB" }, 211 { 141, "MSM8660AB" }, 212 { 145, "MSM8626" }, 213 { 147, "MSM8610" }, 214 { 153, "APQ8064AB" }, 215 { 158, "MSM8226" }, 216 { 159, "MSM8526" }, 217 { 161, "MSM8110" }, 218 { 162, "MSM8210" }, 219 { 163, "MSM8810" }, 220 { 164, "MSM8212" }, 221 { 165, "MSM8612" }, 222 { 166, "MSM8112" }, 223 { 168, "MSM8225Q" }, 224 { 169, "MSM8625Q" }, 225 { 170, "MSM8125Q" }, 226 { 172, "APQ8064AA" }, 227 { 178, "APQ8084" }, 228 { 184, "APQ8074" }, 229 { 185, "MSM8274" }, 230 { 186, "MSM8674" }, 231 { 194, "MSM8974PRO" }, 232 { 198, "MSM8126" }, 233 { 199, "APQ8026" }, 234 { 200, "MSM8926" }, 235 { 205, "MSM8326" }, 236 { 206, "MSM8916" }, 237 { 207, "MSM8994" }, 238 { 208, "APQ8074-AA" }, 239 { 209, "APQ8074-AB" }, 240 { 210, "APQ8074PRO" }, 241 { 211, "MSM8274-AA" }, 242 { 212, "MSM8274-AB" }, 243 { 213, "MSM8274PRO" }, 244 { 214, "MSM8674-AA" }, 245 { 215, "MSM8674-AB" }, 246 { 216, "MSM8674PRO" }, 247 { 217, "MSM8974-AA" }, 248 { 218, "MSM8974-AB" }, 249 { 219, "APQ8028" }, 250 { 220, "MSM8128" }, 251 { 221, "MSM8228" }, 252 { 222, "MSM8528" }, 253 { 223, "MSM8628" }, 254 { 224, "MSM8928" }, 255 { 225, "MSM8510" }, 256 { 226, "MSM8512" }, 257 { 233, "MSM8936" }, 258 { 239, "MSM8939" }, 259 { 240, "APQ8036" }, 260 { 241, "APQ8039" }, 261 { 246, "MSM8996" }, 262 { 247, "APQ8016" }, 263 { 248, "MSM8216" }, 264 { 249, "MSM8116" }, 265 { 250, "MSM8616" }, 266 { 251, "MSM8992" }, 267 { 253, "APQ8094" }, 268 { 290, "MDM9607" }, 269 { 291, "APQ8096" }, 270 { 292, "MSM8998" }, 271 { 293, "MSM8953" }, 272 { 296, "MDM8207" }, 273 { 297, "MDM9207" }, 274 { 298, "MDM9307" }, 275 { 299, "MDM9628" }, 276 { 304, "APQ8053" }, 277 { 305, "MSM8996SG" }, 278 { 310, "MSM8996AU" }, 279 { 311, "APQ8096AU" }, 280 { 312, "APQ8096SG" }, 281 { 317, "SDM660" }, 282 { 318, "SDM630" }, 283 { 319, "APQ8098" }, 284 { 321, "SDM845" }, 285 { 322, "MDM9206" }, 286 { 323, "IPQ8074" }, 287 { 324, "SDA660" }, 288 { 325, "SDM658" }, 289 { 326, "SDA658" }, 290 { 327, "SDA630" }, 291 { 338, "SDM450" }, 292 { 341, "SDA845" }, 293 { 342, "IPQ8072" }, 294 { 343, "IPQ8076" }, 295 { 344, "IPQ8078" }, 296 { 345, "SDM636" }, 297 { 346, "SDA636" }, 298 { 349, "SDM632" }, 299 { 350, "SDA632" }, 300 { 351, "SDA450" }, 301 { 356, "SM8250" }, 302 { 375, "IPQ8070" }, 303 { 376, "IPQ8071" }, 304 { 389, "IPQ8072A" }, 305 { 390, "IPQ8074A" }, 306 { 391, "IPQ8076A" }, 307 { 392, "IPQ8078A" }, 308 { 394, "SM6125" }, 309 { 395, "IPQ8070A" }, 310 { 396, "IPQ8071A" }, 311 { 402, "IPQ6018" }, 312 { 403, "IPQ6028" }, 313 { 421, "IPQ6000" }, 314 { 422, "IPQ6010" }, 315 { 425, "SC7180" }, 316 { 434, "SM6350" }, 317 { 453, "IPQ6005" }, 318 { 455, "QRB5165" }, 319 { 457, "SM8450" }, 320 { 459, "SM7225" }, 321 }; 322 323 static const char *socinfo_machine(struct device *dev, unsigned int id) 324 { 325 int idx; 326 327 for (idx = 0; idx < ARRAY_SIZE(soc_id); idx++) { 328 if (soc_id[idx].id == id) 329 return soc_id[idx].name; 330 } 331 332 return NULL; 333 } 334 335 #ifdef CONFIG_DEBUG_FS 336 337 #define QCOM_OPEN(name, _func) \ 338 static int qcom_open_##name(struct inode *inode, struct file *file) \ 339 { \ 340 return single_open(file, _func, inode->i_private); \ 341 } \ 342 \ 343 static const struct file_operations qcom_ ##name## _ops = { \ 344 .open = qcom_open_##name, \ 345 .read = seq_read, \ 346 .llseek = seq_lseek, \ 347 .release = single_release, \ 348 } 349 350 #define DEBUGFS_ADD(info, name) \ 351 debugfs_create_file(__stringify(name), 0444, \ 352 qcom_socinfo->dbg_root, \ 353 info, &qcom_ ##name## _ops) 354 355 356 static int qcom_show_build_id(struct seq_file *seq, void *p) 357 { 358 struct socinfo *socinfo = seq->private; 359 360 seq_printf(seq, "%s\n", socinfo->build_id); 361 362 return 0; 363 } 364 365 static int qcom_show_pmic_model(struct seq_file *seq, void *p) 366 { 367 struct socinfo *socinfo = seq->private; 368 int model = SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_model)); 369 370 if (model < 0) 371 return -EINVAL; 372 373 if (model < ARRAY_SIZE(pmic_models) && pmic_models[model]) 374 seq_printf(seq, "%s\n", pmic_models[model]); 375 else 376 seq_printf(seq, "unknown (%d)\n", model); 377 378 return 0; 379 } 380 381 static int qcom_show_pmic_model_array(struct seq_file *seq, void *p) 382 { 383 struct socinfo *socinfo = seq->private; 384 unsigned int num_pmics = le32_to_cpu(socinfo->num_pmics); 385 unsigned int pmic_array_offset = le32_to_cpu(socinfo->pmic_array_offset); 386 int i; 387 void *ptr = socinfo; 388 389 ptr += pmic_array_offset; 390 391 /* No need for bounds checking, it happened at socinfo_debugfs_init */ 392 for (i = 0; i < num_pmics; i++) { 393 unsigned int model = SOCINFO_MINOR(get_unaligned_le32(ptr + 2 * i * sizeof(u32))); 394 unsigned int die_rev = get_unaligned_le32(ptr + (2 * i + 1) * sizeof(u32)); 395 396 if (model < ARRAY_SIZE(pmic_models) && pmic_models[model]) 397 seq_printf(seq, "%s %u.%u\n", pmic_models[model], 398 SOCINFO_MAJOR(die_rev), 399 SOCINFO_MINOR(die_rev)); 400 else 401 seq_printf(seq, "unknown (%d)\n", model); 402 } 403 404 return 0; 405 } 406 407 static int qcom_show_pmic_die_revision(struct seq_file *seq, void *p) 408 { 409 struct socinfo *socinfo = seq->private; 410 411 seq_printf(seq, "%u.%u\n", 412 SOCINFO_MAJOR(le32_to_cpu(socinfo->pmic_die_rev)), 413 SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_die_rev))); 414 415 return 0; 416 } 417 418 static int qcom_show_chip_id(struct seq_file *seq, void *p) 419 { 420 struct socinfo *socinfo = seq->private; 421 422 seq_printf(seq, "%s\n", socinfo->chip_id); 423 424 return 0; 425 } 426 427 QCOM_OPEN(build_id, qcom_show_build_id); 428 QCOM_OPEN(pmic_model, qcom_show_pmic_model); 429 QCOM_OPEN(pmic_model_array, qcom_show_pmic_model_array); 430 QCOM_OPEN(pmic_die_rev, qcom_show_pmic_die_revision); 431 QCOM_OPEN(chip_id, qcom_show_chip_id); 432 433 #define DEFINE_IMAGE_OPS(type) \ 434 static int show_image_##type(struct seq_file *seq, void *p) \ 435 { \ 436 struct smem_image_version *image_version = seq->private; \ 437 if (image_version->type[0] != '\0') \ 438 seq_printf(seq, "%s\n", image_version->type); \ 439 return 0; \ 440 } \ 441 static int open_image_##type(struct inode *inode, struct file *file) \ 442 { \ 443 return single_open(file, show_image_##type, inode->i_private); \ 444 } \ 445 \ 446 static const struct file_operations qcom_image_##type##_ops = { \ 447 .open = open_image_##type, \ 448 .read = seq_read, \ 449 .llseek = seq_lseek, \ 450 .release = single_release, \ 451 } 452 453 DEFINE_IMAGE_OPS(name); 454 DEFINE_IMAGE_OPS(variant); 455 DEFINE_IMAGE_OPS(oem); 456 457 static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, 458 struct socinfo *info, size_t info_size) 459 { 460 struct smem_image_version *versions; 461 struct dentry *dentry; 462 size_t size; 463 int i; 464 unsigned int num_pmics; 465 unsigned int pmic_array_offset; 466 467 qcom_socinfo->dbg_root = debugfs_create_dir("qcom_socinfo", NULL); 468 469 qcom_socinfo->info.fmt = __le32_to_cpu(info->fmt); 470 471 debugfs_create_x32("info_fmt", 0444, qcom_socinfo->dbg_root, 472 &qcom_socinfo->info.fmt); 473 474 switch (qcom_socinfo->info.fmt) { 475 case SOCINFO_VERSION(0, 15): 476 qcom_socinfo->info.nmodem_supported = __le32_to_cpu(info->nmodem_supported); 477 478 debugfs_create_u32("nmodem_supported", 0444, qcom_socinfo->dbg_root, 479 &qcom_socinfo->info.nmodem_supported); 480 fallthrough; 481 case SOCINFO_VERSION(0, 14): 482 qcom_socinfo->info.num_clusters = __le32_to_cpu(info->num_clusters); 483 qcom_socinfo->info.ncluster_array_offset = __le32_to_cpu(info->ncluster_array_offset); 484 qcom_socinfo->info.num_defective_parts = __le32_to_cpu(info->num_defective_parts); 485 qcom_socinfo->info.ndefective_parts_array_offset = __le32_to_cpu(info->ndefective_parts_array_offset); 486 487 debugfs_create_u32("num_clusters", 0444, qcom_socinfo->dbg_root, 488 &qcom_socinfo->info.num_clusters); 489 debugfs_create_u32("ncluster_array_offset", 0444, qcom_socinfo->dbg_root, 490 &qcom_socinfo->info.ncluster_array_offset); 491 debugfs_create_u32("num_defective_parts", 0444, qcom_socinfo->dbg_root, 492 &qcom_socinfo->info.num_defective_parts); 493 debugfs_create_u32("ndefective_parts_array_offset", 0444, qcom_socinfo->dbg_root, 494 &qcom_socinfo->info.ndefective_parts_array_offset); 495 fallthrough; 496 case SOCINFO_VERSION(0, 13): 497 qcom_socinfo->info.nproduct_id = __le32_to_cpu(info->nproduct_id); 498 499 debugfs_create_u32("nproduct_id", 0444, qcom_socinfo->dbg_root, 500 &qcom_socinfo->info.nproduct_id); 501 DEBUGFS_ADD(info, chip_id); 502 fallthrough; 503 case SOCINFO_VERSION(0, 12): 504 qcom_socinfo->info.chip_family = 505 __le32_to_cpu(info->chip_family); 506 qcom_socinfo->info.raw_device_family = 507 __le32_to_cpu(info->raw_device_family); 508 qcom_socinfo->info.raw_device_num = 509 __le32_to_cpu(info->raw_device_num); 510 511 debugfs_create_x32("chip_family", 0444, qcom_socinfo->dbg_root, 512 &qcom_socinfo->info.chip_family); 513 debugfs_create_x32("raw_device_family", 0444, 514 qcom_socinfo->dbg_root, 515 &qcom_socinfo->info.raw_device_family); 516 debugfs_create_x32("raw_device_number", 0444, 517 qcom_socinfo->dbg_root, 518 &qcom_socinfo->info.raw_device_num); 519 fallthrough; 520 case SOCINFO_VERSION(0, 11): 521 num_pmics = le32_to_cpu(info->num_pmics); 522 pmic_array_offset = le32_to_cpu(info->pmic_array_offset); 523 if (pmic_array_offset + 2 * num_pmics * sizeof(u32) <= info_size) 524 DEBUGFS_ADD(info, pmic_model_array); 525 fallthrough; 526 case SOCINFO_VERSION(0, 10): 527 case SOCINFO_VERSION(0, 9): 528 qcom_socinfo->info.foundry_id = __le32_to_cpu(info->foundry_id); 529 530 debugfs_create_u32("foundry_id", 0444, qcom_socinfo->dbg_root, 531 &qcom_socinfo->info.foundry_id); 532 fallthrough; 533 case SOCINFO_VERSION(0, 8): 534 case SOCINFO_VERSION(0, 7): 535 DEBUGFS_ADD(info, pmic_model); 536 DEBUGFS_ADD(info, pmic_die_rev); 537 fallthrough; 538 case SOCINFO_VERSION(0, 6): 539 qcom_socinfo->info.hw_plat_subtype = 540 __le32_to_cpu(info->hw_plat_subtype); 541 542 debugfs_create_u32("hardware_platform_subtype", 0444, 543 qcom_socinfo->dbg_root, 544 &qcom_socinfo->info.hw_plat_subtype); 545 fallthrough; 546 case SOCINFO_VERSION(0, 5): 547 qcom_socinfo->info.accessory_chip = 548 __le32_to_cpu(info->accessory_chip); 549 550 debugfs_create_u32("accessory_chip", 0444, 551 qcom_socinfo->dbg_root, 552 &qcom_socinfo->info.accessory_chip); 553 fallthrough; 554 case SOCINFO_VERSION(0, 4): 555 qcom_socinfo->info.plat_ver = __le32_to_cpu(info->plat_ver); 556 557 debugfs_create_u32("platform_version", 0444, 558 qcom_socinfo->dbg_root, 559 &qcom_socinfo->info.plat_ver); 560 fallthrough; 561 case SOCINFO_VERSION(0, 3): 562 qcom_socinfo->info.hw_plat = __le32_to_cpu(info->hw_plat); 563 564 debugfs_create_u32("hardware_platform", 0444, 565 qcom_socinfo->dbg_root, 566 &qcom_socinfo->info.hw_plat); 567 fallthrough; 568 case SOCINFO_VERSION(0, 2): 569 qcom_socinfo->info.raw_ver = __le32_to_cpu(info->raw_ver); 570 571 debugfs_create_u32("raw_version", 0444, qcom_socinfo->dbg_root, 572 &qcom_socinfo->info.raw_ver); 573 fallthrough; 574 case SOCINFO_VERSION(0, 1): 575 DEBUGFS_ADD(info, build_id); 576 break; 577 } 578 579 versions = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_IMAGE_VERSION_TABLE, 580 &size); 581 582 for (i = 0; i < ARRAY_SIZE(socinfo_image_names); i++) { 583 if (!socinfo_image_names[i]) 584 continue; 585 586 dentry = debugfs_create_dir(socinfo_image_names[i], 587 qcom_socinfo->dbg_root); 588 debugfs_create_file("name", 0444, dentry, &versions[i], 589 &qcom_image_name_ops); 590 debugfs_create_file("variant", 0444, dentry, &versions[i], 591 &qcom_image_variant_ops); 592 debugfs_create_file("oem", 0444, dentry, &versions[i], 593 &qcom_image_oem_ops); 594 } 595 } 596 597 static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) 598 { 599 debugfs_remove_recursive(qcom_socinfo->dbg_root); 600 } 601 #else 602 static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, 603 struct socinfo *info, size_t info_size) 604 { 605 } 606 static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) { } 607 #endif /* CONFIG_DEBUG_FS */ 608 609 static int qcom_socinfo_probe(struct platform_device *pdev) 610 { 611 struct qcom_socinfo *qs; 612 struct socinfo *info; 613 size_t item_size; 614 615 info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, 616 &item_size); 617 if (IS_ERR(info)) { 618 dev_err(&pdev->dev, "Couldn't find socinfo\n"); 619 return PTR_ERR(info); 620 } 621 622 qs = devm_kzalloc(&pdev->dev, sizeof(*qs), GFP_KERNEL); 623 if (!qs) 624 return -ENOMEM; 625 626 qs->attr.family = "Snapdragon"; 627 qs->attr.machine = socinfo_machine(&pdev->dev, 628 le32_to_cpu(info->id)); 629 qs->attr.soc_id = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u", 630 le32_to_cpu(info->id)); 631 qs->attr.revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u.%u", 632 SOCINFO_MAJOR(le32_to_cpu(info->ver)), 633 SOCINFO_MINOR(le32_to_cpu(info->ver))); 634 if (offsetof(struct socinfo, serial_num) <= item_size) 635 qs->attr.serial_number = devm_kasprintf(&pdev->dev, GFP_KERNEL, 636 "%u", 637 le32_to_cpu(info->serial_num)); 638 639 qs->soc_dev = soc_device_register(&qs->attr); 640 if (IS_ERR(qs->soc_dev)) 641 return PTR_ERR(qs->soc_dev); 642 643 socinfo_debugfs_init(qs, info, item_size); 644 645 /* Feed the soc specific unique data into entropy pool */ 646 add_device_randomness(info, item_size); 647 648 platform_set_drvdata(pdev, qs); 649 650 return 0; 651 } 652 653 static int qcom_socinfo_remove(struct platform_device *pdev) 654 { 655 struct qcom_socinfo *qs = platform_get_drvdata(pdev); 656 657 soc_device_unregister(qs->soc_dev); 658 659 socinfo_debugfs_exit(qs); 660 661 return 0; 662 } 663 664 static struct platform_driver qcom_socinfo_driver = { 665 .probe = qcom_socinfo_probe, 666 .remove = qcom_socinfo_remove, 667 .driver = { 668 .name = "qcom-socinfo", 669 }, 670 }; 671 672 module_platform_driver(qcom_socinfo_driver); 673 674 MODULE_DESCRIPTION("Qualcomm SoCinfo driver"); 675 MODULE_LICENSE("GPL v2"); 676 MODULE_ALIAS("platform:qcom-socinfo"); 677