1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 3 4 #include <linux/acpi.h> 5 #include <linux/clk.h> 6 #include <linux/console.h> 7 #include <linux/slab.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/pinctrl/consumer.h> 14 #include <linux/platform_device.h> 15 #include <linux/qcom-geni-se.h> 16 17 /** 18 * DOC: Overview 19 * 20 * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced 21 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper 22 * controller. QUP Wrapper is designed to support various serial bus protocols 23 * like UART, SPI, I2C, I3C, etc. 24 */ 25 26 /** 27 * DOC: Hardware description 28 * 29 * GENI based QUP is a highly-flexible and programmable module for supporting 30 * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single 31 * QUP module can provide upto 8 serial interfaces, using its internal 32 * serial engines. The actual configuration is determined by the target 33 * platform configuration. The protocol supported by each interface is 34 * determined by the firmware loaded to the serial engine. Each SE consists 35 * of a DMA Engine and GENI sub modules which enable serial engines to 36 * support FIFO and DMA modes of operation. 37 * 38 * 39 * +-----------------------------------------+ 40 * |QUP Wrapper | 41 * | +----------------------------+ | 42 * --QUP & SE Clocks--> | Serial Engine N | +-IO------> 43 * | | ... | | Interface 44 * <---Clock Perf.----+ +----+-----------------------+ | | 45 * State Interface | | Serial Engine 1 | | | 46 * | | | | | 47 * | | | | | 48 * <--------AHB-------> | | | | 49 * | | +----+ | 50 * | | | | 51 * | | | | 52 * <------SE IRQ------+ +----------------------------+ | 53 * | | 54 * +-----------------------------------------+ 55 * 56 * Figure 1: GENI based QUP Wrapper 57 * 58 * The GENI submodules include primary and secondary sequencers which are 59 * used to drive TX & RX operations. On serial interfaces that operate using 60 * master-slave model, primary sequencer drives both TX & RX operations. On 61 * serial interfaces that operate using peer-to-peer model, primary sequencer 62 * drives TX operation and secondary sequencer drives RX operation. 63 */ 64 65 /** 66 * DOC: Software description 67 * 68 * GENI SE Wrapper driver is structured into 2 parts: 69 * 70 * geni_wrapper represents QUP Wrapper controller. This part of the driver 71 * manages QUP Wrapper information such as hardware version, clock 72 * performance table that is common to all the internal serial engines. 73 * 74 * geni_se represents serial engine. This part of the driver manages serial 75 * engine information such as clocks, containing QUP Wrapper, etc. This part 76 * of driver also supports operations (eg. initialize the concerned serial 77 * engine, select between FIFO and DMA mode of operation etc.) that are 78 * common to all the serial engines and are independent of serial interfaces. 79 */ 80 81 #define MAX_CLK_PERF_LEVEL 32 82 #define NUM_AHB_CLKS 2 83 84 /** 85 * @struct geni_wrapper - Data structure to represent the QUP Wrapper Core 86 * @dev: Device pointer of the QUP wrapper core 87 * @base: Base address of this instance of QUP wrapper core 88 * @ahb_clks: Handle to the primary & secondary AHB clocks 89 */ 90 struct geni_wrapper { 91 struct device *dev; 92 void __iomem *base; 93 struct clk_bulk_data ahb_clks[NUM_AHB_CLKS]; 94 struct geni_icc_path to_core; 95 }; 96 97 static const char * const icc_path_names[] = {"qup-core", "qup-config", 98 "qup-memory"}; 99 100 static struct geni_wrapper *earlycon_wrapper; 101 102 #define QUP_HW_VER_REG 0x4 103 104 /* Common SE registers */ 105 #define GENI_INIT_CFG_REVISION 0x0 106 #define GENI_S_INIT_CFG_REVISION 0x4 107 #define GENI_OUTPUT_CTRL 0x24 108 #define GENI_CGC_CTRL 0x28 109 #define GENI_CLK_CTRL_RO 0x60 110 #define GENI_IF_DISABLE_RO 0x64 111 #define GENI_FW_S_REVISION_RO 0x6c 112 #define SE_GENI_BYTE_GRAN 0x254 113 #define SE_GENI_TX_PACKING_CFG0 0x260 114 #define SE_GENI_TX_PACKING_CFG1 0x264 115 #define SE_GENI_RX_PACKING_CFG0 0x284 116 #define SE_GENI_RX_PACKING_CFG1 0x288 117 #define SE_GENI_M_GP_LENGTH 0x910 118 #define SE_GENI_S_GP_LENGTH 0x914 119 #define SE_DMA_TX_PTR_L 0xc30 120 #define SE_DMA_TX_PTR_H 0xc34 121 #define SE_DMA_TX_ATTR 0xc38 122 #define SE_DMA_TX_LEN 0xc3c 123 #define SE_DMA_TX_IRQ_EN 0xc48 124 #define SE_DMA_TX_IRQ_EN_SET 0xc4c 125 #define SE_DMA_TX_IRQ_EN_CLR 0xc50 126 #define SE_DMA_TX_LEN_IN 0xc54 127 #define SE_DMA_TX_MAX_BURST 0xc5c 128 #define SE_DMA_RX_PTR_L 0xd30 129 #define SE_DMA_RX_PTR_H 0xd34 130 #define SE_DMA_RX_ATTR 0xd38 131 #define SE_DMA_RX_LEN 0xd3c 132 #define SE_DMA_RX_IRQ_EN 0xd48 133 #define SE_DMA_RX_IRQ_EN_SET 0xd4c 134 #define SE_DMA_RX_IRQ_EN_CLR 0xd50 135 #define SE_DMA_RX_LEN_IN 0xd54 136 #define SE_DMA_RX_MAX_BURST 0xd5c 137 #define SE_DMA_RX_FLUSH 0xd60 138 #define SE_GSI_EVENT_EN 0xe18 139 #define SE_IRQ_EN 0xe1c 140 #define SE_DMA_GENERAL_CFG 0xe30 141 142 /* GENI_OUTPUT_CTRL fields */ 143 #define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0) 144 145 /* GENI_CGC_CTRL fields */ 146 #define CFG_AHB_CLK_CGC_ON BIT(0) 147 #define CFG_AHB_WR_ACLK_CGC_ON BIT(1) 148 #define DATA_AHB_CLK_CGC_ON BIT(2) 149 #define SCLK_CGC_ON BIT(3) 150 #define TX_CLK_CGC_ON BIT(4) 151 #define RX_CLK_CGC_ON BIT(5) 152 #define EXT_CLK_CGC_ON BIT(6) 153 #define PROG_RAM_HCLK_OFF BIT(8) 154 #define PROG_RAM_SCLK_OFF BIT(9) 155 #define DEFAULT_CGC_EN GENMASK(6, 0) 156 157 /* SE_GSI_EVENT_EN fields */ 158 #define DMA_RX_EVENT_EN BIT(0) 159 #define DMA_TX_EVENT_EN BIT(1) 160 #define GENI_M_EVENT_EN BIT(2) 161 #define GENI_S_EVENT_EN BIT(3) 162 163 /* SE_IRQ_EN fields */ 164 #define DMA_RX_IRQ_EN BIT(0) 165 #define DMA_TX_IRQ_EN BIT(1) 166 #define GENI_M_IRQ_EN BIT(2) 167 #define GENI_S_IRQ_EN BIT(3) 168 169 /* SE_DMA_GENERAL_CFG */ 170 #define DMA_RX_CLK_CGC_ON BIT(0) 171 #define DMA_TX_CLK_CGC_ON BIT(1) 172 #define DMA_AHB_SLV_CFG_ON BIT(2) 173 #define AHB_SEC_SLV_CLK_CGC_ON BIT(3) 174 #define DUMMY_RX_NON_BUFFERABLE BIT(4) 175 #define RX_DMA_ZERO_PADDING_EN BIT(5) 176 #define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6) 177 #define RX_DMA_IRQ_DELAY_SHFT 6 178 179 /** 180 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version 181 * @se: Pointer to the corresponding serial engine. 182 * 183 * Return: Hardware Version of the wrapper. 184 */ 185 u32 geni_se_get_qup_hw_version(struct geni_se *se) 186 { 187 struct geni_wrapper *wrapper = se->wrapper; 188 189 return readl_relaxed(wrapper->base + QUP_HW_VER_REG); 190 } 191 EXPORT_SYMBOL(geni_se_get_qup_hw_version); 192 193 static void geni_se_io_set_mode(void __iomem *base) 194 { 195 u32 val; 196 197 val = readl_relaxed(base + SE_IRQ_EN); 198 val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN; 199 val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN; 200 writel_relaxed(val, base + SE_IRQ_EN); 201 202 val = readl_relaxed(base + SE_GENI_DMA_MODE_EN); 203 val &= ~GENI_DMA_MODE_EN; 204 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN); 205 206 writel_relaxed(0, base + SE_GSI_EVENT_EN); 207 } 208 209 static void geni_se_io_init(void __iomem *base) 210 { 211 u32 val; 212 213 val = readl_relaxed(base + GENI_CGC_CTRL); 214 val |= DEFAULT_CGC_EN; 215 writel_relaxed(val, base + GENI_CGC_CTRL); 216 217 val = readl_relaxed(base + SE_DMA_GENERAL_CFG); 218 val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON; 219 val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON; 220 writel_relaxed(val, base + SE_DMA_GENERAL_CFG); 221 222 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL); 223 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG); 224 } 225 226 static void geni_se_irq_clear(struct geni_se *se) 227 { 228 writel_relaxed(0, se->base + SE_GSI_EVENT_EN); 229 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR); 230 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR); 231 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR); 232 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR); 233 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN); 234 } 235 236 /** 237 * geni_se_init() - Initialize the GENI serial engine 238 * @se: Pointer to the concerned serial engine. 239 * @rx_wm: Receive watermark, in units of FIFO words. 240 * @rx_rfr_wm: Ready-for-receive watermark, in units of FIFO words. 241 * 242 * This function is used to initialize the GENI serial engine, configure 243 * receive watermark and ready-for-receive watermarks. 244 */ 245 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr) 246 { 247 u32 val; 248 249 geni_se_irq_clear(se); 250 geni_se_io_init(se->base); 251 geni_se_io_set_mode(se->base); 252 253 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG); 254 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG); 255 256 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 257 val |= M_COMMON_GENI_M_IRQ_EN; 258 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 259 260 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 261 val |= S_COMMON_GENI_S_IRQ_EN; 262 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 263 } 264 EXPORT_SYMBOL(geni_se_init); 265 266 static void geni_se_select_fifo_mode(struct geni_se *se) 267 { 268 u32 proto = geni_se_read_proto(se); 269 u32 val, val_old; 270 271 geni_se_irq_clear(se); 272 273 /* 274 * The RX path for the UART is asynchronous and so needs more 275 * complex logic for enabling / disabling its interrupts. 276 * 277 * Specific notes: 278 * - The done and TX-related interrupts are managed manually. 279 * - We don't RX from the main sequencer (we use the secondary) so 280 * we don't need the RX-related interrupts enabled in the main 281 * sequencer for UART. 282 */ 283 if (proto != GENI_SE_UART) { 284 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 285 val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN; 286 val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 287 if (val != val_old) 288 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 289 290 val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 291 val |= S_CMD_DONE_EN; 292 if (val != val_old) 293 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 294 } 295 296 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 297 val &= ~GENI_DMA_MODE_EN; 298 if (val != val_old) 299 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 300 } 301 302 static void geni_se_select_dma_mode(struct geni_se *se) 303 { 304 u32 proto = geni_se_read_proto(se); 305 u32 val, val_old; 306 307 geni_se_irq_clear(se); 308 309 if (proto != GENI_SE_UART) { 310 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 311 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 312 val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 313 if (val != val_old) 314 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 315 316 val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 317 val &= ~S_CMD_DONE_EN; 318 if (val != val_old) 319 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 320 } 321 322 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 323 val |= GENI_DMA_MODE_EN; 324 if (val != val_old) 325 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 326 } 327 328 /** 329 * geni_se_select_mode() - Select the serial engine transfer mode 330 * @se: Pointer to the concerned serial engine. 331 * @mode: Transfer mode to be selected. 332 */ 333 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode) 334 { 335 WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA); 336 337 switch (mode) { 338 case GENI_SE_FIFO: 339 geni_se_select_fifo_mode(se); 340 break; 341 case GENI_SE_DMA: 342 geni_se_select_dma_mode(se); 343 break; 344 case GENI_SE_INVALID: 345 default: 346 break; 347 } 348 } 349 EXPORT_SYMBOL(geni_se_select_mode); 350 351 /** 352 * DOC: Overview 353 * 354 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist 355 * of up to 4 operations, each operation represented by 4 configuration vectors 356 * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for 357 * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO. 358 * Refer to below examples for detailed bit-field description. 359 * 360 * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1 361 * 362 * +-----------+-------+-------+-------+-------+ 363 * | | vec_0 | vec_1 | vec_2 | vec_3 | 364 * +-----------+-------+-------+-------+-------+ 365 * | start | 0x6 | 0xe | 0x16 | 0x1e | 366 * | direction | 1 | 1 | 1 | 1 | 367 * | length | 6 | 6 | 6 | 6 | 368 * | stop | 0 | 0 | 0 | 1 | 369 * +-----------+-------+-------+-------+-------+ 370 * 371 * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0 372 * 373 * +-----------+-------+-------+-------+-------+ 374 * | | vec_0 | vec_1 | vec_2 | vec_3 | 375 * +-----------+-------+-------+-------+-------+ 376 * | start | 0x0 | 0x8 | 0x10 | 0x18 | 377 * | direction | 0 | 0 | 0 | 0 | 378 * | length | 7 | 6 | 7 | 6 | 379 * | stop | 0 | 0 | 0 | 1 | 380 * +-----------+-------+-------+-------+-------+ 381 * 382 * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1 383 * 384 * +-----------+-------+-------+-------+-------+ 385 * | | vec_0 | vec_1 | vec_2 | vec_3 | 386 * +-----------+-------+-------+-------+-------+ 387 * | start | 0x16 | 0xe | 0x6 | 0x0 | 388 * | direction | 1 | 1 | 1 | 1 | 389 * | length | 7 | 7 | 6 | 0 | 390 * | stop | 0 | 0 | 1 | 0 | 391 * +-----------+-------+-------+-------+-------+ 392 * 393 */ 394 395 #define NUM_PACKING_VECTORS 4 396 #define PACKING_START_SHIFT 5 397 #define PACKING_DIR_SHIFT 4 398 #define PACKING_LEN_SHIFT 1 399 #define PACKING_STOP_BIT BIT(0) 400 #define PACKING_VECTOR_SHIFT 10 401 /** 402 * geni_se_config_packing() - Packing configuration of the serial engine 403 * @se: Pointer to the concerned serial engine 404 * @bpw: Bits of data per transfer word. 405 * @pack_words: Number of words per fifo element. 406 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa. 407 * @tx_cfg: Flag to configure the TX Packing. 408 * @rx_cfg: Flag to configure the RX Packing. 409 * 410 * This function is used to configure the packing rules for the current 411 * transfer. 412 */ 413 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words, 414 bool msb_to_lsb, bool tx_cfg, bool rx_cfg) 415 { 416 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0}; 417 int len; 418 int temp_bpw = bpw; 419 int idx_start = msb_to_lsb ? bpw - 1 : 0; 420 int idx = idx_start; 421 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE; 422 int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE); 423 int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE; 424 int i; 425 426 if (iter <= 0 || iter > NUM_PACKING_VECTORS) 427 return; 428 429 for (i = 0; i < iter; i++) { 430 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1; 431 cfg[i] = idx << PACKING_START_SHIFT; 432 cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT; 433 cfg[i] |= len << PACKING_LEN_SHIFT; 434 435 if (temp_bpw <= BITS_PER_BYTE) { 436 idx = ((i + 1) * BITS_PER_BYTE) + idx_start; 437 temp_bpw = bpw; 438 } else { 439 idx = idx + idx_delta; 440 temp_bpw = temp_bpw - BITS_PER_BYTE; 441 } 442 } 443 cfg[iter - 1] |= PACKING_STOP_BIT; 444 cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT); 445 cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT); 446 447 if (tx_cfg) { 448 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); 449 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); 450 } 451 if (rx_cfg) { 452 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); 453 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); 454 } 455 456 /* 457 * Number of protocol words in each FIFO entry 458 * 0 - 4x8, four words in each entry, max word size of 8 bits 459 * 1 - 2x16, two words in each entry, max word size of 16 bits 460 * 2 - 1x32, one word in each entry, max word size of 32 bits 461 * 3 - undefined 462 */ 463 if (pack_words || bpw == 32) 464 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN); 465 } 466 EXPORT_SYMBOL(geni_se_config_packing); 467 468 static void geni_se_clks_off(struct geni_se *se) 469 { 470 struct geni_wrapper *wrapper = se->wrapper; 471 472 clk_disable_unprepare(se->clk); 473 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), 474 wrapper->ahb_clks); 475 } 476 477 /** 478 * geni_se_resources_off() - Turn off resources associated with the serial 479 * engine 480 * @se: Pointer to the concerned serial engine. 481 * 482 * Return: 0 on success, standard Linux error codes on failure/error. 483 */ 484 int geni_se_resources_off(struct geni_se *se) 485 { 486 int ret; 487 488 if (has_acpi_companion(se->dev)) 489 return 0; 490 491 ret = pinctrl_pm_select_sleep_state(se->dev); 492 if (ret) 493 return ret; 494 495 geni_se_clks_off(se); 496 return 0; 497 } 498 EXPORT_SYMBOL(geni_se_resources_off); 499 500 static int geni_se_clks_on(struct geni_se *se) 501 { 502 int ret; 503 struct geni_wrapper *wrapper = se->wrapper; 504 505 ret = clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks), 506 wrapper->ahb_clks); 507 if (ret) 508 return ret; 509 510 ret = clk_prepare_enable(se->clk); 511 if (ret) 512 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), 513 wrapper->ahb_clks); 514 return ret; 515 } 516 517 /** 518 * geni_se_resources_on() - Turn on resources associated with the serial 519 * engine 520 * @se: Pointer to the concerned serial engine. 521 * 522 * Return: 0 on success, standard Linux error codes on failure/error. 523 */ 524 int geni_se_resources_on(struct geni_se *se) 525 { 526 int ret; 527 528 if (has_acpi_companion(se->dev)) 529 return 0; 530 531 ret = geni_se_clks_on(se); 532 if (ret) 533 return ret; 534 535 ret = pinctrl_pm_select_default_state(se->dev); 536 if (ret) 537 geni_se_clks_off(se); 538 539 return ret; 540 } 541 EXPORT_SYMBOL(geni_se_resources_on); 542 543 /** 544 * geni_se_clk_tbl_get() - Get the clock table to program DFS 545 * @se: Pointer to the concerned serial engine. 546 * @tbl: Table in which the output is returned. 547 * 548 * This function is called by the protocol drivers to determine the different 549 * clock frequencies supported by serial engine core clock. The protocol 550 * drivers use the output to determine the clock frequency index to be 551 * programmed into DFS. 552 * 553 * Return: number of valid performance levels in the table on success, 554 * standard Linux error codes on failure. 555 */ 556 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl) 557 { 558 long freq = 0; 559 int i; 560 561 if (se->clk_perf_tbl) { 562 *tbl = se->clk_perf_tbl; 563 return se->num_clk_levels; 564 } 565 566 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL, 567 sizeof(*se->clk_perf_tbl), 568 GFP_KERNEL); 569 if (!se->clk_perf_tbl) 570 return -ENOMEM; 571 572 for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) { 573 freq = clk_round_rate(se->clk, freq + 1); 574 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1]) 575 break; 576 se->clk_perf_tbl[i] = freq; 577 } 578 se->num_clk_levels = i; 579 *tbl = se->clk_perf_tbl; 580 return se->num_clk_levels; 581 } 582 EXPORT_SYMBOL(geni_se_clk_tbl_get); 583 584 /** 585 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency 586 * @se: Pointer to the concerned serial engine. 587 * @req_freq: Requested clock frequency. 588 * @index: Index of the resultant frequency in the table. 589 * @res_freq: Resultant frequency of the source clock. 590 * @exact: Flag to indicate exact multiple requirement of the requested 591 * frequency. 592 * 593 * This function is called by the protocol drivers to determine the best match 594 * of the requested frequency as provided by the serial engine clock in order 595 * to meet the performance requirements. 596 * 597 * If we return success: 598 * - if @exact is true then @res_freq / <an_integer> == @req_freq 599 * - if @exact is false then @res_freq / <an_integer> <= @req_freq 600 * 601 * Return: 0 on success, standard Linux error codes on failure. 602 */ 603 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, 604 unsigned int *index, unsigned long *res_freq, 605 bool exact) 606 { 607 unsigned long *tbl; 608 int num_clk_levels; 609 int i; 610 unsigned long best_delta; 611 unsigned long new_delta; 612 unsigned int divider; 613 614 num_clk_levels = geni_se_clk_tbl_get(se, &tbl); 615 if (num_clk_levels < 0) 616 return num_clk_levels; 617 618 if (num_clk_levels == 0) 619 return -EINVAL; 620 621 best_delta = ULONG_MAX; 622 for (i = 0; i < num_clk_levels; i++) { 623 divider = DIV_ROUND_UP(tbl[i], req_freq); 624 new_delta = req_freq - tbl[i] / divider; 625 if (new_delta < best_delta) { 626 /* We have a new best! */ 627 *index = i; 628 *res_freq = tbl[i]; 629 630 /* If the new best is exact then we're done */ 631 if (new_delta == 0) 632 return 0; 633 634 /* Record how close we got */ 635 best_delta = new_delta; 636 } 637 } 638 639 if (exact) 640 return -EINVAL; 641 642 return 0; 643 } 644 EXPORT_SYMBOL(geni_se_clk_freq_match); 645 646 #define GENI_SE_DMA_DONE_EN BIT(0) 647 #define GENI_SE_DMA_EOT_EN BIT(1) 648 #define GENI_SE_DMA_AHB_ERR_EN BIT(2) 649 #define GENI_SE_DMA_EOT_BUF BIT(0) 650 /** 651 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer 652 * @se: Pointer to the concerned serial engine. 653 * @buf: Pointer to the TX buffer. 654 * @len: Length of the TX buffer. 655 * @iova: Pointer to store the mapped DMA address. 656 * 657 * This function is used to prepare the buffers for DMA TX. 658 * 659 * Return: 0 on success, standard Linux error codes on failure. 660 */ 661 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, 662 dma_addr_t *iova) 663 { 664 struct geni_wrapper *wrapper = se->wrapper; 665 u32 val; 666 667 if (!wrapper) 668 return -EINVAL; 669 670 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE); 671 if (dma_mapping_error(wrapper->dev, *iova)) 672 return -EIO; 673 674 val = GENI_SE_DMA_DONE_EN; 675 val |= GENI_SE_DMA_EOT_EN; 676 val |= GENI_SE_DMA_AHB_ERR_EN; 677 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); 678 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L); 679 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H); 680 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); 681 writel(len, se->base + SE_DMA_TX_LEN); 682 return 0; 683 } 684 EXPORT_SYMBOL(geni_se_tx_dma_prep); 685 686 /** 687 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer 688 * @se: Pointer to the concerned serial engine. 689 * @buf: Pointer to the RX buffer. 690 * @len: Length of the RX buffer. 691 * @iova: Pointer to store the mapped DMA address. 692 * 693 * This function is used to prepare the buffers for DMA RX. 694 * 695 * Return: 0 on success, standard Linux error codes on failure. 696 */ 697 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, 698 dma_addr_t *iova) 699 { 700 struct geni_wrapper *wrapper = se->wrapper; 701 u32 val; 702 703 if (!wrapper) 704 return -EINVAL; 705 706 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE); 707 if (dma_mapping_error(wrapper->dev, *iova)) 708 return -EIO; 709 710 val = GENI_SE_DMA_DONE_EN; 711 val |= GENI_SE_DMA_EOT_EN; 712 val |= GENI_SE_DMA_AHB_ERR_EN; 713 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); 714 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L); 715 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H); 716 /* RX does not have EOT buffer type bit. So just reset RX_ATTR */ 717 writel_relaxed(0, se->base + SE_DMA_RX_ATTR); 718 writel(len, se->base + SE_DMA_RX_LEN); 719 return 0; 720 } 721 EXPORT_SYMBOL(geni_se_rx_dma_prep); 722 723 /** 724 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer 725 * @se: Pointer to the concerned serial engine. 726 * @iova: DMA address of the TX buffer. 727 * @len: Length of the TX buffer. 728 * 729 * This function is used to unprepare the DMA buffers after DMA TX. 730 */ 731 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) 732 { 733 struct geni_wrapper *wrapper = se->wrapper; 734 735 if (iova && !dma_mapping_error(wrapper->dev, iova)) 736 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE); 737 } 738 EXPORT_SYMBOL(geni_se_tx_dma_unprep); 739 740 /** 741 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer 742 * @se: Pointer to the concerned serial engine. 743 * @iova: DMA address of the RX buffer. 744 * @len: Length of the RX buffer. 745 * 746 * This function is used to unprepare the DMA buffers after DMA RX. 747 */ 748 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) 749 { 750 struct geni_wrapper *wrapper = se->wrapper; 751 752 if (iova && !dma_mapping_error(wrapper->dev, iova)) 753 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE); 754 } 755 EXPORT_SYMBOL(geni_se_rx_dma_unprep); 756 757 int geni_icc_get(struct geni_se *se, const char *icc_ddr) 758 { 759 int i, err; 760 const char *icc_names[] = {"qup-core", "qup-config", icc_ddr}; 761 762 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 763 if (!icc_names[i]) 764 continue; 765 766 se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]); 767 if (IS_ERR(se->icc_paths[i].path)) 768 goto err; 769 } 770 771 return 0; 772 773 err: 774 err = PTR_ERR(se->icc_paths[i].path); 775 if (err != -EPROBE_DEFER) 776 dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n", 777 icc_names[i], err); 778 return err; 779 780 } 781 EXPORT_SYMBOL(geni_icc_get); 782 783 int geni_icc_set_bw(struct geni_se *se) 784 { 785 int i, ret; 786 787 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 788 ret = icc_set_bw(se->icc_paths[i].path, 789 se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw); 790 if (ret) { 791 dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n", 792 icc_path_names[i], ret); 793 return ret; 794 } 795 } 796 797 return 0; 798 } 799 EXPORT_SYMBOL(geni_icc_set_bw); 800 801 void geni_icc_set_tag(struct geni_se *se, u32 tag) 802 { 803 int i; 804 805 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) 806 icc_set_tag(se->icc_paths[i].path, tag); 807 } 808 EXPORT_SYMBOL(geni_icc_set_tag); 809 810 /* To do: Replace this by icc_bulk_enable once it's implemented in ICC core */ 811 int geni_icc_enable(struct geni_se *se) 812 { 813 int i, ret; 814 815 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 816 ret = icc_enable(se->icc_paths[i].path); 817 if (ret) { 818 dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n", 819 icc_path_names[i], ret); 820 return ret; 821 } 822 } 823 824 return 0; 825 } 826 EXPORT_SYMBOL(geni_icc_enable); 827 828 int geni_icc_disable(struct geni_se *se) 829 { 830 int i, ret; 831 832 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 833 ret = icc_disable(se->icc_paths[i].path); 834 if (ret) { 835 dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n", 836 icc_path_names[i], ret); 837 return ret; 838 } 839 } 840 841 return 0; 842 } 843 EXPORT_SYMBOL(geni_icc_disable); 844 845 void geni_remove_earlycon_icc_vote(void) 846 { 847 struct platform_device *pdev; 848 struct geni_wrapper *wrapper; 849 struct device_node *parent; 850 struct device_node *child; 851 852 if (!earlycon_wrapper) 853 return; 854 855 wrapper = earlycon_wrapper; 856 parent = of_get_next_parent(wrapper->dev->of_node); 857 for_each_child_of_node(parent, child) { 858 if (!of_device_is_compatible(child, "qcom,geni-se-qup")) 859 continue; 860 861 pdev = of_find_device_by_node(child); 862 if (!pdev) 863 continue; 864 865 wrapper = platform_get_drvdata(pdev); 866 icc_put(wrapper->to_core.path); 867 wrapper->to_core.path = NULL; 868 869 } 870 of_node_put(parent); 871 872 earlycon_wrapper = NULL; 873 } 874 EXPORT_SYMBOL(geni_remove_earlycon_icc_vote); 875 876 static int geni_se_probe(struct platform_device *pdev) 877 { 878 struct device *dev = &pdev->dev; 879 struct resource *res; 880 struct geni_wrapper *wrapper; 881 struct console __maybe_unused *bcon; 882 bool __maybe_unused has_earlycon = false; 883 int ret; 884 885 wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL); 886 if (!wrapper) 887 return -ENOMEM; 888 889 wrapper->dev = dev; 890 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 891 wrapper->base = devm_ioremap_resource(dev, res); 892 if (IS_ERR(wrapper->base)) 893 return PTR_ERR(wrapper->base); 894 895 if (!has_acpi_companion(&pdev->dev)) { 896 wrapper->ahb_clks[0].id = "m-ahb"; 897 wrapper->ahb_clks[1].id = "s-ahb"; 898 ret = devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks); 899 if (ret) { 900 dev_err(dev, "Err getting AHB clks %d\n", ret); 901 return ret; 902 } 903 } 904 905 #ifdef CONFIG_SERIAL_EARLYCON 906 for_each_console(bcon) { 907 if (!strcmp(bcon->name, "qcom_geni")) { 908 has_earlycon = true; 909 break; 910 } 911 } 912 if (!has_earlycon) 913 goto exit; 914 915 wrapper->to_core.path = devm_of_icc_get(dev, "qup-core"); 916 if (IS_ERR(wrapper->to_core.path)) 917 return PTR_ERR(wrapper->to_core.path); 918 /* 919 * Put minmal BW request on core clocks on behalf of early console. 920 * The vote will be removed earlycon exit function. 921 * 922 * Note: We are putting vote on each QUP wrapper instead only to which 923 * earlycon is connected because QUP core clock of different wrapper 924 * share same voltage domain. If core1 is put to 0, then core2 will 925 * also run at 0, if not voted. Default ICC vote will be removed ASA 926 * we touch any of the core clock. 927 * core1 = core2 = max(core1, core2) 928 */ 929 ret = icc_set_bw(wrapper->to_core.path, GENI_DEFAULT_BW, 930 GENI_DEFAULT_BW); 931 if (ret) { 932 dev_err(&pdev->dev, "%s: ICC BW voting failed for core: %d\n", 933 __func__, ret); 934 return ret; 935 } 936 937 if (of_get_compatible_child(pdev->dev.of_node, "qcom,geni-debug-uart")) 938 earlycon_wrapper = wrapper; 939 of_node_put(pdev->dev.of_node); 940 exit: 941 #endif 942 dev_set_drvdata(dev, wrapper); 943 dev_dbg(dev, "GENI SE Driver probed\n"); 944 return devm_of_platform_populate(dev); 945 } 946 947 static const struct of_device_id geni_se_dt_match[] = { 948 { .compatible = "qcom,geni-se-qup", }, 949 {} 950 }; 951 MODULE_DEVICE_TABLE(of, geni_se_dt_match); 952 953 static struct platform_driver geni_se_driver = { 954 .driver = { 955 .name = "geni_se_qup", 956 .of_match_table = geni_se_dt_match, 957 }, 958 .probe = geni_se_probe, 959 }; 960 module_platform_driver(geni_se_driver); 961 962 MODULE_DESCRIPTION("GENI Serial Engine Driver"); 963 MODULE_LICENSE("GPL v2"); 964