1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 3 4 #include <linux/acpi.h> 5 #include <linux/clk.h> 6 #include <linux/console.h> 7 #include <linux/slab.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/pinctrl/consumer.h> 14 #include <linux/platform_device.h> 15 #include <linux/qcom-geni-se.h> 16 17 /** 18 * DOC: Overview 19 * 20 * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced 21 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper 22 * controller. QUP Wrapper is designed to support various serial bus protocols 23 * like UART, SPI, I2C, I3C, etc. 24 */ 25 26 /** 27 * DOC: Hardware description 28 * 29 * GENI based QUP is a highly-flexible and programmable module for supporting 30 * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single 31 * QUP module can provide upto 8 serial interfaces, using its internal 32 * serial engines. The actual configuration is determined by the target 33 * platform configuration. The protocol supported by each interface is 34 * determined by the firmware loaded to the serial engine. Each SE consists 35 * of a DMA Engine and GENI sub modules which enable serial engines to 36 * support FIFO and DMA modes of operation. 37 * 38 * 39 * +-----------------------------------------+ 40 * |QUP Wrapper | 41 * | +----------------------------+ | 42 * --QUP & SE Clocks--> | Serial Engine N | +-IO------> 43 * | | ... | | Interface 44 * <---Clock Perf.----+ +----+-----------------------+ | | 45 * State Interface | | Serial Engine 1 | | | 46 * | | | | | 47 * | | | | | 48 * <--------AHB-------> | | | | 49 * | | +----+ | 50 * | | | | 51 * | | | | 52 * <------SE IRQ------+ +----------------------------+ | 53 * | | 54 * +-----------------------------------------+ 55 * 56 * Figure 1: GENI based QUP Wrapper 57 * 58 * The GENI submodules include primary and secondary sequencers which are 59 * used to drive TX & RX operations. On serial interfaces that operate using 60 * master-slave model, primary sequencer drives both TX & RX operations. On 61 * serial interfaces that operate using peer-to-peer model, primary sequencer 62 * drives TX operation and secondary sequencer drives RX operation. 63 */ 64 65 /** 66 * DOC: Software description 67 * 68 * GENI SE Wrapper driver is structured into 2 parts: 69 * 70 * geni_wrapper represents QUP Wrapper controller. This part of the driver 71 * manages QUP Wrapper information such as hardware version, clock 72 * performance table that is common to all the internal serial engines. 73 * 74 * geni_se represents serial engine. This part of the driver manages serial 75 * engine information such as clocks, containing QUP Wrapper, etc. This part 76 * of driver also supports operations (eg. initialize the concerned serial 77 * engine, select between FIFO and DMA mode of operation etc.) that are 78 * common to all the serial engines and are independent of serial interfaces. 79 */ 80 81 #define MAX_CLK_PERF_LEVEL 32 82 #define NUM_AHB_CLKS 2 83 84 /** 85 * @struct geni_wrapper - Data structure to represent the QUP Wrapper Core 86 * @dev: Device pointer of the QUP wrapper core 87 * @base: Base address of this instance of QUP wrapper core 88 * @ahb_clks: Handle to the primary & secondary AHB clocks 89 */ 90 struct geni_wrapper { 91 struct device *dev; 92 void __iomem *base; 93 struct clk_bulk_data ahb_clks[NUM_AHB_CLKS]; 94 struct geni_icc_path to_core; 95 }; 96 97 static const char * const icc_path_names[] = {"qup-core", "qup-config", 98 "qup-memory"}; 99 100 static struct geni_wrapper *earlycon_wrapper; 101 102 #define QUP_HW_VER_REG 0x4 103 104 /* Common SE registers */ 105 #define GENI_INIT_CFG_REVISION 0x0 106 #define GENI_S_INIT_CFG_REVISION 0x4 107 #define GENI_OUTPUT_CTRL 0x24 108 #define GENI_CGC_CTRL 0x28 109 #define GENI_CLK_CTRL_RO 0x60 110 #define GENI_IF_DISABLE_RO 0x64 111 #define GENI_FW_S_REVISION_RO 0x6c 112 #define SE_GENI_BYTE_GRAN 0x254 113 #define SE_GENI_TX_PACKING_CFG0 0x260 114 #define SE_GENI_TX_PACKING_CFG1 0x264 115 #define SE_GENI_RX_PACKING_CFG0 0x284 116 #define SE_GENI_RX_PACKING_CFG1 0x288 117 #define SE_GENI_M_GP_LENGTH 0x910 118 #define SE_GENI_S_GP_LENGTH 0x914 119 #define SE_DMA_TX_PTR_L 0xc30 120 #define SE_DMA_TX_PTR_H 0xc34 121 #define SE_DMA_TX_ATTR 0xc38 122 #define SE_DMA_TX_LEN 0xc3c 123 #define SE_DMA_TX_IRQ_EN 0xc48 124 #define SE_DMA_TX_IRQ_EN_SET 0xc4c 125 #define SE_DMA_TX_IRQ_EN_CLR 0xc50 126 #define SE_DMA_TX_LEN_IN 0xc54 127 #define SE_DMA_TX_MAX_BURST 0xc5c 128 #define SE_DMA_RX_PTR_L 0xd30 129 #define SE_DMA_RX_PTR_H 0xd34 130 #define SE_DMA_RX_ATTR 0xd38 131 #define SE_DMA_RX_LEN 0xd3c 132 #define SE_DMA_RX_IRQ_EN 0xd48 133 #define SE_DMA_RX_IRQ_EN_SET 0xd4c 134 #define SE_DMA_RX_IRQ_EN_CLR 0xd50 135 #define SE_DMA_RX_LEN_IN 0xd54 136 #define SE_DMA_RX_MAX_BURST 0xd5c 137 #define SE_DMA_RX_FLUSH 0xd60 138 #define SE_GSI_EVENT_EN 0xe18 139 #define SE_IRQ_EN 0xe1c 140 #define SE_DMA_GENERAL_CFG 0xe30 141 142 /* GENI_OUTPUT_CTRL fields */ 143 #define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0) 144 145 /* GENI_CGC_CTRL fields */ 146 #define CFG_AHB_CLK_CGC_ON BIT(0) 147 #define CFG_AHB_WR_ACLK_CGC_ON BIT(1) 148 #define DATA_AHB_CLK_CGC_ON BIT(2) 149 #define SCLK_CGC_ON BIT(3) 150 #define TX_CLK_CGC_ON BIT(4) 151 #define RX_CLK_CGC_ON BIT(5) 152 #define EXT_CLK_CGC_ON BIT(6) 153 #define PROG_RAM_HCLK_OFF BIT(8) 154 #define PROG_RAM_SCLK_OFF BIT(9) 155 #define DEFAULT_CGC_EN GENMASK(6, 0) 156 157 /* SE_GSI_EVENT_EN fields */ 158 #define DMA_RX_EVENT_EN BIT(0) 159 #define DMA_TX_EVENT_EN BIT(1) 160 #define GENI_M_EVENT_EN BIT(2) 161 #define GENI_S_EVENT_EN BIT(3) 162 163 /* SE_IRQ_EN fields */ 164 #define DMA_RX_IRQ_EN BIT(0) 165 #define DMA_TX_IRQ_EN BIT(1) 166 #define GENI_M_IRQ_EN BIT(2) 167 #define GENI_S_IRQ_EN BIT(3) 168 169 /* SE_DMA_GENERAL_CFG */ 170 #define DMA_RX_CLK_CGC_ON BIT(0) 171 #define DMA_TX_CLK_CGC_ON BIT(1) 172 #define DMA_AHB_SLV_CFG_ON BIT(2) 173 #define AHB_SEC_SLV_CLK_CGC_ON BIT(3) 174 #define DUMMY_RX_NON_BUFFERABLE BIT(4) 175 #define RX_DMA_ZERO_PADDING_EN BIT(5) 176 #define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6) 177 #define RX_DMA_IRQ_DELAY_SHFT 6 178 179 /** 180 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version 181 * @se: Pointer to the corresponding serial engine. 182 * 183 * Return: Hardware Version of the wrapper. 184 */ 185 u32 geni_se_get_qup_hw_version(struct geni_se *se) 186 { 187 struct geni_wrapper *wrapper = se->wrapper; 188 189 return readl_relaxed(wrapper->base + QUP_HW_VER_REG); 190 } 191 EXPORT_SYMBOL(geni_se_get_qup_hw_version); 192 193 static void geni_se_io_set_mode(void __iomem *base) 194 { 195 u32 val; 196 197 val = readl_relaxed(base + SE_IRQ_EN); 198 val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN; 199 val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN; 200 writel_relaxed(val, base + SE_IRQ_EN); 201 202 val = readl_relaxed(base + SE_GENI_DMA_MODE_EN); 203 val &= ~GENI_DMA_MODE_EN; 204 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN); 205 206 writel_relaxed(0, base + SE_GSI_EVENT_EN); 207 } 208 209 static void geni_se_io_init(void __iomem *base) 210 { 211 u32 val; 212 213 val = readl_relaxed(base + GENI_CGC_CTRL); 214 val |= DEFAULT_CGC_EN; 215 writel_relaxed(val, base + GENI_CGC_CTRL); 216 217 val = readl_relaxed(base + SE_DMA_GENERAL_CFG); 218 val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON; 219 val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON; 220 writel_relaxed(val, base + SE_DMA_GENERAL_CFG); 221 222 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL); 223 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG); 224 } 225 226 static void geni_se_irq_clear(struct geni_se *se) 227 { 228 writel_relaxed(0, se->base + SE_GSI_EVENT_EN); 229 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR); 230 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR); 231 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR); 232 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR); 233 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN); 234 } 235 236 /** 237 * geni_se_init() - Initialize the GENI serial engine 238 * @se: Pointer to the concerned serial engine. 239 * @rx_wm: Receive watermark, in units of FIFO words. 240 * @rx_rfr_wm: Ready-for-receive watermark, in units of FIFO words. 241 * 242 * This function is used to initialize the GENI serial engine, configure 243 * receive watermark and ready-for-receive watermarks. 244 */ 245 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr) 246 { 247 u32 val; 248 249 geni_se_irq_clear(se); 250 geni_se_io_init(se->base); 251 geni_se_io_set_mode(se->base); 252 253 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG); 254 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG); 255 256 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 257 val |= M_COMMON_GENI_M_IRQ_EN; 258 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 259 260 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 261 val |= S_COMMON_GENI_S_IRQ_EN; 262 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 263 } 264 EXPORT_SYMBOL(geni_se_init); 265 266 static void geni_se_select_fifo_mode(struct geni_se *se) 267 { 268 u32 proto = geni_se_read_proto(se); 269 u32 val; 270 271 geni_se_irq_clear(se); 272 273 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 274 if (proto != GENI_SE_UART) { 275 val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN; 276 val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 277 } 278 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 279 280 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 281 if (proto != GENI_SE_UART) 282 val |= S_CMD_DONE_EN; 283 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 284 285 val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 286 val &= ~GENI_DMA_MODE_EN; 287 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 288 } 289 290 static void geni_se_select_dma_mode(struct geni_se *se) 291 { 292 u32 val; 293 294 geni_se_irq_clear(se); 295 296 val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 297 val |= GENI_DMA_MODE_EN; 298 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 299 } 300 301 /** 302 * geni_se_select_mode() - Select the serial engine transfer mode 303 * @se: Pointer to the concerned serial engine. 304 * @mode: Transfer mode to be selected. 305 */ 306 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode) 307 { 308 WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA); 309 310 switch (mode) { 311 case GENI_SE_FIFO: 312 geni_se_select_fifo_mode(se); 313 break; 314 case GENI_SE_DMA: 315 geni_se_select_dma_mode(se); 316 break; 317 case GENI_SE_INVALID: 318 default: 319 break; 320 } 321 } 322 EXPORT_SYMBOL(geni_se_select_mode); 323 324 /** 325 * DOC: Overview 326 * 327 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist 328 * of up to 4 operations, each operation represented by 4 configuration vectors 329 * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for 330 * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO. 331 * Refer to below examples for detailed bit-field description. 332 * 333 * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1 334 * 335 * +-----------+-------+-------+-------+-------+ 336 * | | vec_0 | vec_1 | vec_2 | vec_3 | 337 * +-----------+-------+-------+-------+-------+ 338 * | start | 0x6 | 0xe | 0x16 | 0x1e | 339 * | direction | 1 | 1 | 1 | 1 | 340 * | length | 6 | 6 | 6 | 6 | 341 * | stop | 0 | 0 | 0 | 1 | 342 * +-----------+-------+-------+-------+-------+ 343 * 344 * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0 345 * 346 * +-----------+-------+-------+-------+-------+ 347 * | | vec_0 | vec_1 | vec_2 | vec_3 | 348 * +-----------+-------+-------+-------+-------+ 349 * | start | 0x0 | 0x8 | 0x10 | 0x18 | 350 * | direction | 0 | 0 | 0 | 0 | 351 * | length | 7 | 6 | 7 | 6 | 352 * | stop | 0 | 0 | 0 | 1 | 353 * +-----------+-------+-------+-------+-------+ 354 * 355 * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1 356 * 357 * +-----------+-------+-------+-------+-------+ 358 * | | vec_0 | vec_1 | vec_2 | vec_3 | 359 * +-----------+-------+-------+-------+-------+ 360 * | start | 0x16 | 0xe | 0x6 | 0x0 | 361 * | direction | 1 | 1 | 1 | 1 | 362 * | length | 7 | 7 | 6 | 0 | 363 * | stop | 0 | 0 | 1 | 0 | 364 * +-----------+-------+-------+-------+-------+ 365 * 366 */ 367 368 #define NUM_PACKING_VECTORS 4 369 #define PACKING_START_SHIFT 5 370 #define PACKING_DIR_SHIFT 4 371 #define PACKING_LEN_SHIFT 1 372 #define PACKING_STOP_BIT BIT(0) 373 #define PACKING_VECTOR_SHIFT 10 374 /** 375 * geni_se_config_packing() - Packing configuration of the serial engine 376 * @se: Pointer to the concerned serial engine 377 * @bpw: Bits of data per transfer word. 378 * @pack_words: Number of words per fifo element. 379 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa. 380 * @tx_cfg: Flag to configure the TX Packing. 381 * @rx_cfg: Flag to configure the RX Packing. 382 * 383 * This function is used to configure the packing rules for the current 384 * transfer. 385 */ 386 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words, 387 bool msb_to_lsb, bool tx_cfg, bool rx_cfg) 388 { 389 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0}; 390 int len; 391 int temp_bpw = bpw; 392 int idx_start = msb_to_lsb ? bpw - 1 : 0; 393 int idx = idx_start; 394 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE; 395 int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE); 396 int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE; 397 int i; 398 399 if (iter <= 0 || iter > NUM_PACKING_VECTORS) 400 return; 401 402 for (i = 0; i < iter; i++) { 403 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1; 404 cfg[i] = idx << PACKING_START_SHIFT; 405 cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT; 406 cfg[i] |= len << PACKING_LEN_SHIFT; 407 408 if (temp_bpw <= BITS_PER_BYTE) { 409 idx = ((i + 1) * BITS_PER_BYTE) + idx_start; 410 temp_bpw = bpw; 411 } else { 412 idx = idx + idx_delta; 413 temp_bpw = temp_bpw - BITS_PER_BYTE; 414 } 415 } 416 cfg[iter - 1] |= PACKING_STOP_BIT; 417 cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT); 418 cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT); 419 420 if (tx_cfg) { 421 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); 422 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); 423 } 424 if (rx_cfg) { 425 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); 426 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); 427 } 428 429 /* 430 * Number of protocol words in each FIFO entry 431 * 0 - 4x8, four words in each entry, max word size of 8 bits 432 * 1 - 2x16, two words in each entry, max word size of 16 bits 433 * 2 - 1x32, one word in each entry, max word size of 32 bits 434 * 3 - undefined 435 */ 436 if (pack_words || bpw == 32) 437 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN); 438 } 439 EXPORT_SYMBOL(geni_se_config_packing); 440 441 static void geni_se_clks_off(struct geni_se *se) 442 { 443 struct geni_wrapper *wrapper = se->wrapper; 444 445 clk_disable_unprepare(se->clk); 446 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), 447 wrapper->ahb_clks); 448 } 449 450 /** 451 * geni_se_resources_off() - Turn off resources associated with the serial 452 * engine 453 * @se: Pointer to the concerned serial engine. 454 * 455 * Return: 0 on success, standard Linux error codes on failure/error. 456 */ 457 int geni_se_resources_off(struct geni_se *se) 458 { 459 int ret; 460 461 if (has_acpi_companion(se->dev)) 462 return 0; 463 464 ret = pinctrl_pm_select_sleep_state(se->dev); 465 if (ret) 466 return ret; 467 468 geni_se_clks_off(se); 469 return 0; 470 } 471 EXPORT_SYMBOL(geni_se_resources_off); 472 473 static int geni_se_clks_on(struct geni_se *se) 474 { 475 int ret; 476 struct geni_wrapper *wrapper = se->wrapper; 477 478 ret = clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks), 479 wrapper->ahb_clks); 480 if (ret) 481 return ret; 482 483 ret = clk_prepare_enable(se->clk); 484 if (ret) 485 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), 486 wrapper->ahb_clks); 487 return ret; 488 } 489 490 /** 491 * geni_se_resources_on() - Turn on resources associated with the serial 492 * engine 493 * @se: Pointer to the concerned serial engine. 494 * 495 * Return: 0 on success, standard Linux error codes on failure/error. 496 */ 497 int geni_se_resources_on(struct geni_se *se) 498 { 499 int ret; 500 501 if (has_acpi_companion(se->dev)) 502 return 0; 503 504 ret = geni_se_clks_on(se); 505 if (ret) 506 return ret; 507 508 ret = pinctrl_pm_select_default_state(se->dev); 509 if (ret) 510 geni_se_clks_off(se); 511 512 return ret; 513 } 514 EXPORT_SYMBOL(geni_se_resources_on); 515 516 /** 517 * geni_se_clk_tbl_get() - Get the clock table to program DFS 518 * @se: Pointer to the concerned serial engine. 519 * @tbl: Table in which the output is returned. 520 * 521 * This function is called by the protocol drivers to determine the different 522 * clock frequencies supported by serial engine core clock. The protocol 523 * drivers use the output to determine the clock frequency index to be 524 * programmed into DFS. 525 * 526 * Return: number of valid performance levels in the table on success, 527 * standard Linux error codes on failure. 528 */ 529 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl) 530 { 531 long freq = 0; 532 int i; 533 534 if (se->clk_perf_tbl) { 535 *tbl = se->clk_perf_tbl; 536 return se->num_clk_levels; 537 } 538 539 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL, 540 sizeof(*se->clk_perf_tbl), 541 GFP_KERNEL); 542 if (!se->clk_perf_tbl) 543 return -ENOMEM; 544 545 for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) { 546 freq = clk_round_rate(se->clk, freq + 1); 547 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1]) 548 break; 549 se->clk_perf_tbl[i] = freq; 550 } 551 se->num_clk_levels = i; 552 *tbl = se->clk_perf_tbl; 553 return se->num_clk_levels; 554 } 555 EXPORT_SYMBOL(geni_se_clk_tbl_get); 556 557 /** 558 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency 559 * @se: Pointer to the concerned serial engine. 560 * @req_freq: Requested clock frequency. 561 * @index: Index of the resultant frequency in the table. 562 * @res_freq: Resultant frequency of the source clock. 563 * @exact: Flag to indicate exact multiple requirement of the requested 564 * frequency. 565 * 566 * This function is called by the protocol drivers to determine the best match 567 * of the requested frequency as provided by the serial engine clock in order 568 * to meet the performance requirements. 569 * 570 * If we return success: 571 * - if @exact is true then @res_freq / <an_integer> == @req_freq 572 * - if @exact is false then @res_freq / <an_integer> <= @req_freq 573 * 574 * Return: 0 on success, standard Linux error codes on failure. 575 */ 576 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, 577 unsigned int *index, unsigned long *res_freq, 578 bool exact) 579 { 580 unsigned long *tbl; 581 int num_clk_levels; 582 int i; 583 unsigned long best_delta; 584 unsigned long new_delta; 585 unsigned int divider; 586 587 num_clk_levels = geni_se_clk_tbl_get(se, &tbl); 588 if (num_clk_levels < 0) 589 return num_clk_levels; 590 591 if (num_clk_levels == 0) 592 return -EINVAL; 593 594 best_delta = ULONG_MAX; 595 for (i = 0; i < num_clk_levels; i++) { 596 divider = DIV_ROUND_UP(tbl[i], req_freq); 597 new_delta = req_freq - tbl[i] / divider; 598 if (new_delta < best_delta) { 599 /* We have a new best! */ 600 *index = i; 601 *res_freq = tbl[i]; 602 603 /* If the new best is exact then we're done */ 604 if (new_delta == 0) 605 return 0; 606 607 /* Record how close we got */ 608 best_delta = new_delta; 609 } 610 } 611 612 if (exact) 613 return -EINVAL; 614 615 return 0; 616 } 617 EXPORT_SYMBOL(geni_se_clk_freq_match); 618 619 #define GENI_SE_DMA_DONE_EN BIT(0) 620 #define GENI_SE_DMA_EOT_EN BIT(1) 621 #define GENI_SE_DMA_AHB_ERR_EN BIT(2) 622 #define GENI_SE_DMA_EOT_BUF BIT(0) 623 /** 624 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer 625 * @se: Pointer to the concerned serial engine. 626 * @buf: Pointer to the TX buffer. 627 * @len: Length of the TX buffer. 628 * @iova: Pointer to store the mapped DMA address. 629 * 630 * This function is used to prepare the buffers for DMA TX. 631 * 632 * Return: 0 on success, standard Linux error codes on failure. 633 */ 634 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, 635 dma_addr_t *iova) 636 { 637 struct geni_wrapper *wrapper = se->wrapper; 638 u32 val; 639 640 if (!wrapper) 641 return -EINVAL; 642 643 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE); 644 if (dma_mapping_error(wrapper->dev, *iova)) 645 return -EIO; 646 647 val = GENI_SE_DMA_DONE_EN; 648 val |= GENI_SE_DMA_EOT_EN; 649 val |= GENI_SE_DMA_AHB_ERR_EN; 650 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); 651 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L); 652 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H); 653 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); 654 writel_relaxed(len, se->base + SE_DMA_TX_LEN); 655 return 0; 656 } 657 EXPORT_SYMBOL(geni_se_tx_dma_prep); 658 659 /** 660 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer 661 * @se: Pointer to the concerned serial engine. 662 * @buf: Pointer to the RX buffer. 663 * @len: Length of the RX buffer. 664 * @iova: Pointer to store the mapped DMA address. 665 * 666 * This function is used to prepare the buffers for DMA RX. 667 * 668 * Return: 0 on success, standard Linux error codes on failure. 669 */ 670 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, 671 dma_addr_t *iova) 672 { 673 struct geni_wrapper *wrapper = se->wrapper; 674 u32 val; 675 676 if (!wrapper) 677 return -EINVAL; 678 679 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE); 680 if (dma_mapping_error(wrapper->dev, *iova)) 681 return -EIO; 682 683 val = GENI_SE_DMA_DONE_EN; 684 val |= GENI_SE_DMA_EOT_EN; 685 val |= GENI_SE_DMA_AHB_ERR_EN; 686 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); 687 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L); 688 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H); 689 /* RX does not have EOT buffer type bit. So just reset RX_ATTR */ 690 writel_relaxed(0, se->base + SE_DMA_RX_ATTR); 691 writel_relaxed(len, se->base + SE_DMA_RX_LEN); 692 return 0; 693 } 694 EXPORT_SYMBOL(geni_se_rx_dma_prep); 695 696 /** 697 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer 698 * @se: Pointer to the concerned serial engine. 699 * @iova: DMA address of the TX buffer. 700 * @len: Length of the TX buffer. 701 * 702 * This function is used to unprepare the DMA buffers after DMA TX. 703 */ 704 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) 705 { 706 struct geni_wrapper *wrapper = se->wrapper; 707 708 if (iova && !dma_mapping_error(wrapper->dev, iova)) 709 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE); 710 } 711 EXPORT_SYMBOL(geni_se_tx_dma_unprep); 712 713 /** 714 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer 715 * @se: Pointer to the concerned serial engine. 716 * @iova: DMA address of the RX buffer. 717 * @len: Length of the RX buffer. 718 * 719 * This function is used to unprepare the DMA buffers after DMA RX. 720 */ 721 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) 722 { 723 struct geni_wrapper *wrapper = se->wrapper; 724 725 if (iova && !dma_mapping_error(wrapper->dev, iova)) 726 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE); 727 } 728 EXPORT_SYMBOL(geni_se_rx_dma_unprep); 729 730 int geni_icc_get(struct geni_se *se, const char *icc_ddr) 731 { 732 int i, err; 733 const char *icc_names[] = {"qup-core", "qup-config", icc_ddr}; 734 735 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 736 if (!icc_names[i]) 737 continue; 738 739 se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]); 740 if (IS_ERR(se->icc_paths[i].path)) 741 goto err; 742 } 743 744 return 0; 745 746 err: 747 err = PTR_ERR(se->icc_paths[i].path); 748 if (err != -EPROBE_DEFER) 749 dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n", 750 icc_names[i], err); 751 return err; 752 753 } 754 EXPORT_SYMBOL(geni_icc_get); 755 756 int geni_icc_set_bw(struct geni_se *se) 757 { 758 int i, ret; 759 760 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 761 ret = icc_set_bw(se->icc_paths[i].path, 762 se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw); 763 if (ret) { 764 dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n", 765 icc_path_names[i], ret); 766 return ret; 767 } 768 } 769 770 return 0; 771 } 772 EXPORT_SYMBOL(geni_icc_set_bw); 773 774 void geni_icc_set_tag(struct geni_se *se, u32 tag) 775 { 776 int i; 777 778 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) 779 icc_set_tag(se->icc_paths[i].path, tag); 780 } 781 EXPORT_SYMBOL(geni_icc_set_tag); 782 783 /* To do: Replace this by icc_bulk_enable once it's implemented in ICC core */ 784 int geni_icc_enable(struct geni_se *se) 785 { 786 int i, ret; 787 788 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 789 ret = icc_enable(se->icc_paths[i].path); 790 if (ret) { 791 dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n", 792 icc_path_names[i], ret); 793 return ret; 794 } 795 } 796 797 return 0; 798 } 799 EXPORT_SYMBOL(geni_icc_enable); 800 801 int geni_icc_disable(struct geni_se *se) 802 { 803 int i, ret; 804 805 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 806 ret = icc_disable(se->icc_paths[i].path); 807 if (ret) { 808 dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n", 809 icc_path_names[i], ret); 810 return ret; 811 } 812 } 813 814 return 0; 815 } 816 EXPORT_SYMBOL(geni_icc_disable); 817 818 void geni_remove_earlycon_icc_vote(void) 819 { 820 struct platform_device *pdev; 821 struct geni_wrapper *wrapper; 822 struct device_node *parent; 823 struct device_node *child; 824 825 if (!earlycon_wrapper) 826 return; 827 828 wrapper = earlycon_wrapper; 829 parent = of_get_next_parent(wrapper->dev->of_node); 830 for_each_child_of_node(parent, child) { 831 if (!of_device_is_compatible(child, "qcom,geni-se-qup")) 832 continue; 833 834 pdev = of_find_device_by_node(child); 835 if (!pdev) 836 continue; 837 838 wrapper = platform_get_drvdata(pdev); 839 icc_put(wrapper->to_core.path); 840 wrapper->to_core.path = NULL; 841 842 } 843 of_node_put(parent); 844 845 earlycon_wrapper = NULL; 846 } 847 EXPORT_SYMBOL(geni_remove_earlycon_icc_vote); 848 849 static int geni_se_probe(struct platform_device *pdev) 850 { 851 struct device *dev = &pdev->dev; 852 struct resource *res; 853 struct geni_wrapper *wrapper; 854 struct console __maybe_unused *bcon; 855 bool __maybe_unused has_earlycon = false; 856 int ret; 857 858 wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL); 859 if (!wrapper) 860 return -ENOMEM; 861 862 wrapper->dev = dev; 863 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 864 wrapper->base = devm_ioremap_resource(dev, res); 865 if (IS_ERR(wrapper->base)) 866 return PTR_ERR(wrapper->base); 867 868 if (!has_acpi_companion(&pdev->dev)) { 869 wrapper->ahb_clks[0].id = "m-ahb"; 870 wrapper->ahb_clks[1].id = "s-ahb"; 871 ret = devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks); 872 if (ret) { 873 dev_err(dev, "Err getting AHB clks %d\n", ret); 874 return ret; 875 } 876 } 877 878 #ifdef CONFIG_SERIAL_EARLYCON 879 for_each_console(bcon) { 880 if (!strcmp(bcon->name, "qcom_geni")) { 881 has_earlycon = true; 882 break; 883 } 884 } 885 if (!has_earlycon) 886 goto exit; 887 888 wrapper->to_core.path = devm_of_icc_get(dev, "qup-core"); 889 if (IS_ERR(wrapper->to_core.path)) 890 return PTR_ERR(wrapper->to_core.path); 891 /* 892 * Put minmal BW request on core clocks on behalf of early console. 893 * The vote will be removed earlycon exit function. 894 * 895 * Note: We are putting vote on each QUP wrapper instead only to which 896 * earlycon is connected because QUP core clock of different wrapper 897 * share same voltage domain. If core1 is put to 0, then core2 will 898 * also run at 0, if not voted. Default ICC vote will be removed ASA 899 * we touch any of the core clock. 900 * core1 = core2 = max(core1, core2) 901 */ 902 ret = icc_set_bw(wrapper->to_core.path, GENI_DEFAULT_BW, 903 GENI_DEFAULT_BW); 904 if (ret) { 905 dev_err(&pdev->dev, "%s: ICC BW voting failed for core: %d\n", 906 __func__, ret); 907 return ret; 908 } 909 910 if (of_get_compatible_child(pdev->dev.of_node, "qcom,geni-debug-uart")) 911 earlycon_wrapper = wrapper; 912 of_node_put(pdev->dev.of_node); 913 exit: 914 #endif 915 dev_set_drvdata(dev, wrapper); 916 dev_dbg(dev, "GENI SE Driver probed\n"); 917 return devm_of_platform_populate(dev); 918 } 919 920 static const struct of_device_id geni_se_dt_match[] = { 921 { .compatible = "qcom,geni-se-qup", }, 922 {} 923 }; 924 MODULE_DEVICE_TABLE(of, geni_se_dt_match); 925 926 static struct platform_driver geni_se_driver = { 927 .driver = { 928 .name = "geni_se_qup", 929 .of_match_table = geni_se_dt_match, 930 }, 931 .probe = geni_se_probe, 932 }; 933 module_platform_driver(geni_se_driver); 934 935 MODULE_DESCRIPTION("GENI Serial Engine Driver"); 936 MODULE_LICENSE("GPL v2"); 937