1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 3 4 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ 5 #define __DISABLE_TRACE_MMIO__ 6 7 #include <linux/acpi.h> 8 #include <linux/clk.h> 9 #include <linux/slab.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_platform.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/platform_device.h> 17 #include <linux/soc/qcom/geni-se.h> 18 19 /** 20 * DOC: Overview 21 * 22 * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced 23 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper 24 * controller. QUP Wrapper is designed to support various serial bus protocols 25 * like UART, SPI, I2C, I3C, etc. 26 */ 27 28 /** 29 * DOC: Hardware description 30 * 31 * GENI based QUP is a highly-flexible and programmable module for supporting 32 * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single 33 * QUP module can provide upto 8 serial interfaces, using its internal 34 * serial engines. The actual configuration is determined by the target 35 * platform configuration. The protocol supported by each interface is 36 * determined by the firmware loaded to the serial engine. Each SE consists 37 * of a DMA Engine and GENI sub modules which enable serial engines to 38 * support FIFO and DMA modes of operation. 39 * 40 * 41 * +-----------------------------------------+ 42 * |QUP Wrapper | 43 * | +----------------------------+ | 44 * --QUP & SE Clocks--> | Serial Engine N | +-IO------> 45 * | | ... | | Interface 46 * <---Clock Perf.----+ +----+-----------------------+ | | 47 * State Interface | | Serial Engine 1 | | | 48 * | | | | | 49 * | | | | | 50 * <--------AHB-------> | | | | 51 * | | +----+ | 52 * | | | | 53 * | | | | 54 * <------SE IRQ------+ +----------------------------+ | 55 * | | 56 * +-----------------------------------------+ 57 * 58 * Figure 1: GENI based QUP Wrapper 59 * 60 * The GENI submodules include primary and secondary sequencers which are 61 * used to drive TX & RX operations. On serial interfaces that operate using 62 * master-slave model, primary sequencer drives both TX & RX operations. On 63 * serial interfaces that operate using peer-to-peer model, primary sequencer 64 * drives TX operation and secondary sequencer drives RX operation. 65 */ 66 67 /** 68 * DOC: Software description 69 * 70 * GENI SE Wrapper driver is structured into 2 parts: 71 * 72 * geni_wrapper represents QUP Wrapper controller. This part of the driver 73 * manages QUP Wrapper information such as hardware version, clock 74 * performance table that is common to all the internal serial engines. 75 * 76 * geni_se represents serial engine. This part of the driver manages serial 77 * engine information such as clocks, containing QUP Wrapper, etc. This part 78 * of driver also supports operations (eg. initialize the concerned serial 79 * engine, select between FIFO and DMA mode of operation etc.) that are 80 * common to all the serial engines and are independent of serial interfaces. 81 */ 82 83 #define MAX_CLK_PERF_LEVEL 32 84 #define MAX_CLKS 2 85 86 /** 87 * struct geni_wrapper - Data structure to represent the QUP Wrapper Core 88 * @dev: Device pointer of the QUP wrapper core 89 * @base: Base address of this instance of QUP wrapper core 90 * @clks: Handle to the primary & optional secondary AHB clocks 91 * @num_clks: Count of clocks 92 * @to_core: Core ICC path 93 */ 94 struct geni_wrapper { 95 struct device *dev; 96 void __iomem *base; 97 struct clk_bulk_data clks[MAX_CLKS]; 98 unsigned int num_clks; 99 }; 100 101 /** 102 * struct geni_se_desc - Data structure to represent the QUP Wrapper resources 103 * @clks: Name of the primary & optional secondary AHB clocks 104 * @num_clks: Count of clock names 105 */ 106 struct geni_se_desc { 107 unsigned int num_clks; 108 const char * const *clks; 109 }; 110 111 static const char * const icc_path_names[] = {"qup-core", "qup-config", 112 "qup-memory"}; 113 114 #define QUP_HW_VER_REG 0x4 115 116 /* Common SE registers */ 117 #define GENI_INIT_CFG_REVISION 0x0 118 #define GENI_S_INIT_CFG_REVISION 0x4 119 #define GENI_OUTPUT_CTRL 0x24 120 #define GENI_CGC_CTRL 0x28 121 #define GENI_CLK_CTRL_RO 0x60 122 #define GENI_FW_S_REVISION_RO 0x6c 123 #define SE_GENI_BYTE_GRAN 0x254 124 #define SE_GENI_TX_PACKING_CFG0 0x260 125 #define SE_GENI_TX_PACKING_CFG1 0x264 126 #define SE_GENI_RX_PACKING_CFG0 0x284 127 #define SE_GENI_RX_PACKING_CFG1 0x288 128 #define SE_GENI_M_GP_LENGTH 0x910 129 #define SE_GENI_S_GP_LENGTH 0x914 130 #define SE_DMA_TX_PTR_L 0xc30 131 #define SE_DMA_TX_PTR_H 0xc34 132 #define SE_DMA_TX_ATTR 0xc38 133 #define SE_DMA_TX_LEN 0xc3c 134 #define SE_DMA_TX_IRQ_EN 0xc48 135 #define SE_DMA_TX_IRQ_EN_SET 0xc4c 136 #define SE_DMA_TX_IRQ_EN_CLR 0xc50 137 #define SE_DMA_TX_LEN_IN 0xc54 138 #define SE_DMA_TX_MAX_BURST 0xc5c 139 #define SE_DMA_RX_PTR_L 0xd30 140 #define SE_DMA_RX_PTR_H 0xd34 141 #define SE_DMA_RX_ATTR 0xd38 142 #define SE_DMA_RX_LEN 0xd3c 143 #define SE_DMA_RX_IRQ_EN 0xd48 144 #define SE_DMA_RX_IRQ_EN_SET 0xd4c 145 #define SE_DMA_RX_IRQ_EN_CLR 0xd50 146 #define SE_DMA_RX_LEN_IN 0xd54 147 #define SE_DMA_RX_MAX_BURST 0xd5c 148 #define SE_DMA_RX_FLUSH 0xd60 149 #define SE_GSI_EVENT_EN 0xe18 150 #define SE_IRQ_EN 0xe1c 151 #define SE_DMA_GENERAL_CFG 0xe30 152 153 /* GENI_OUTPUT_CTRL fields */ 154 #define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0) 155 156 /* GENI_CGC_CTRL fields */ 157 #define CFG_AHB_CLK_CGC_ON BIT(0) 158 #define CFG_AHB_WR_ACLK_CGC_ON BIT(1) 159 #define DATA_AHB_CLK_CGC_ON BIT(2) 160 #define SCLK_CGC_ON BIT(3) 161 #define TX_CLK_CGC_ON BIT(4) 162 #define RX_CLK_CGC_ON BIT(5) 163 #define EXT_CLK_CGC_ON BIT(6) 164 #define PROG_RAM_HCLK_OFF BIT(8) 165 #define PROG_RAM_SCLK_OFF BIT(9) 166 #define DEFAULT_CGC_EN GENMASK(6, 0) 167 168 /* SE_GSI_EVENT_EN fields */ 169 #define DMA_RX_EVENT_EN BIT(0) 170 #define DMA_TX_EVENT_EN BIT(1) 171 #define GENI_M_EVENT_EN BIT(2) 172 #define GENI_S_EVENT_EN BIT(3) 173 174 /* SE_IRQ_EN fields */ 175 #define DMA_RX_IRQ_EN BIT(0) 176 #define DMA_TX_IRQ_EN BIT(1) 177 #define GENI_M_IRQ_EN BIT(2) 178 #define GENI_S_IRQ_EN BIT(3) 179 180 /* SE_DMA_GENERAL_CFG */ 181 #define DMA_RX_CLK_CGC_ON BIT(0) 182 #define DMA_TX_CLK_CGC_ON BIT(1) 183 #define DMA_AHB_SLV_CFG_ON BIT(2) 184 #define AHB_SEC_SLV_CLK_CGC_ON BIT(3) 185 #define DUMMY_RX_NON_BUFFERABLE BIT(4) 186 #define RX_DMA_ZERO_PADDING_EN BIT(5) 187 #define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6) 188 #define RX_DMA_IRQ_DELAY_SHFT 6 189 190 /** 191 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version 192 * @se: Pointer to the corresponding serial engine. 193 * 194 * Return: Hardware Version of the wrapper. 195 */ 196 u32 geni_se_get_qup_hw_version(struct geni_se *se) 197 { 198 struct geni_wrapper *wrapper = se->wrapper; 199 200 return readl_relaxed(wrapper->base + QUP_HW_VER_REG); 201 } 202 EXPORT_SYMBOL(geni_se_get_qup_hw_version); 203 204 static void geni_se_io_set_mode(void __iomem *base) 205 { 206 u32 val; 207 208 val = readl_relaxed(base + SE_IRQ_EN); 209 val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN; 210 val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN; 211 writel_relaxed(val, base + SE_IRQ_EN); 212 213 val = readl_relaxed(base + SE_GENI_DMA_MODE_EN); 214 val &= ~GENI_DMA_MODE_EN; 215 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN); 216 217 writel_relaxed(0, base + SE_GSI_EVENT_EN); 218 } 219 220 static void geni_se_io_init(void __iomem *base) 221 { 222 u32 val; 223 224 val = readl_relaxed(base + GENI_CGC_CTRL); 225 val |= DEFAULT_CGC_EN; 226 writel_relaxed(val, base + GENI_CGC_CTRL); 227 228 val = readl_relaxed(base + SE_DMA_GENERAL_CFG); 229 val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON; 230 val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON; 231 writel_relaxed(val, base + SE_DMA_GENERAL_CFG); 232 233 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL); 234 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG); 235 } 236 237 static void geni_se_irq_clear(struct geni_se *se) 238 { 239 writel_relaxed(0, se->base + SE_GSI_EVENT_EN); 240 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR); 241 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR); 242 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR); 243 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR); 244 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN); 245 } 246 247 /** 248 * geni_se_init() - Initialize the GENI serial engine 249 * @se: Pointer to the concerned serial engine. 250 * @rx_wm: Receive watermark, in units of FIFO words. 251 * @rx_rfr: Ready-for-receive watermark, in units of FIFO words. 252 * 253 * This function is used to initialize the GENI serial engine, configure 254 * receive watermark and ready-for-receive watermarks. 255 */ 256 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr) 257 { 258 u32 val; 259 260 geni_se_irq_clear(se); 261 geni_se_io_init(se->base); 262 geni_se_io_set_mode(se->base); 263 264 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG); 265 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG); 266 267 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 268 val |= M_COMMON_GENI_M_IRQ_EN; 269 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 270 271 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 272 val |= S_COMMON_GENI_S_IRQ_EN; 273 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 274 } 275 EXPORT_SYMBOL(geni_se_init); 276 277 static void geni_se_select_fifo_mode(struct geni_se *se) 278 { 279 u32 proto = geni_se_read_proto(se); 280 u32 val, val_old; 281 282 geni_se_irq_clear(se); 283 284 /* 285 * The RX path for the UART is asynchronous and so needs more 286 * complex logic for enabling / disabling its interrupts. 287 * 288 * Specific notes: 289 * - The done and TX-related interrupts are managed manually. 290 * - We don't RX from the main sequencer (we use the secondary) so 291 * we don't need the RX-related interrupts enabled in the main 292 * sequencer for UART. 293 */ 294 if (proto != GENI_SE_UART) { 295 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 296 val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN; 297 val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 298 if (val != val_old) 299 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 300 301 val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 302 val |= S_CMD_DONE_EN; 303 if (val != val_old) 304 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 305 } 306 307 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 308 val &= ~GENI_DMA_MODE_EN; 309 if (val != val_old) 310 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 311 } 312 313 static void geni_se_select_dma_mode(struct geni_se *se) 314 { 315 u32 proto = geni_se_read_proto(se); 316 u32 val, val_old; 317 318 geni_se_irq_clear(se); 319 320 if (proto != GENI_SE_UART) { 321 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 322 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 323 val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 324 if (val != val_old) 325 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 326 327 val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 328 val &= ~S_CMD_DONE_EN; 329 if (val != val_old) 330 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 331 } 332 333 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 334 val |= GENI_DMA_MODE_EN; 335 if (val != val_old) 336 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 337 } 338 339 static void geni_se_select_gpi_mode(struct geni_se *se) 340 { 341 u32 val; 342 343 geni_se_irq_clear(se); 344 345 writel(0, se->base + SE_IRQ_EN); 346 347 val = readl(se->base + SE_GENI_S_IRQ_EN); 348 val &= ~S_CMD_DONE_EN; 349 writel(val, se->base + SE_GENI_S_IRQ_EN); 350 351 val = readl(se->base + SE_GENI_M_IRQ_EN); 352 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN | 353 M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 354 writel(val, se->base + SE_GENI_M_IRQ_EN); 355 356 writel(GENI_DMA_MODE_EN, se->base + SE_GENI_DMA_MODE_EN); 357 358 val = readl(se->base + SE_GSI_EVENT_EN); 359 val |= (DMA_RX_EVENT_EN | DMA_TX_EVENT_EN | GENI_M_EVENT_EN | GENI_S_EVENT_EN); 360 writel(val, se->base + SE_GSI_EVENT_EN); 361 } 362 363 /** 364 * geni_se_select_mode() - Select the serial engine transfer mode 365 * @se: Pointer to the concerned serial engine. 366 * @mode: Transfer mode to be selected. 367 */ 368 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode) 369 { 370 WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA && mode != GENI_GPI_DMA); 371 372 switch (mode) { 373 case GENI_SE_FIFO: 374 geni_se_select_fifo_mode(se); 375 break; 376 case GENI_SE_DMA: 377 geni_se_select_dma_mode(se); 378 break; 379 case GENI_GPI_DMA: 380 geni_se_select_gpi_mode(se); 381 break; 382 case GENI_SE_INVALID: 383 default: 384 break; 385 } 386 } 387 EXPORT_SYMBOL(geni_se_select_mode); 388 389 /** 390 * DOC: Overview 391 * 392 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist 393 * of up to 4 operations, each operation represented by 4 configuration vectors 394 * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for 395 * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO. 396 * Refer to below examples for detailed bit-field description. 397 * 398 * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1 399 * 400 * +-----------+-------+-------+-------+-------+ 401 * | | vec_0 | vec_1 | vec_2 | vec_3 | 402 * +-----------+-------+-------+-------+-------+ 403 * | start | 0x6 | 0xe | 0x16 | 0x1e | 404 * | direction | 1 | 1 | 1 | 1 | 405 * | length | 6 | 6 | 6 | 6 | 406 * | stop | 0 | 0 | 0 | 1 | 407 * +-----------+-------+-------+-------+-------+ 408 * 409 * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0 410 * 411 * +-----------+-------+-------+-------+-------+ 412 * | | vec_0 | vec_1 | vec_2 | vec_3 | 413 * +-----------+-------+-------+-------+-------+ 414 * | start | 0x0 | 0x8 | 0x10 | 0x18 | 415 * | direction | 0 | 0 | 0 | 0 | 416 * | length | 7 | 6 | 7 | 6 | 417 * | stop | 0 | 0 | 0 | 1 | 418 * +-----------+-------+-------+-------+-------+ 419 * 420 * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1 421 * 422 * +-----------+-------+-------+-------+-------+ 423 * | | vec_0 | vec_1 | vec_2 | vec_3 | 424 * +-----------+-------+-------+-------+-------+ 425 * | start | 0x16 | 0xe | 0x6 | 0x0 | 426 * | direction | 1 | 1 | 1 | 1 | 427 * | length | 7 | 7 | 6 | 0 | 428 * | stop | 0 | 0 | 1 | 0 | 429 * +-----------+-------+-------+-------+-------+ 430 * 431 */ 432 433 #define NUM_PACKING_VECTORS 4 434 #define PACKING_START_SHIFT 5 435 #define PACKING_DIR_SHIFT 4 436 #define PACKING_LEN_SHIFT 1 437 #define PACKING_STOP_BIT BIT(0) 438 #define PACKING_VECTOR_SHIFT 10 439 /** 440 * geni_se_config_packing() - Packing configuration of the serial engine 441 * @se: Pointer to the concerned serial engine 442 * @bpw: Bits of data per transfer word. 443 * @pack_words: Number of words per fifo element. 444 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa. 445 * @tx_cfg: Flag to configure the TX Packing. 446 * @rx_cfg: Flag to configure the RX Packing. 447 * 448 * This function is used to configure the packing rules for the current 449 * transfer. 450 */ 451 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words, 452 bool msb_to_lsb, bool tx_cfg, bool rx_cfg) 453 { 454 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0}; 455 int len; 456 int temp_bpw = bpw; 457 int idx_start = msb_to_lsb ? bpw - 1 : 0; 458 int idx = idx_start; 459 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE; 460 int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE); 461 int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE; 462 int i; 463 464 if (iter <= 0 || iter > NUM_PACKING_VECTORS) 465 return; 466 467 for (i = 0; i < iter; i++) { 468 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1; 469 cfg[i] = idx << PACKING_START_SHIFT; 470 cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT; 471 cfg[i] |= len << PACKING_LEN_SHIFT; 472 473 if (temp_bpw <= BITS_PER_BYTE) { 474 idx = ((i + 1) * BITS_PER_BYTE) + idx_start; 475 temp_bpw = bpw; 476 } else { 477 idx = idx + idx_delta; 478 temp_bpw = temp_bpw - BITS_PER_BYTE; 479 } 480 } 481 cfg[iter - 1] |= PACKING_STOP_BIT; 482 cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT); 483 cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT); 484 485 if (tx_cfg) { 486 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); 487 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); 488 } 489 if (rx_cfg) { 490 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); 491 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); 492 } 493 494 /* 495 * Number of protocol words in each FIFO entry 496 * 0 - 4x8, four words in each entry, max word size of 8 bits 497 * 1 - 2x16, two words in each entry, max word size of 16 bits 498 * 2 - 1x32, one word in each entry, max word size of 32 bits 499 * 3 - undefined 500 */ 501 if (pack_words || bpw == 32) 502 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN); 503 } 504 EXPORT_SYMBOL(geni_se_config_packing); 505 506 static void geni_se_clks_off(struct geni_se *se) 507 { 508 struct geni_wrapper *wrapper = se->wrapper; 509 510 clk_disable_unprepare(se->clk); 511 clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks); 512 } 513 514 /** 515 * geni_se_resources_off() - Turn off resources associated with the serial 516 * engine 517 * @se: Pointer to the concerned serial engine. 518 * 519 * Return: 0 on success, standard Linux error codes on failure/error. 520 */ 521 int geni_se_resources_off(struct geni_se *se) 522 { 523 int ret; 524 525 if (has_acpi_companion(se->dev)) 526 return 0; 527 528 ret = pinctrl_pm_select_sleep_state(se->dev); 529 if (ret) 530 return ret; 531 532 geni_se_clks_off(se); 533 return 0; 534 } 535 EXPORT_SYMBOL(geni_se_resources_off); 536 537 static int geni_se_clks_on(struct geni_se *se) 538 { 539 int ret; 540 struct geni_wrapper *wrapper = se->wrapper; 541 542 ret = clk_bulk_prepare_enable(wrapper->num_clks, wrapper->clks); 543 if (ret) 544 return ret; 545 546 ret = clk_prepare_enable(se->clk); 547 if (ret) 548 clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks); 549 return ret; 550 } 551 552 /** 553 * geni_se_resources_on() - Turn on resources associated with the serial 554 * engine 555 * @se: Pointer to the concerned serial engine. 556 * 557 * Return: 0 on success, standard Linux error codes on failure/error. 558 */ 559 int geni_se_resources_on(struct geni_se *se) 560 { 561 int ret; 562 563 if (has_acpi_companion(se->dev)) 564 return 0; 565 566 ret = geni_se_clks_on(se); 567 if (ret) 568 return ret; 569 570 ret = pinctrl_pm_select_default_state(se->dev); 571 if (ret) 572 geni_se_clks_off(se); 573 574 return ret; 575 } 576 EXPORT_SYMBOL(geni_se_resources_on); 577 578 /** 579 * geni_se_clk_tbl_get() - Get the clock table to program DFS 580 * @se: Pointer to the concerned serial engine. 581 * @tbl: Table in which the output is returned. 582 * 583 * This function is called by the protocol drivers to determine the different 584 * clock frequencies supported by serial engine core clock. The protocol 585 * drivers use the output to determine the clock frequency index to be 586 * programmed into DFS. 587 * 588 * Return: number of valid performance levels in the table on success, 589 * standard Linux error codes on failure. 590 */ 591 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl) 592 { 593 long freq = 0; 594 int i; 595 596 if (se->clk_perf_tbl) { 597 *tbl = se->clk_perf_tbl; 598 return se->num_clk_levels; 599 } 600 601 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL, 602 sizeof(*se->clk_perf_tbl), 603 GFP_KERNEL); 604 if (!se->clk_perf_tbl) 605 return -ENOMEM; 606 607 for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) { 608 freq = clk_round_rate(se->clk, freq + 1); 609 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1]) 610 break; 611 se->clk_perf_tbl[i] = freq; 612 } 613 se->num_clk_levels = i; 614 *tbl = se->clk_perf_tbl; 615 return se->num_clk_levels; 616 } 617 EXPORT_SYMBOL(geni_se_clk_tbl_get); 618 619 /** 620 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency 621 * @se: Pointer to the concerned serial engine. 622 * @req_freq: Requested clock frequency. 623 * @index: Index of the resultant frequency in the table. 624 * @res_freq: Resultant frequency of the source clock. 625 * @exact: Flag to indicate exact multiple requirement of the requested 626 * frequency. 627 * 628 * This function is called by the protocol drivers to determine the best match 629 * of the requested frequency as provided by the serial engine clock in order 630 * to meet the performance requirements. 631 * 632 * If we return success: 633 * - if @exact is true then @res_freq / <an_integer> == @req_freq 634 * - if @exact is false then @res_freq / <an_integer> <= @req_freq 635 * 636 * Return: 0 on success, standard Linux error codes on failure. 637 */ 638 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, 639 unsigned int *index, unsigned long *res_freq, 640 bool exact) 641 { 642 unsigned long *tbl; 643 int num_clk_levels; 644 int i; 645 unsigned long best_delta; 646 unsigned long new_delta; 647 unsigned int divider; 648 649 num_clk_levels = geni_se_clk_tbl_get(se, &tbl); 650 if (num_clk_levels < 0) 651 return num_clk_levels; 652 653 if (num_clk_levels == 0) 654 return -EINVAL; 655 656 best_delta = ULONG_MAX; 657 for (i = 0; i < num_clk_levels; i++) { 658 divider = DIV_ROUND_UP(tbl[i], req_freq); 659 new_delta = req_freq - tbl[i] / divider; 660 if (new_delta < best_delta) { 661 /* We have a new best! */ 662 *index = i; 663 *res_freq = tbl[i]; 664 665 /* If the new best is exact then we're done */ 666 if (new_delta == 0) 667 return 0; 668 669 /* Record how close we got */ 670 best_delta = new_delta; 671 } 672 } 673 674 if (exact) 675 return -EINVAL; 676 677 return 0; 678 } 679 EXPORT_SYMBOL(geni_se_clk_freq_match); 680 681 #define GENI_SE_DMA_DONE_EN BIT(0) 682 #define GENI_SE_DMA_EOT_EN BIT(1) 683 #define GENI_SE_DMA_AHB_ERR_EN BIT(2) 684 #define GENI_SE_DMA_EOT_BUF BIT(0) 685 /** 686 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer 687 * @se: Pointer to the concerned serial engine. 688 * @buf: Pointer to the TX buffer. 689 * @len: Length of the TX buffer. 690 * @iova: Pointer to store the mapped DMA address. 691 * 692 * This function is used to prepare the buffers for DMA TX. 693 * 694 * Return: 0 on success, standard Linux error codes on failure. 695 */ 696 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, 697 dma_addr_t *iova) 698 { 699 struct geni_wrapper *wrapper = se->wrapper; 700 u32 val; 701 702 if (!wrapper) 703 return -EINVAL; 704 705 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE); 706 if (dma_mapping_error(wrapper->dev, *iova)) 707 return -EIO; 708 709 val = GENI_SE_DMA_DONE_EN; 710 val |= GENI_SE_DMA_EOT_EN; 711 val |= GENI_SE_DMA_AHB_ERR_EN; 712 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); 713 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L); 714 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H); 715 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); 716 writel(len, se->base + SE_DMA_TX_LEN); 717 return 0; 718 } 719 EXPORT_SYMBOL(geni_se_tx_dma_prep); 720 721 /** 722 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer 723 * @se: Pointer to the concerned serial engine. 724 * @buf: Pointer to the RX buffer. 725 * @len: Length of the RX buffer. 726 * @iova: Pointer to store the mapped DMA address. 727 * 728 * This function is used to prepare the buffers for DMA RX. 729 * 730 * Return: 0 on success, standard Linux error codes on failure. 731 */ 732 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, 733 dma_addr_t *iova) 734 { 735 struct geni_wrapper *wrapper = se->wrapper; 736 u32 val; 737 738 if (!wrapper) 739 return -EINVAL; 740 741 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE); 742 if (dma_mapping_error(wrapper->dev, *iova)) 743 return -EIO; 744 745 val = GENI_SE_DMA_DONE_EN; 746 val |= GENI_SE_DMA_EOT_EN; 747 val |= GENI_SE_DMA_AHB_ERR_EN; 748 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); 749 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L); 750 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H); 751 /* RX does not have EOT buffer type bit. So just reset RX_ATTR */ 752 writel_relaxed(0, se->base + SE_DMA_RX_ATTR); 753 writel(len, se->base + SE_DMA_RX_LEN); 754 return 0; 755 } 756 EXPORT_SYMBOL(geni_se_rx_dma_prep); 757 758 /** 759 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer 760 * @se: Pointer to the concerned serial engine. 761 * @iova: DMA address of the TX buffer. 762 * @len: Length of the TX buffer. 763 * 764 * This function is used to unprepare the DMA buffers after DMA TX. 765 */ 766 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) 767 { 768 struct geni_wrapper *wrapper = se->wrapper; 769 770 if (!dma_mapping_error(wrapper->dev, iova)) 771 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE); 772 } 773 EXPORT_SYMBOL(geni_se_tx_dma_unprep); 774 775 /** 776 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer 777 * @se: Pointer to the concerned serial engine. 778 * @iova: DMA address of the RX buffer. 779 * @len: Length of the RX buffer. 780 * 781 * This function is used to unprepare the DMA buffers after DMA RX. 782 */ 783 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) 784 { 785 struct geni_wrapper *wrapper = se->wrapper; 786 787 if (!dma_mapping_error(wrapper->dev, iova)) 788 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE); 789 } 790 EXPORT_SYMBOL(geni_se_rx_dma_unprep); 791 792 int geni_icc_get(struct geni_se *se, const char *icc_ddr) 793 { 794 int i, err; 795 const char *icc_names[] = {"qup-core", "qup-config", icc_ddr}; 796 797 if (has_acpi_companion(se->dev)) 798 return 0; 799 800 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 801 if (!icc_names[i]) 802 continue; 803 804 se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]); 805 if (IS_ERR(se->icc_paths[i].path)) 806 goto err; 807 } 808 809 return 0; 810 811 err: 812 err = PTR_ERR(se->icc_paths[i].path); 813 if (err != -EPROBE_DEFER) 814 dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n", 815 icc_names[i], err); 816 return err; 817 818 } 819 EXPORT_SYMBOL(geni_icc_get); 820 821 int geni_icc_set_bw(struct geni_se *se) 822 { 823 int i, ret; 824 825 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 826 ret = icc_set_bw(se->icc_paths[i].path, 827 se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw); 828 if (ret) { 829 dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n", 830 icc_path_names[i], ret); 831 return ret; 832 } 833 } 834 835 return 0; 836 } 837 EXPORT_SYMBOL(geni_icc_set_bw); 838 839 void geni_icc_set_tag(struct geni_se *se, u32 tag) 840 { 841 int i; 842 843 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) 844 icc_set_tag(se->icc_paths[i].path, tag); 845 } 846 EXPORT_SYMBOL(geni_icc_set_tag); 847 848 /* To do: Replace this by icc_bulk_enable once it's implemented in ICC core */ 849 int geni_icc_enable(struct geni_se *se) 850 { 851 int i, ret; 852 853 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 854 ret = icc_enable(se->icc_paths[i].path); 855 if (ret) { 856 dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n", 857 icc_path_names[i], ret); 858 return ret; 859 } 860 } 861 862 return 0; 863 } 864 EXPORT_SYMBOL(geni_icc_enable); 865 866 int geni_icc_disable(struct geni_se *se) 867 { 868 int i, ret; 869 870 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 871 ret = icc_disable(se->icc_paths[i].path); 872 if (ret) { 873 dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n", 874 icc_path_names[i], ret); 875 return ret; 876 } 877 } 878 879 return 0; 880 } 881 EXPORT_SYMBOL(geni_icc_disable); 882 883 static int geni_se_probe(struct platform_device *pdev) 884 { 885 struct device *dev = &pdev->dev; 886 struct geni_wrapper *wrapper; 887 int ret; 888 889 wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL); 890 if (!wrapper) 891 return -ENOMEM; 892 893 wrapper->dev = dev; 894 wrapper->base = devm_platform_ioremap_resource(pdev, 0); 895 if (IS_ERR(wrapper->base)) 896 return PTR_ERR(wrapper->base); 897 898 if (!has_acpi_companion(&pdev->dev)) { 899 const struct geni_se_desc *desc; 900 int i; 901 902 desc = device_get_match_data(&pdev->dev); 903 if (!desc) 904 return -EINVAL; 905 906 wrapper->num_clks = min_t(unsigned int, desc->num_clks, MAX_CLKS); 907 908 for (i = 0; i < wrapper->num_clks; ++i) 909 wrapper->clks[i].id = desc->clks[i]; 910 911 ret = of_count_phandle_with_args(dev->of_node, "clocks", "#clock-cells"); 912 if (ret < 0) { 913 dev_err(dev, "invalid clocks property at %pOF\n", dev->of_node); 914 return ret; 915 } 916 917 if (ret < wrapper->num_clks) { 918 dev_err(dev, "invalid clocks count at %pOF, expected %d entries\n", 919 dev->of_node, wrapper->num_clks); 920 return -EINVAL; 921 } 922 923 ret = devm_clk_bulk_get(dev, wrapper->num_clks, wrapper->clks); 924 if (ret) { 925 dev_err(dev, "Err getting clks %d\n", ret); 926 return ret; 927 } 928 } 929 930 dev_set_drvdata(dev, wrapper); 931 dev_dbg(dev, "GENI SE Driver probed\n"); 932 return devm_of_platform_populate(dev); 933 } 934 935 static const char * const qup_clks[] = { 936 "m-ahb", 937 "s-ahb", 938 }; 939 940 static const struct geni_se_desc qup_desc = { 941 .clks = qup_clks, 942 .num_clks = ARRAY_SIZE(qup_clks), 943 }; 944 945 static const char * const i2c_master_hub_clks[] = { 946 "s-ahb", 947 }; 948 949 static const struct geni_se_desc i2c_master_hub_desc = { 950 .clks = i2c_master_hub_clks, 951 .num_clks = ARRAY_SIZE(i2c_master_hub_clks), 952 }; 953 954 static const struct of_device_id geni_se_dt_match[] = { 955 { .compatible = "qcom,geni-se-qup", .data = &qup_desc }, 956 { .compatible = "qcom,geni-se-i2c-master-hub", .data = &i2c_master_hub_desc }, 957 {} 958 }; 959 MODULE_DEVICE_TABLE(of, geni_se_dt_match); 960 961 static struct platform_driver geni_se_driver = { 962 .driver = { 963 .name = "geni_se_qup", 964 .of_match_table = geni_se_dt_match, 965 }, 966 .probe = geni_se_probe, 967 }; 968 module_platform_driver(geni_se_driver); 969 970 MODULE_DESCRIPTION("GENI Serial Engine Driver"); 971 MODULE_LICENSE("GPL v2"); 972