1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 3 4 #include <linux/acpi.h> 5 #include <linux/clk.h> 6 #include <linux/slab.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/io.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_platform.h> 12 #include <linux/pinctrl/consumer.h> 13 #include <linux/platform_device.h> 14 #include <linux/qcom-geni-se.h> 15 16 /** 17 * DOC: Overview 18 * 19 * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced 20 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper 21 * controller. QUP Wrapper is designed to support various serial bus protocols 22 * like UART, SPI, I2C, I3C, etc. 23 */ 24 25 /** 26 * DOC: Hardware description 27 * 28 * GENI based QUP is a highly-flexible and programmable module for supporting 29 * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single 30 * QUP module can provide upto 8 serial interfaces, using its internal 31 * serial engines. The actual configuration is determined by the target 32 * platform configuration. The protocol supported by each interface is 33 * determined by the firmware loaded to the serial engine. Each SE consists 34 * of a DMA Engine and GENI sub modules which enable serial engines to 35 * support FIFO and DMA modes of operation. 36 * 37 * 38 * +-----------------------------------------+ 39 * |QUP Wrapper | 40 * | +----------------------------+ | 41 * --QUP & SE Clocks--> | Serial Engine N | +-IO------> 42 * | | ... | | Interface 43 * <---Clock Perf.----+ +----+-----------------------+ | | 44 * State Interface | | Serial Engine 1 | | | 45 * | | | | | 46 * | | | | | 47 * <--------AHB-------> | | | | 48 * | | +----+ | 49 * | | | | 50 * | | | | 51 * <------SE IRQ------+ +----------------------------+ | 52 * | | 53 * +-----------------------------------------+ 54 * 55 * Figure 1: GENI based QUP Wrapper 56 * 57 * The GENI submodules include primary and secondary sequencers which are 58 * used to drive TX & RX operations. On serial interfaces that operate using 59 * master-slave model, primary sequencer drives both TX & RX operations. On 60 * serial interfaces that operate using peer-to-peer model, primary sequencer 61 * drives TX operation and secondary sequencer drives RX operation. 62 */ 63 64 /** 65 * DOC: Software description 66 * 67 * GENI SE Wrapper driver is structured into 2 parts: 68 * 69 * geni_wrapper represents QUP Wrapper controller. This part of the driver 70 * manages QUP Wrapper information such as hardware version, clock 71 * performance table that is common to all the internal serial engines. 72 * 73 * geni_se represents serial engine. This part of the driver manages serial 74 * engine information such as clocks, containing QUP Wrapper, etc. This part 75 * of driver also supports operations (eg. initialize the concerned serial 76 * engine, select between FIFO and DMA mode of operation etc.) that are 77 * common to all the serial engines and are independent of serial interfaces. 78 */ 79 80 #define MAX_CLK_PERF_LEVEL 32 81 #define NUM_AHB_CLKS 2 82 83 /** 84 * struct geni_wrapper - Data structure to represent the QUP Wrapper Core 85 * @dev: Device pointer of the QUP wrapper core 86 * @base: Base address of this instance of QUP wrapper core 87 * @ahb_clks: Handle to the primary & secondary AHB clocks 88 * @to_core: Core ICC path 89 */ 90 struct geni_wrapper { 91 struct device *dev; 92 void __iomem *base; 93 struct clk_bulk_data ahb_clks[NUM_AHB_CLKS]; 94 }; 95 96 static const char * const icc_path_names[] = {"qup-core", "qup-config", 97 "qup-memory"}; 98 99 #define QUP_HW_VER_REG 0x4 100 101 /* Common SE registers */ 102 #define GENI_INIT_CFG_REVISION 0x0 103 #define GENI_S_INIT_CFG_REVISION 0x4 104 #define GENI_OUTPUT_CTRL 0x24 105 #define GENI_CGC_CTRL 0x28 106 #define GENI_CLK_CTRL_RO 0x60 107 #define GENI_IF_DISABLE_RO 0x64 108 #define GENI_FW_S_REVISION_RO 0x6c 109 #define SE_GENI_BYTE_GRAN 0x254 110 #define SE_GENI_TX_PACKING_CFG0 0x260 111 #define SE_GENI_TX_PACKING_CFG1 0x264 112 #define SE_GENI_RX_PACKING_CFG0 0x284 113 #define SE_GENI_RX_PACKING_CFG1 0x288 114 #define SE_GENI_M_GP_LENGTH 0x910 115 #define SE_GENI_S_GP_LENGTH 0x914 116 #define SE_DMA_TX_PTR_L 0xc30 117 #define SE_DMA_TX_PTR_H 0xc34 118 #define SE_DMA_TX_ATTR 0xc38 119 #define SE_DMA_TX_LEN 0xc3c 120 #define SE_DMA_TX_IRQ_EN 0xc48 121 #define SE_DMA_TX_IRQ_EN_SET 0xc4c 122 #define SE_DMA_TX_IRQ_EN_CLR 0xc50 123 #define SE_DMA_TX_LEN_IN 0xc54 124 #define SE_DMA_TX_MAX_BURST 0xc5c 125 #define SE_DMA_RX_PTR_L 0xd30 126 #define SE_DMA_RX_PTR_H 0xd34 127 #define SE_DMA_RX_ATTR 0xd38 128 #define SE_DMA_RX_LEN 0xd3c 129 #define SE_DMA_RX_IRQ_EN 0xd48 130 #define SE_DMA_RX_IRQ_EN_SET 0xd4c 131 #define SE_DMA_RX_IRQ_EN_CLR 0xd50 132 #define SE_DMA_RX_LEN_IN 0xd54 133 #define SE_DMA_RX_MAX_BURST 0xd5c 134 #define SE_DMA_RX_FLUSH 0xd60 135 #define SE_GSI_EVENT_EN 0xe18 136 #define SE_IRQ_EN 0xe1c 137 #define SE_DMA_GENERAL_CFG 0xe30 138 139 /* GENI_OUTPUT_CTRL fields */ 140 #define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0) 141 142 /* GENI_CGC_CTRL fields */ 143 #define CFG_AHB_CLK_CGC_ON BIT(0) 144 #define CFG_AHB_WR_ACLK_CGC_ON BIT(1) 145 #define DATA_AHB_CLK_CGC_ON BIT(2) 146 #define SCLK_CGC_ON BIT(3) 147 #define TX_CLK_CGC_ON BIT(4) 148 #define RX_CLK_CGC_ON BIT(5) 149 #define EXT_CLK_CGC_ON BIT(6) 150 #define PROG_RAM_HCLK_OFF BIT(8) 151 #define PROG_RAM_SCLK_OFF BIT(9) 152 #define DEFAULT_CGC_EN GENMASK(6, 0) 153 154 /* SE_GSI_EVENT_EN fields */ 155 #define DMA_RX_EVENT_EN BIT(0) 156 #define DMA_TX_EVENT_EN BIT(1) 157 #define GENI_M_EVENT_EN BIT(2) 158 #define GENI_S_EVENT_EN BIT(3) 159 160 /* SE_IRQ_EN fields */ 161 #define DMA_RX_IRQ_EN BIT(0) 162 #define DMA_TX_IRQ_EN BIT(1) 163 #define GENI_M_IRQ_EN BIT(2) 164 #define GENI_S_IRQ_EN BIT(3) 165 166 /* SE_DMA_GENERAL_CFG */ 167 #define DMA_RX_CLK_CGC_ON BIT(0) 168 #define DMA_TX_CLK_CGC_ON BIT(1) 169 #define DMA_AHB_SLV_CFG_ON BIT(2) 170 #define AHB_SEC_SLV_CLK_CGC_ON BIT(3) 171 #define DUMMY_RX_NON_BUFFERABLE BIT(4) 172 #define RX_DMA_ZERO_PADDING_EN BIT(5) 173 #define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6) 174 #define RX_DMA_IRQ_DELAY_SHFT 6 175 176 /** 177 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version 178 * @se: Pointer to the corresponding serial engine. 179 * 180 * Return: Hardware Version of the wrapper. 181 */ 182 u32 geni_se_get_qup_hw_version(struct geni_se *se) 183 { 184 struct geni_wrapper *wrapper = se->wrapper; 185 186 return readl_relaxed(wrapper->base + QUP_HW_VER_REG); 187 } 188 EXPORT_SYMBOL(geni_se_get_qup_hw_version); 189 190 static void geni_se_io_set_mode(void __iomem *base) 191 { 192 u32 val; 193 194 val = readl_relaxed(base + SE_IRQ_EN); 195 val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN; 196 val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN; 197 writel_relaxed(val, base + SE_IRQ_EN); 198 199 val = readl_relaxed(base + SE_GENI_DMA_MODE_EN); 200 val &= ~GENI_DMA_MODE_EN; 201 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN); 202 203 writel_relaxed(0, base + SE_GSI_EVENT_EN); 204 } 205 206 static void geni_se_io_init(void __iomem *base) 207 { 208 u32 val; 209 210 val = readl_relaxed(base + GENI_CGC_CTRL); 211 val |= DEFAULT_CGC_EN; 212 writel_relaxed(val, base + GENI_CGC_CTRL); 213 214 val = readl_relaxed(base + SE_DMA_GENERAL_CFG); 215 val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON; 216 val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON; 217 writel_relaxed(val, base + SE_DMA_GENERAL_CFG); 218 219 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL); 220 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG); 221 } 222 223 static void geni_se_irq_clear(struct geni_se *se) 224 { 225 writel_relaxed(0, se->base + SE_GSI_EVENT_EN); 226 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR); 227 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR); 228 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR); 229 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR); 230 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN); 231 } 232 233 /** 234 * geni_se_init() - Initialize the GENI serial engine 235 * @se: Pointer to the concerned serial engine. 236 * @rx_wm: Receive watermark, in units of FIFO words. 237 * @rx_rfr: Ready-for-receive watermark, in units of FIFO words. 238 * 239 * This function is used to initialize the GENI serial engine, configure 240 * receive watermark and ready-for-receive watermarks. 241 */ 242 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr) 243 { 244 u32 val; 245 246 geni_se_irq_clear(se); 247 geni_se_io_init(se->base); 248 geni_se_io_set_mode(se->base); 249 250 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG); 251 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG); 252 253 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 254 val |= M_COMMON_GENI_M_IRQ_EN; 255 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 256 257 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 258 val |= S_COMMON_GENI_S_IRQ_EN; 259 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 260 } 261 EXPORT_SYMBOL(geni_se_init); 262 263 static void geni_se_select_fifo_mode(struct geni_se *se) 264 { 265 u32 proto = geni_se_read_proto(se); 266 u32 val, val_old; 267 268 geni_se_irq_clear(se); 269 270 /* 271 * The RX path for the UART is asynchronous and so needs more 272 * complex logic for enabling / disabling its interrupts. 273 * 274 * Specific notes: 275 * - The done and TX-related interrupts are managed manually. 276 * - We don't RX from the main sequencer (we use the secondary) so 277 * we don't need the RX-related interrupts enabled in the main 278 * sequencer for UART. 279 */ 280 if (proto != GENI_SE_UART) { 281 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 282 val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN; 283 val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 284 if (val != val_old) 285 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 286 287 val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 288 val |= S_CMD_DONE_EN; 289 if (val != val_old) 290 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 291 } 292 293 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 294 val &= ~GENI_DMA_MODE_EN; 295 if (val != val_old) 296 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 297 } 298 299 static void geni_se_select_dma_mode(struct geni_se *se) 300 { 301 u32 proto = geni_se_read_proto(se); 302 u32 val, val_old; 303 304 geni_se_irq_clear(se); 305 306 if (proto != GENI_SE_UART) { 307 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 308 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 309 val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 310 if (val != val_old) 311 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 312 313 val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 314 val &= ~S_CMD_DONE_EN; 315 if (val != val_old) 316 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 317 } 318 319 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 320 val |= GENI_DMA_MODE_EN; 321 if (val != val_old) 322 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 323 } 324 325 /** 326 * geni_se_select_mode() - Select the serial engine transfer mode 327 * @se: Pointer to the concerned serial engine. 328 * @mode: Transfer mode to be selected. 329 */ 330 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode) 331 { 332 WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA); 333 334 switch (mode) { 335 case GENI_SE_FIFO: 336 geni_se_select_fifo_mode(se); 337 break; 338 case GENI_SE_DMA: 339 geni_se_select_dma_mode(se); 340 break; 341 case GENI_SE_INVALID: 342 default: 343 break; 344 } 345 } 346 EXPORT_SYMBOL(geni_se_select_mode); 347 348 /** 349 * DOC: Overview 350 * 351 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist 352 * of up to 4 operations, each operation represented by 4 configuration vectors 353 * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for 354 * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO. 355 * Refer to below examples for detailed bit-field description. 356 * 357 * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1 358 * 359 * +-----------+-------+-------+-------+-------+ 360 * | | vec_0 | vec_1 | vec_2 | vec_3 | 361 * +-----------+-------+-------+-------+-------+ 362 * | start | 0x6 | 0xe | 0x16 | 0x1e | 363 * | direction | 1 | 1 | 1 | 1 | 364 * | length | 6 | 6 | 6 | 6 | 365 * | stop | 0 | 0 | 0 | 1 | 366 * +-----------+-------+-------+-------+-------+ 367 * 368 * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0 369 * 370 * +-----------+-------+-------+-------+-------+ 371 * | | vec_0 | vec_1 | vec_2 | vec_3 | 372 * +-----------+-------+-------+-------+-------+ 373 * | start | 0x0 | 0x8 | 0x10 | 0x18 | 374 * | direction | 0 | 0 | 0 | 0 | 375 * | length | 7 | 6 | 7 | 6 | 376 * | stop | 0 | 0 | 0 | 1 | 377 * +-----------+-------+-------+-------+-------+ 378 * 379 * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1 380 * 381 * +-----------+-------+-------+-------+-------+ 382 * | | vec_0 | vec_1 | vec_2 | vec_3 | 383 * +-----------+-------+-------+-------+-------+ 384 * | start | 0x16 | 0xe | 0x6 | 0x0 | 385 * | direction | 1 | 1 | 1 | 1 | 386 * | length | 7 | 7 | 6 | 0 | 387 * | stop | 0 | 0 | 1 | 0 | 388 * +-----------+-------+-------+-------+-------+ 389 * 390 */ 391 392 #define NUM_PACKING_VECTORS 4 393 #define PACKING_START_SHIFT 5 394 #define PACKING_DIR_SHIFT 4 395 #define PACKING_LEN_SHIFT 1 396 #define PACKING_STOP_BIT BIT(0) 397 #define PACKING_VECTOR_SHIFT 10 398 /** 399 * geni_se_config_packing() - Packing configuration of the serial engine 400 * @se: Pointer to the concerned serial engine 401 * @bpw: Bits of data per transfer word. 402 * @pack_words: Number of words per fifo element. 403 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa. 404 * @tx_cfg: Flag to configure the TX Packing. 405 * @rx_cfg: Flag to configure the RX Packing. 406 * 407 * This function is used to configure the packing rules for the current 408 * transfer. 409 */ 410 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words, 411 bool msb_to_lsb, bool tx_cfg, bool rx_cfg) 412 { 413 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0}; 414 int len; 415 int temp_bpw = bpw; 416 int idx_start = msb_to_lsb ? bpw - 1 : 0; 417 int idx = idx_start; 418 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE; 419 int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE); 420 int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE; 421 int i; 422 423 if (iter <= 0 || iter > NUM_PACKING_VECTORS) 424 return; 425 426 for (i = 0; i < iter; i++) { 427 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1; 428 cfg[i] = idx << PACKING_START_SHIFT; 429 cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT; 430 cfg[i] |= len << PACKING_LEN_SHIFT; 431 432 if (temp_bpw <= BITS_PER_BYTE) { 433 idx = ((i + 1) * BITS_PER_BYTE) + idx_start; 434 temp_bpw = bpw; 435 } else { 436 idx = idx + idx_delta; 437 temp_bpw = temp_bpw - BITS_PER_BYTE; 438 } 439 } 440 cfg[iter - 1] |= PACKING_STOP_BIT; 441 cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT); 442 cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT); 443 444 if (tx_cfg) { 445 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); 446 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); 447 } 448 if (rx_cfg) { 449 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); 450 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); 451 } 452 453 /* 454 * Number of protocol words in each FIFO entry 455 * 0 - 4x8, four words in each entry, max word size of 8 bits 456 * 1 - 2x16, two words in each entry, max word size of 16 bits 457 * 2 - 1x32, one word in each entry, max word size of 32 bits 458 * 3 - undefined 459 */ 460 if (pack_words || bpw == 32) 461 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN); 462 } 463 EXPORT_SYMBOL(geni_se_config_packing); 464 465 static void geni_se_clks_off(struct geni_se *se) 466 { 467 struct geni_wrapper *wrapper = se->wrapper; 468 469 clk_disable_unprepare(se->clk); 470 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), 471 wrapper->ahb_clks); 472 } 473 474 /** 475 * geni_se_resources_off() - Turn off resources associated with the serial 476 * engine 477 * @se: Pointer to the concerned serial engine. 478 * 479 * Return: 0 on success, standard Linux error codes on failure/error. 480 */ 481 int geni_se_resources_off(struct geni_se *se) 482 { 483 int ret; 484 485 if (has_acpi_companion(se->dev)) 486 return 0; 487 488 ret = pinctrl_pm_select_sleep_state(se->dev); 489 if (ret) 490 return ret; 491 492 geni_se_clks_off(se); 493 return 0; 494 } 495 EXPORT_SYMBOL(geni_se_resources_off); 496 497 static int geni_se_clks_on(struct geni_se *se) 498 { 499 int ret; 500 struct geni_wrapper *wrapper = se->wrapper; 501 502 ret = clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks), 503 wrapper->ahb_clks); 504 if (ret) 505 return ret; 506 507 ret = clk_prepare_enable(se->clk); 508 if (ret) 509 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), 510 wrapper->ahb_clks); 511 return ret; 512 } 513 514 /** 515 * geni_se_resources_on() - Turn on resources associated with the serial 516 * engine 517 * @se: Pointer to the concerned serial engine. 518 * 519 * Return: 0 on success, standard Linux error codes on failure/error. 520 */ 521 int geni_se_resources_on(struct geni_se *se) 522 { 523 int ret; 524 525 if (has_acpi_companion(se->dev)) 526 return 0; 527 528 ret = geni_se_clks_on(se); 529 if (ret) 530 return ret; 531 532 ret = pinctrl_pm_select_default_state(se->dev); 533 if (ret) 534 geni_se_clks_off(se); 535 536 return ret; 537 } 538 EXPORT_SYMBOL(geni_se_resources_on); 539 540 /** 541 * geni_se_clk_tbl_get() - Get the clock table to program DFS 542 * @se: Pointer to the concerned serial engine. 543 * @tbl: Table in which the output is returned. 544 * 545 * This function is called by the protocol drivers to determine the different 546 * clock frequencies supported by serial engine core clock. The protocol 547 * drivers use the output to determine the clock frequency index to be 548 * programmed into DFS. 549 * 550 * Return: number of valid performance levels in the table on success, 551 * standard Linux error codes on failure. 552 */ 553 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl) 554 { 555 long freq = 0; 556 int i; 557 558 if (se->clk_perf_tbl) { 559 *tbl = se->clk_perf_tbl; 560 return se->num_clk_levels; 561 } 562 563 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL, 564 sizeof(*se->clk_perf_tbl), 565 GFP_KERNEL); 566 if (!se->clk_perf_tbl) 567 return -ENOMEM; 568 569 for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) { 570 freq = clk_round_rate(se->clk, freq + 1); 571 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1]) 572 break; 573 se->clk_perf_tbl[i] = freq; 574 } 575 se->num_clk_levels = i; 576 *tbl = se->clk_perf_tbl; 577 return se->num_clk_levels; 578 } 579 EXPORT_SYMBOL(geni_se_clk_tbl_get); 580 581 /** 582 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency 583 * @se: Pointer to the concerned serial engine. 584 * @req_freq: Requested clock frequency. 585 * @index: Index of the resultant frequency in the table. 586 * @res_freq: Resultant frequency of the source clock. 587 * @exact: Flag to indicate exact multiple requirement of the requested 588 * frequency. 589 * 590 * This function is called by the protocol drivers to determine the best match 591 * of the requested frequency as provided by the serial engine clock in order 592 * to meet the performance requirements. 593 * 594 * If we return success: 595 * - if @exact is true then @res_freq / <an_integer> == @req_freq 596 * - if @exact is false then @res_freq / <an_integer> <= @req_freq 597 * 598 * Return: 0 on success, standard Linux error codes on failure. 599 */ 600 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, 601 unsigned int *index, unsigned long *res_freq, 602 bool exact) 603 { 604 unsigned long *tbl; 605 int num_clk_levels; 606 int i; 607 unsigned long best_delta; 608 unsigned long new_delta; 609 unsigned int divider; 610 611 num_clk_levels = geni_se_clk_tbl_get(se, &tbl); 612 if (num_clk_levels < 0) 613 return num_clk_levels; 614 615 if (num_clk_levels == 0) 616 return -EINVAL; 617 618 best_delta = ULONG_MAX; 619 for (i = 0; i < num_clk_levels; i++) { 620 divider = DIV_ROUND_UP(tbl[i], req_freq); 621 new_delta = req_freq - tbl[i] / divider; 622 if (new_delta < best_delta) { 623 /* We have a new best! */ 624 *index = i; 625 *res_freq = tbl[i]; 626 627 /* If the new best is exact then we're done */ 628 if (new_delta == 0) 629 return 0; 630 631 /* Record how close we got */ 632 best_delta = new_delta; 633 } 634 } 635 636 if (exact) 637 return -EINVAL; 638 639 return 0; 640 } 641 EXPORT_SYMBOL(geni_se_clk_freq_match); 642 643 #define GENI_SE_DMA_DONE_EN BIT(0) 644 #define GENI_SE_DMA_EOT_EN BIT(1) 645 #define GENI_SE_DMA_AHB_ERR_EN BIT(2) 646 #define GENI_SE_DMA_EOT_BUF BIT(0) 647 /** 648 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer 649 * @se: Pointer to the concerned serial engine. 650 * @buf: Pointer to the TX buffer. 651 * @len: Length of the TX buffer. 652 * @iova: Pointer to store the mapped DMA address. 653 * 654 * This function is used to prepare the buffers for DMA TX. 655 * 656 * Return: 0 on success, standard Linux error codes on failure. 657 */ 658 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, 659 dma_addr_t *iova) 660 { 661 struct geni_wrapper *wrapper = se->wrapper; 662 u32 val; 663 664 if (!wrapper) 665 return -EINVAL; 666 667 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE); 668 if (dma_mapping_error(wrapper->dev, *iova)) 669 return -EIO; 670 671 val = GENI_SE_DMA_DONE_EN; 672 val |= GENI_SE_DMA_EOT_EN; 673 val |= GENI_SE_DMA_AHB_ERR_EN; 674 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); 675 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L); 676 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H); 677 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); 678 writel(len, se->base + SE_DMA_TX_LEN); 679 return 0; 680 } 681 EXPORT_SYMBOL(geni_se_tx_dma_prep); 682 683 /** 684 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer 685 * @se: Pointer to the concerned serial engine. 686 * @buf: Pointer to the RX buffer. 687 * @len: Length of the RX buffer. 688 * @iova: Pointer to store the mapped DMA address. 689 * 690 * This function is used to prepare the buffers for DMA RX. 691 * 692 * Return: 0 on success, standard Linux error codes on failure. 693 */ 694 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, 695 dma_addr_t *iova) 696 { 697 struct geni_wrapper *wrapper = se->wrapper; 698 u32 val; 699 700 if (!wrapper) 701 return -EINVAL; 702 703 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE); 704 if (dma_mapping_error(wrapper->dev, *iova)) 705 return -EIO; 706 707 val = GENI_SE_DMA_DONE_EN; 708 val |= GENI_SE_DMA_EOT_EN; 709 val |= GENI_SE_DMA_AHB_ERR_EN; 710 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); 711 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L); 712 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H); 713 /* RX does not have EOT buffer type bit. So just reset RX_ATTR */ 714 writel_relaxed(0, se->base + SE_DMA_RX_ATTR); 715 writel(len, se->base + SE_DMA_RX_LEN); 716 return 0; 717 } 718 EXPORT_SYMBOL(geni_se_rx_dma_prep); 719 720 /** 721 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer 722 * @se: Pointer to the concerned serial engine. 723 * @iova: DMA address of the TX buffer. 724 * @len: Length of the TX buffer. 725 * 726 * This function is used to unprepare the DMA buffers after DMA TX. 727 */ 728 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) 729 { 730 struct geni_wrapper *wrapper = se->wrapper; 731 732 if (!dma_mapping_error(wrapper->dev, iova)) 733 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE); 734 } 735 EXPORT_SYMBOL(geni_se_tx_dma_unprep); 736 737 /** 738 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer 739 * @se: Pointer to the concerned serial engine. 740 * @iova: DMA address of the RX buffer. 741 * @len: Length of the RX buffer. 742 * 743 * This function is used to unprepare the DMA buffers after DMA RX. 744 */ 745 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) 746 { 747 struct geni_wrapper *wrapper = se->wrapper; 748 749 if (!dma_mapping_error(wrapper->dev, iova)) 750 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE); 751 } 752 EXPORT_SYMBOL(geni_se_rx_dma_unprep); 753 754 int geni_icc_get(struct geni_se *se, const char *icc_ddr) 755 { 756 int i, err; 757 const char *icc_names[] = {"qup-core", "qup-config", icc_ddr}; 758 759 if (has_acpi_companion(se->dev)) 760 return 0; 761 762 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 763 if (!icc_names[i]) 764 continue; 765 766 se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]); 767 if (IS_ERR(se->icc_paths[i].path)) 768 goto err; 769 } 770 771 return 0; 772 773 err: 774 err = PTR_ERR(se->icc_paths[i].path); 775 if (err != -EPROBE_DEFER) 776 dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n", 777 icc_names[i], err); 778 return err; 779 780 } 781 EXPORT_SYMBOL(geni_icc_get); 782 783 int geni_icc_set_bw(struct geni_se *se) 784 { 785 int i, ret; 786 787 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 788 ret = icc_set_bw(se->icc_paths[i].path, 789 se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw); 790 if (ret) { 791 dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n", 792 icc_path_names[i], ret); 793 return ret; 794 } 795 } 796 797 return 0; 798 } 799 EXPORT_SYMBOL(geni_icc_set_bw); 800 801 void geni_icc_set_tag(struct geni_se *se, u32 tag) 802 { 803 int i; 804 805 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) 806 icc_set_tag(se->icc_paths[i].path, tag); 807 } 808 EXPORT_SYMBOL(geni_icc_set_tag); 809 810 /* To do: Replace this by icc_bulk_enable once it's implemented in ICC core */ 811 int geni_icc_enable(struct geni_se *se) 812 { 813 int i, ret; 814 815 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 816 ret = icc_enable(se->icc_paths[i].path); 817 if (ret) { 818 dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n", 819 icc_path_names[i], ret); 820 return ret; 821 } 822 } 823 824 return 0; 825 } 826 EXPORT_SYMBOL(geni_icc_enable); 827 828 int geni_icc_disable(struct geni_se *se) 829 { 830 int i, ret; 831 832 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 833 ret = icc_disable(se->icc_paths[i].path); 834 if (ret) { 835 dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n", 836 icc_path_names[i], ret); 837 return ret; 838 } 839 } 840 841 return 0; 842 } 843 EXPORT_SYMBOL(geni_icc_disable); 844 845 static int geni_se_probe(struct platform_device *pdev) 846 { 847 struct device *dev = &pdev->dev; 848 struct resource *res; 849 struct geni_wrapper *wrapper; 850 int ret; 851 852 wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL); 853 if (!wrapper) 854 return -ENOMEM; 855 856 wrapper->dev = dev; 857 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 858 wrapper->base = devm_ioremap_resource(dev, res); 859 if (IS_ERR(wrapper->base)) 860 return PTR_ERR(wrapper->base); 861 862 if (!has_acpi_companion(&pdev->dev)) { 863 wrapper->ahb_clks[0].id = "m-ahb"; 864 wrapper->ahb_clks[1].id = "s-ahb"; 865 ret = devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks); 866 if (ret) { 867 dev_err(dev, "Err getting AHB clks %d\n", ret); 868 return ret; 869 } 870 } 871 872 dev_set_drvdata(dev, wrapper); 873 dev_dbg(dev, "GENI SE Driver probed\n"); 874 return devm_of_platform_populate(dev); 875 } 876 877 static const struct of_device_id geni_se_dt_match[] = { 878 { .compatible = "qcom,geni-se-qup", }, 879 {} 880 }; 881 MODULE_DEVICE_TABLE(of, geni_se_dt_match); 882 883 static struct platform_driver geni_se_driver = { 884 .driver = { 885 .name = "geni_se_qup", 886 .of_match_table = geni_se_dt_match, 887 }, 888 .probe = geni_se_probe, 889 }; 890 module_platform_driver(geni_se_driver); 891 892 MODULE_DESCRIPTION("GENI Serial Engine Driver"); 893 MODULE_LICENSE("GPL v2"); 894