1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 3 4 #include <linux/acpi.h> 5 #include <linux/clk.h> 6 #include <linux/console.h> 7 #include <linux/slab.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/pinctrl/consumer.h> 14 #include <linux/platform_device.h> 15 #include <linux/qcom-geni-se.h> 16 17 /** 18 * DOC: Overview 19 * 20 * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced 21 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper 22 * controller. QUP Wrapper is designed to support various serial bus protocols 23 * like UART, SPI, I2C, I3C, etc. 24 */ 25 26 /** 27 * DOC: Hardware description 28 * 29 * GENI based QUP is a highly-flexible and programmable module for supporting 30 * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single 31 * QUP module can provide upto 8 serial interfaces, using its internal 32 * serial engines. The actual configuration is determined by the target 33 * platform configuration. The protocol supported by each interface is 34 * determined by the firmware loaded to the serial engine. Each SE consists 35 * of a DMA Engine and GENI sub modules which enable serial engines to 36 * support FIFO and DMA modes of operation. 37 * 38 * 39 * +-----------------------------------------+ 40 * |QUP Wrapper | 41 * | +----------------------------+ | 42 * --QUP & SE Clocks--> | Serial Engine N | +-IO------> 43 * | | ... | | Interface 44 * <---Clock Perf.----+ +----+-----------------------+ | | 45 * State Interface | | Serial Engine 1 | | | 46 * | | | | | 47 * | | | | | 48 * <--------AHB-------> | | | | 49 * | | +----+ | 50 * | | | | 51 * | | | | 52 * <------SE IRQ------+ +----------------------------+ | 53 * | | 54 * +-----------------------------------------+ 55 * 56 * Figure 1: GENI based QUP Wrapper 57 * 58 * The GENI submodules include primary and secondary sequencers which are 59 * used to drive TX & RX operations. On serial interfaces that operate using 60 * master-slave model, primary sequencer drives both TX & RX operations. On 61 * serial interfaces that operate using peer-to-peer model, primary sequencer 62 * drives TX operation and secondary sequencer drives RX operation. 63 */ 64 65 /** 66 * DOC: Software description 67 * 68 * GENI SE Wrapper driver is structured into 2 parts: 69 * 70 * geni_wrapper represents QUP Wrapper controller. This part of the driver 71 * manages QUP Wrapper information such as hardware version, clock 72 * performance table that is common to all the internal serial engines. 73 * 74 * geni_se represents serial engine. This part of the driver manages serial 75 * engine information such as clocks, containing QUP Wrapper, etc. This part 76 * of driver also supports operations (eg. initialize the concerned serial 77 * engine, select between FIFO and DMA mode of operation etc.) that are 78 * common to all the serial engines and are independent of serial interfaces. 79 */ 80 81 #define MAX_CLK_PERF_LEVEL 32 82 #define NUM_AHB_CLKS 2 83 84 /** 85 * struct geni_wrapper - Data structure to represent the QUP Wrapper Core 86 * @dev: Device pointer of the QUP wrapper core 87 * @base: Base address of this instance of QUP wrapper core 88 * @ahb_clks: Handle to the primary & secondary AHB clocks 89 * @to_core: Core ICC path 90 */ 91 struct geni_wrapper { 92 struct device *dev; 93 void __iomem *base; 94 struct clk_bulk_data ahb_clks[NUM_AHB_CLKS]; 95 struct geni_icc_path to_core; 96 }; 97 98 static const char * const icc_path_names[] = {"qup-core", "qup-config", 99 "qup-memory"}; 100 101 static struct geni_wrapper *earlycon_wrapper; 102 103 #define QUP_HW_VER_REG 0x4 104 105 /* Common SE registers */ 106 #define GENI_INIT_CFG_REVISION 0x0 107 #define GENI_S_INIT_CFG_REVISION 0x4 108 #define GENI_OUTPUT_CTRL 0x24 109 #define GENI_CGC_CTRL 0x28 110 #define GENI_CLK_CTRL_RO 0x60 111 #define GENI_IF_DISABLE_RO 0x64 112 #define GENI_FW_S_REVISION_RO 0x6c 113 #define SE_GENI_BYTE_GRAN 0x254 114 #define SE_GENI_TX_PACKING_CFG0 0x260 115 #define SE_GENI_TX_PACKING_CFG1 0x264 116 #define SE_GENI_RX_PACKING_CFG0 0x284 117 #define SE_GENI_RX_PACKING_CFG1 0x288 118 #define SE_GENI_M_GP_LENGTH 0x910 119 #define SE_GENI_S_GP_LENGTH 0x914 120 #define SE_DMA_TX_PTR_L 0xc30 121 #define SE_DMA_TX_PTR_H 0xc34 122 #define SE_DMA_TX_ATTR 0xc38 123 #define SE_DMA_TX_LEN 0xc3c 124 #define SE_DMA_TX_IRQ_EN 0xc48 125 #define SE_DMA_TX_IRQ_EN_SET 0xc4c 126 #define SE_DMA_TX_IRQ_EN_CLR 0xc50 127 #define SE_DMA_TX_LEN_IN 0xc54 128 #define SE_DMA_TX_MAX_BURST 0xc5c 129 #define SE_DMA_RX_PTR_L 0xd30 130 #define SE_DMA_RX_PTR_H 0xd34 131 #define SE_DMA_RX_ATTR 0xd38 132 #define SE_DMA_RX_LEN 0xd3c 133 #define SE_DMA_RX_IRQ_EN 0xd48 134 #define SE_DMA_RX_IRQ_EN_SET 0xd4c 135 #define SE_DMA_RX_IRQ_EN_CLR 0xd50 136 #define SE_DMA_RX_LEN_IN 0xd54 137 #define SE_DMA_RX_MAX_BURST 0xd5c 138 #define SE_DMA_RX_FLUSH 0xd60 139 #define SE_GSI_EVENT_EN 0xe18 140 #define SE_IRQ_EN 0xe1c 141 #define SE_DMA_GENERAL_CFG 0xe30 142 143 /* GENI_OUTPUT_CTRL fields */ 144 #define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0) 145 146 /* GENI_CGC_CTRL fields */ 147 #define CFG_AHB_CLK_CGC_ON BIT(0) 148 #define CFG_AHB_WR_ACLK_CGC_ON BIT(1) 149 #define DATA_AHB_CLK_CGC_ON BIT(2) 150 #define SCLK_CGC_ON BIT(3) 151 #define TX_CLK_CGC_ON BIT(4) 152 #define RX_CLK_CGC_ON BIT(5) 153 #define EXT_CLK_CGC_ON BIT(6) 154 #define PROG_RAM_HCLK_OFF BIT(8) 155 #define PROG_RAM_SCLK_OFF BIT(9) 156 #define DEFAULT_CGC_EN GENMASK(6, 0) 157 158 /* SE_GSI_EVENT_EN fields */ 159 #define DMA_RX_EVENT_EN BIT(0) 160 #define DMA_TX_EVENT_EN BIT(1) 161 #define GENI_M_EVENT_EN BIT(2) 162 #define GENI_S_EVENT_EN BIT(3) 163 164 /* SE_IRQ_EN fields */ 165 #define DMA_RX_IRQ_EN BIT(0) 166 #define DMA_TX_IRQ_EN BIT(1) 167 #define GENI_M_IRQ_EN BIT(2) 168 #define GENI_S_IRQ_EN BIT(3) 169 170 /* SE_DMA_GENERAL_CFG */ 171 #define DMA_RX_CLK_CGC_ON BIT(0) 172 #define DMA_TX_CLK_CGC_ON BIT(1) 173 #define DMA_AHB_SLV_CFG_ON BIT(2) 174 #define AHB_SEC_SLV_CLK_CGC_ON BIT(3) 175 #define DUMMY_RX_NON_BUFFERABLE BIT(4) 176 #define RX_DMA_ZERO_PADDING_EN BIT(5) 177 #define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6) 178 #define RX_DMA_IRQ_DELAY_SHFT 6 179 180 /** 181 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version 182 * @se: Pointer to the corresponding serial engine. 183 * 184 * Return: Hardware Version of the wrapper. 185 */ 186 u32 geni_se_get_qup_hw_version(struct geni_se *se) 187 { 188 struct geni_wrapper *wrapper = se->wrapper; 189 190 return readl_relaxed(wrapper->base + QUP_HW_VER_REG); 191 } 192 EXPORT_SYMBOL(geni_se_get_qup_hw_version); 193 194 static void geni_se_io_set_mode(void __iomem *base) 195 { 196 u32 val; 197 198 val = readl_relaxed(base + SE_IRQ_EN); 199 val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN; 200 val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN; 201 writel_relaxed(val, base + SE_IRQ_EN); 202 203 val = readl_relaxed(base + SE_GENI_DMA_MODE_EN); 204 val &= ~GENI_DMA_MODE_EN; 205 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN); 206 207 writel_relaxed(0, base + SE_GSI_EVENT_EN); 208 } 209 210 static void geni_se_io_init(void __iomem *base) 211 { 212 u32 val; 213 214 val = readl_relaxed(base + GENI_CGC_CTRL); 215 val |= DEFAULT_CGC_EN; 216 writel_relaxed(val, base + GENI_CGC_CTRL); 217 218 val = readl_relaxed(base + SE_DMA_GENERAL_CFG); 219 val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON; 220 val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON; 221 writel_relaxed(val, base + SE_DMA_GENERAL_CFG); 222 223 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL); 224 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG); 225 } 226 227 static void geni_se_irq_clear(struct geni_se *se) 228 { 229 writel_relaxed(0, se->base + SE_GSI_EVENT_EN); 230 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR); 231 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR); 232 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR); 233 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR); 234 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN); 235 } 236 237 /** 238 * geni_se_init() - Initialize the GENI serial engine 239 * @se: Pointer to the concerned serial engine. 240 * @rx_wm: Receive watermark, in units of FIFO words. 241 * @rx_rfr: Ready-for-receive watermark, in units of FIFO words. 242 * 243 * This function is used to initialize the GENI serial engine, configure 244 * receive watermark and ready-for-receive watermarks. 245 */ 246 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr) 247 { 248 u32 val; 249 250 geni_se_irq_clear(se); 251 geni_se_io_init(se->base); 252 geni_se_io_set_mode(se->base); 253 254 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG); 255 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG); 256 257 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 258 val |= M_COMMON_GENI_M_IRQ_EN; 259 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 260 261 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 262 val |= S_COMMON_GENI_S_IRQ_EN; 263 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 264 } 265 EXPORT_SYMBOL(geni_se_init); 266 267 static void geni_se_select_fifo_mode(struct geni_se *se) 268 { 269 u32 proto = geni_se_read_proto(se); 270 u32 val, val_old; 271 272 geni_se_irq_clear(se); 273 274 /* 275 * The RX path for the UART is asynchronous and so needs more 276 * complex logic for enabling / disabling its interrupts. 277 * 278 * Specific notes: 279 * - The done and TX-related interrupts are managed manually. 280 * - We don't RX from the main sequencer (we use the secondary) so 281 * we don't need the RX-related interrupts enabled in the main 282 * sequencer for UART. 283 */ 284 if (proto != GENI_SE_UART) { 285 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 286 val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN; 287 val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 288 if (val != val_old) 289 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 290 291 val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 292 val |= S_CMD_DONE_EN; 293 if (val != val_old) 294 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 295 } 296 297 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 298 val &= ~GENI_DMA_MODE_EN; 299 if (val != val_old) 300 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 301 } 302 303 static void geni_se_select_dma_mode(struct geni_se *se) 304 { 305 u32 proto = geni_se_read_proto(se); 306 u32 val, val_old; 307 308 geni_se_irq_clear(se); 309 310 if (proto != GENI_SE_UART) { 311 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 312 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 313 val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 314 if (val != val_old) 315 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 316 317 val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 318 val &= ~S_CMD_DONE_EN; 319 if (val != val_old) 320 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 321 } 322 323 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 324 val |= GENI_DMA_MODE_EN; 325 if (val != val_old) 326 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 327 } 328 329 /** 330 * geni_se_select_mode() - Select the serial engine transfer mode 331 * @se: Pointer to the concerned serial engine. 332 * @mode: Transfer mode to be selected. 333 */ 334 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode) 335 { 336 WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA); 337 338 switch (mode) { 339 case GENI_SE_FIFO: 340 geni_se_select_fifo_mode(se); 341 break; 342 case GENI_SE_DMA: 343 geni_se_select_dma_mode(se); 344 break; 345 case GENI_SE_INVALID: 346 default: 347 break; 348 } 349 } 350 EXPORT_SYMBOL(geni_se_select_mode); 351 352 /** 353 * DOC: Overview 354 * 355 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist 356 * of up to 4 operations, each operation represented by 4 configuration vectors 357 * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for 358 * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO. 359 * Refer to below examples for detailed bit-field description. 360 * 361 * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1 362 * 363 * +-----------+-------+-------+-------+-------+ 364 * | | vec_0 | vec_1 | vec_2 | vec_3 | 365 * +-----------+-------+-------+-------+-------+ 366 * | start | 0x6 | 0xe | 0x16 | 0x1e | 367 * | direction | 1 | 1 | 1 | 1 | 368 * | length | 6 | 6 | 6 | 6 | 369 * | stop | 0 | 0 | 0 | 1 | 370 * +-----------+-------+-------+-------+-------+ 371 * 372 * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0 373 * 374 * +-----------+-------+-------+-------+-------+ 375 * | | vec_0 | vec_1 | vec_2 | vec_3 | 376 * +-----------+-------+-------+-------+-------+ 377 * | start | 0x0 | 0x8 | 0x10 | 0x18 | 378 * | direction | 0 | 0 | 0 | 0 | 379 * | length | 7 | 6 | 7 | 6 | 380 * | stop | 0 | 0 | 0 | 1 | 381 * +-----------+-------+-------+-------+-------+ 382 * 383 * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1 384 * 385 * +-----------+-------+-------+-------+-------+ 386 * | | vec_0 | vec_1 | vec_2 | vec_3 | 387 * +-----------+-------+-------+-------+-------+ 388 * | start | 0x16 | 0xe | 0x6 | 0x0 | 389 * | direction | 1 | 1 | 1 | 1 | 390 * | length | 7 | 7 | 6 | 0 | 391 * | stop | 0 | 0 | 1 | 0 | 392 * +-----------+-------+-------+-------+-------+ 393 * 394 */ 395 396 #define NUM_PACKING_VECTORS 4 397 #define PACKING_START_SHIFT 5 398 #define PACKING_DIR_SHIFT 4 399 #define PACKING_LEN_SHIFT 1 400 #define PACKING_STOP_BIT BIT(0) 401 #define PACKING_VECTOR_SHIFT 10 402 /** 403 * geni_se_config_packing() - Packing configuration of the serial engine 404 * @se: Pointer to the concerned serial engine 405 * @bpw: Bits of data per transfer word. 406 * @pack_words: Number of words per fifo element. 407 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa. 408 * @tx_cfg: Flag to configure the TX Packing. 409 * @rx_cfg: Flag to configure the RX Packing. 410 * 411 * This function is used to configure the packing rules for the current 412 * transfer. 413 */ 414 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words, 415 bool msb_to_lsb, bool tx_cfg, bool rx_cfg) 416 { 417 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0}; 418 int len; 419 int temp_bpw = bpw; 420 int idx_start = msb_to_lsb ? bpw - 1 : 0; 421 int idx = idx_start; 422 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE; 423 int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE); 424 int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE; 425 int i; 426 427 if (iter <= 0 || iter > NUM_PACKING_VECTORS) 428 return; 429 430 for (i = 0; i < iter; i++) { 431 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1; 432 cfg[i] = idx << PACKING_START_SHIFT; 433 cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT; 434 cfg[i] |= len << PACKING_LEN_SHIFT; 435 436 if (temp_bpw <= BITS_PER_BYTE) { 437 idx = ((i + 1) * BITS_PER_BYTE) + idx_start; 438 temp_bpw = bpw; 439 } else { 440 idx = idx + idx_delta; 441 temp_bpw = temp_bpw - BITS_PER_BYTE; 442 } 443 } 444 cfg[iter - 1] |= PACKING_STOP_BIT; 445 cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT); 446 cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT); 447 448 if (tx_cfg) { 449 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); 450 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); 451 } 452 if (rx_cfg) { 453 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); 454 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); 455 } 456 457 /* 458 * Number of protocol words in each FIFO entry 459 * 0 - 4x8, four words in each entry, max word size of 8 bits 460 * 1 - 2x16, two words in each entry, max word size of 16 bits 461 * 2 - 1x32, one word in each entry, max word size of 32 bits 462 * 3 - undefined 463 */ 464 if (pack_words || bpw == 32) 465 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN); 466 } 467 EXPORT_SYMBOL(geni_se_config_packing); 468 469 static void geni_se_clks_off(struct geni_se *se) 470 { 471 struct geni_wrapper *wrapper = se->wrapper; 472 473 clk_disable_unprepare(se->clk); 474 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), 475 wrapper->ahb_clks); 476 } 477 478 /** 479 * geni_se_resources_off() - Turn off resources associated with the serial 480 * engine 481 * @se: Pointer to the concerned serial engine. 482 * 483 * Return: 0 on success, standard Linux error codes on failure/error. 484 */ 485 int geni_se_resources_off(struct geni_se *se) 486 { 487 int ret; 488 489 if (has_acpi_companion(se->dev)) 490 return 0; 491 492 ret = pinctrl_pm_select_sleep_state(se->dev); 493 if (ret) 494 return ret; 495 496 geni_se_clks_off(se); 497 return 0; 498 } 499 EXPORT_SYMBOL(geni_se_resources_off); 500 501 static int geni_se_clks_on(struct geni_se *se) 502 { 503 int ret; 504 struct geni_wrapper *wrapper = se->wrapper; 505 506 ret = clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks), 507 wrapper->ahb_clks); 508 if (ret) 509 return ret; 510 511 ret = clk_prepare_enable(se->clk); 512 if (ret) 513 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), 514 wrapper->ahb_clks); 515 return ret; 516 } 517 518 /** 519 * geni_se_resources_on() - Turn on resources associated with the serial 520 * engine 521 * @se: Pointer to the concerned serial engine. 522 * 523 * Return: 0 on success, standard Linux error codes on failure/error. 524 */ 525 int geni_se_resources_on(struct geni_se *se) 526 { 527 int ret; 528 529 if (has_acpi_companion(se->dev)) 530 return 0; 531 532 ret = geni_se_clks_on(se); 533 if (ret) 534 return ret; 535 536 ret = pinctrl_pm_select_default_state(se->dev); 537 if (ret) 538 geni_se_clks_off(se); 539 540 return ret; 541 } 542 EXPORT_SYMBOL(geni_se_resources_on); 543 544 /** 545 * geni_se_clk_tbl_get() - Get the clock table to program DFS 546 * @se: Pointer to the concerned serial engine. 547 * @tbl: Table in which the output is returned. 548 * 549 * This function is called by the protocol drivers to determine the different 550 * clock frequencies supported by serial engine core clock. The protocol 551 * drivers use the output to determine the clock frequency index to be 552 * programmed into DFS. 553 * 554 * Return: number of valid performance levels in the table on success, 555 * standard Linux error codes on failure. 556 */ 557 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl) 558 { 559 long freq = 0; 560 int i; 561 562 if (se->clk_perf_tbl) { 563 *tbl = se->clk_perf_tbl; 564 return se->num_clk_levels; 565 } 566 567 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL, 568 sizeof(*se->clk_perf_tbl), 569 GFP_KERNEL); 570 if (!se->clk_perf_tbl) 571 return -ENOMEM; 572 573 for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) { 574 freq = clk_round_rate(se->clk, freq + 1); 575 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1]) 576 break; 577 se->clk_perf_tbl[i] = freq; 578 } 579 se->num_clk_levels = i; 580 *tbl = se->clk_perf_tbl; 581 return se->num_clk_levels; 582 } 583 EXPORT_SYMBOL(geni_se_clk_tbl_get); 584 585 /** 586 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency 587 * @se: Pointer to the concerned serial engine. 588 * @req_freq: Requested clock frequency. 589 * @index: Index of the resultant frequency in the table. 590 * @res_freq: Resultant frequency of the source clock. 591 * @exact: Flag to indicate exact multiple requirement of the requested 592 * frequency. 593 * 594 * This function is called by the protocol drivers to determine the best match 595 * of the requested frequency as provided by the serial engine clock in order 596 * to meet the performance requirements. 597 * 598 * If we return success: 599 * - if @exact is true then @res_freq / <an_integer> == @req_freq 600 * - if @exact is false then @res_freq / <an_integer> <= @req_freq 601 * 602 * Return: 0 on success, standard Linux error codes on failure. 603 */ 604 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, 605 unsigned int *index, unsigned long *res_freq, 606 bool exact) 607 { 608 unsigned long *tbl; 609 int num_clk_levels; 610 int i; 611 unsigned long best_delta; 612 unsigned long new_delta; 613 unsigned int divider; 614 615 num_clk_levels = geni_se_clk_tbl_get(se, &tbl); 616 if (num_clk_levels < 0) 617 return num_clk_levels; 618 619 if (num_clk_levels == 0) 620 return -EINVAL; 621 622 best_delta = ULONG_MAX; 623 for (i = 0; i < num_clk_levels; i++) { 624 divider = DIV_ROUND_UP(tbl[i], req_freq); 625 new_delta = req_freq - tbl[i] / divider; 626 if (new_delta < best_delta) { 627 /* We have a new best! */ 628 *index = i; 629 *res_freq = tbl[i]; 630 631 /* If the new best is exact then we're done */ 632 if (new_delta == 0) 633 return 0; 634 635 /* Record how close we got */ 636 best_delta = new_delta; 637 } 638 } 639 640 if (exact) 641 return -EINVAL; 642 643 return 0; 644 } 645 EXPORT_SYMBOL(geni_se_clk_freq_match); 646 647 #define GENI_SE_DMA_DONE_EN BIT(0) 648 #define GENI_SE_DMA_EOT_EN BIT(1) 649 #define GENI_SE_DMA_AHB_ERR_EN BIT(2) 650 #define GENI_SE_DMA_EOT_BUF BIT(0) 651 /** 652 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer 653 * @se: Pointer to the concerned serial engine. 654 * @buf: Pointer to the TX buffer. 655 * @len: Length of the TX buffer. 656 * @iova: Pointer to store the mapped DMA address. 657 * 658 * This function is used to prepare the buffers for DMA TX. 659 * 660 * Return: 0 on success, standard Linux error codes on failure. 661 */ 662 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, 663 dma_addr_t *iova) 664 { 665 struct geni_wrapper *wrapper = se->wrapper; 666 u32 val; 667 668 if (!wrapper) 669 return -EINVAL; 670 671 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE); 672 if (dma_mapping_error(wrapper->dev, *iova)) 673 return -EIO; 674 675 val = GENI_SE_DMA_DONE_EN; 676 val |= GENI_SE_DMA_EOT_EN; 677 val |= GENI_SE_DMA_AHB_ERR_EN; 678 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); 679 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L); 680 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H); 681 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); 682 writel(len, se->base + SE_DMA_TX_LEN); 683 return 0; 684 } 685 EXPORT_SYMBOL(geni_se_tx_dma_prep); 686 687 /** 688 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer 689 * @se: Pointer to the concerned serial engine. 690 * @buf: Pointer to the RX buffer. 691 * @len: Length of the RX buffer. 692 * @iova: Pointer to store the mapped DMA address. 693 * 694 * This function is used to prepare the buffers for DMA RX. 695 * 696 * Return: 0 on success, standard Linux error codes on failure. 697 */ 698 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, 699 dma_addr_t *iova) 700 { 701 struct geni_wrapper *wrapper = se->wrapper; 702 u32 val; 703 704 if (!wrapper) 705 return -EINVAL; 706 707 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE); 708 if (dma_mapping_error(wrapper->dev, *iova)) 709 return -EIO; 710 711 val = GENI_SE_DMA_DONE_EN; 712 val |= GENI_SE_DMA_EOT_EN; 713 val |= GENI_SE_DMA_AHB_ERR_EN; 714 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); 715 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L); 716 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H); 717 /* RX does not have EOT buffer type bit. So just reset RX_ATTR */ 718 writel_relaxed(0, se->base + SE_DMA_RX_ATTR); 719 writel(len, se->base + SE_DMA_RX_LEN); 720 return 0; 721 } 722 EXPORT_SYMBOL(geni_se_rx_dma_prep); 723 724 /** 725 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer 726 * @se: Pointer to the concerned serial engine. 727 * @iova: DMA address of the TX buffer. 728 * @len: Length of the TX buffer. 729 * 730 * This function is used to unprepare the DMA buffers after DMA TX. 731 */ 732 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) 733 { 734 struct geni_wrapper *wrapper = se->wrapper; 735 736 if (iova && !dma_mapping_error(wrapper->dev, iova)) 737 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE); 738 } 739 EXPORT_SYMBOL(geni_se_tx_dma_unprep); 740 741 /** 742 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer 743 * @se: Pointer to the concerned serial engine. 744 * @iova: DMA address of the RX buffer. 745 * @len: Length of the RX buffer. 746 * 747 * This function is used to unprepare the DMA buffers after DMA RX. 748 */ 749 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) 750 { 751 struct geni_wrapper *wrapper = se->wrapper; 752 753 if (iova && !dma_mapping_error(wrapper->dev, iova)) 754 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE); 755 } 756 EXPORT_SYMBOL(geni_se_rx_dma_unprep); 757 758 int geni_icc_get(struct geni_se *se, const char *icc_ddr) 759 { 760 int i, err; 761 const char *icc_names[] = {"qup-core", "qup-config", icc_ddr}; 762 763 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 764 if (!icc_names[i]) 765 continue; 766 767 se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]); 768 if (IS_ERR(se->icc_paths[i].path)) 769 goto err; 770 } 771 772 return 0; 773 774 err: 775 err = PTR_ERR(se->icc_paths[i].path); 776 if (err != -EPROBE_DEFER) 777 dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n", 778 icc_names[i], err); 779 return err; 780 781 } 782 EXPORT_SYMBOL(geni_icc_get); 783 784 int geni_icc_set_bw(struct geni_se *se) 785 { 786 int i, ret; 787 788 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 789 ret = icc_set_bw(se->icc_paths[i].path, 790 se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw); 791 if (ret) { 792 dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n", 793 icc_path_names[i], ret); 794 return ret; 795 } 796 } 797 798 return 0; 799 } 800 EXPORT_SYMBOL(geni_icc_set_bw); 801 802 void geni_icc_set_tag(struct geni_se *se, u32 tag) 803 { 804 int i; 805 806 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) 807 icc_set_tag(se->icc_paths[i].path, tag); 808 } 809 EXPORT_SYMBOL(geni_icc_set_tag); 810 811 /* To do: Replace this by icc_bulk_enable once it's implemented in ICC core */ 812 int geni_icc_enable(struct geni_se *se) 813 { 814 int i, ret; 815 816 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 817 ret = icc_enable(se->icc_paths[i].path); 818 if (ret) { 819 dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n", 820 icc_path_names[i], ret); 821 return ret; 822 } 823 } 824 825 return 0; 826 } 827 EXPORT_SYMBOL(geni_icc_enable); 828 829 int geni_icc_disable(struct geni_se *se) 830 { 831 int i, ret; 832 833 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 834 ret = icc_disable(se->icc_paths[i].path); 835 if (ret) { 836 dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n", 837 icc_path_names[i], ret); 838 return ret; 839 } 840 } 841 842 return 0; 843 } 844 EXPORT_SYMBOL(geni_icc_disable); 845 846 void geni_remove_earlycon_icc_vote(void) 847 { 848 struct platform_device *pdev; 849 struct geni_wrapper *wrapper; 850 struct device_node *parent; 851 struct device_node *child; 852 853 if (!earlycon_wrapper) 854 return; 855 856 wrapper = earlycon_wrapper; 857 parent = of_get_next_parent(wrapper->dev->of_node); 858 for_each_child_of_node(parent, child) { 859 if (!of_device_is_compatible(child, "qcom,geni-se-qup")) 860 continue; 861 862 pdev = of_find_device_by_node(child); 863 if (!pdev) 864 continue; 865 866 wrapper = platform_get_drvdata(pdev); 867 icc_put(wrapper->to_core.path); 868 wrapper->to_core.path = NULL; 869 870 } 871 of_node_put(parent); 872 873 earlycon_wrapper = NULL; 874 } 875 EXPORT_SYMBOL(geni_remove_earlycon_icc_vote); 876 877 static int geni_se_probe(struct platform_device *pdev) 878 { 879 struct device *dev = &pdev->dev; 880 struct resource *res; 881 struct geni_wrapper *wrapper; 882 struct console __maybe_unused *bcon; 883 bool __maybe_unused has_earlycon = false; 884 int ret; 885 886 wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL); 887 if (!wrapper) 888 return -ENOMEM; 889 890 wrapper->dev = dev; 891 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 892 wrapper->base = devm_ioremap_resource(dev, res); 893 if (IS_ERR(wrapper->base)) 894 return PTR_ERR(wrapper->base); 895 896 if (!has_acpi_companion(&pdev->dev)) { 897 wrapper->ahb_clks[0].id = "m-ahb"; 898 wrapper->ahb_clks[1].id = "s-ahb"; 899 ret = devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks); 900 if (ret) { 901 dev_err(dev, "Err getting AHB clks %d\n", ret); 902 return ret; 903 } 904 } 905 906 #ifdef CONFIG_SERIAL_EARLYCON 907 for_each_console(bcon) { 908 if (!strcmp(bcon->name, "qcom_geni")) { 909 has_earlycon = true; 910 break; 911 } 912 } 913 if (!has_earlycon) 914 goto exit; 915 916 wrapper->to_core.path = devm_of_icc_get(dev, "qup-core"); 917 if (IS_ERR(wrapper->to_core.path)) 918 return PTR_ERR(wrapper->to_core.path); 919 /* 920 * Put minmal BW request on core clocks on behalf of early console. 921 * The vote will be removed earlycon exit function. 922 * 923 * Note: We are putting vote on each QUP wrapper instead only to which 924 * earlycon is connected because QUP core clock of different wrapper 925 * share same voltage domain. If core1 is put to 0, then core2 will 926 * also run at 0, if not voted. Default ICC vote will be removed ASA 927 * we touch any of the core clock. 928 * core1 = core2 = max(core1, core2) 929 */ 930 ret = icc_set_bw(wrapper->to_core.path, GENI_DEFAULT_BW, 931 GENI_DEFAULT_BW); 932 if (ret) { 933 dev_err(&pdev->dev, "%s: ICC BW voting failed for core: %d\n", 934 __func__, ret); 935 return ret; 936 } 937 938 if (of_get_compatible_child(pdev->dev.of_node, "qcom,geni-debug-uart")) 939 earlycon_wrapper = wrapper; 940 of_node_put(pdev->dev.of_node); 941 exit: 942 #endif 943 dev_set_drvdata(dev, wrapper); 944 dev_dbg(dev, "GENI SE Driver probed\n"); 945 return devm_of_platform_populate(dev); 946 } 947 948 static const struct of_device_id geni_se_dt_match[] = { 949 { .compatible = "qcom,geni-se-qup", }, 950 {} 951 }; 952 MODULE_DEVICE_TABLE(of, geni_se_dt_match); 953 954 static struct platform_driver geni_se_driver = { 955 .driver = { 956 .name = "geni_se_qup", 957 .of_match_table = geni_se_dt_match, 958 }, 959 .probe = geni_se_probe, 960 }; 961 module_platform_driver(geni_se_driver); 962 963 MODULE_DESCRIPTION("GENI Serial Engine Driver"); 964 MODULE_LICENSE("GPL v2"); 965