1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bitmap.h> 9 #include <linux/bitops.h> 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/regmap.h> 18 #include <linux/sizes.h> 19 #include <linux/slab.h> 20 #include <linux/soc/qcom/llcc-qcom.h> 21 22 #define ACTIVATE BIT(0) 23 #define DEACTIVATE BIT(1) 24 #define ACT_CTRL_OPCODE_ACTIVATE BIT(0) 25 #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1) 26 #define ACT_CTRL_ACT_TRIG BIT(0) 27 #define ACT_CTRL_OPCODE_SHIFT 0x01 28 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02 29 #define ATTR1_FIXED_SIZE_SHIFT 0x03 30 #define ATTR1_PRIORITY_SHIFT 0x04 31 #define ATTR1_MAX_CAP_SHIFT 0x10 32 #define ATTR0_RES_WAYS_MASK GENMASK(11, 0) 33 #define ATTR0_BONUS_WAYS_MASK GENMASK(27, 16) 34 #define ATTR0_BONUS_WAYS_SHIFT 0x10 35 #define LLCC_STATUS_READ_DELAY 100 36 37 #define CACHE_LINE_SIZE_SHIFT 6 38 39 #define LLCC_COMMON_HW_INFO 0x00030000 40 #define LLCC_MAJOR_VERSION_MASK GENMASK(31, 24) 41 42 #define LLCC_COMMON_STATUS0 0x0003000c 43 #define LLCC_LB_CNT_MASK GENMASK(31, 28) 44 #define LLCC_LB_CNT_SHIFT 28 45 46 #define MAX_CAP_TO_BYTES(n) (n * SZ_1K) 47 #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K) 48 #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K) 49 #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) 50 #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) 51 52 #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 53 #define LLCC_TRP_PCB_ACT 0x21f04 54 #define LLCC_TRP_WRSC_EN 0x21f20 55 56 #define BANK_OFFSET_STRIDE 0x80000 57 58 /** 59 * struct llcc_slice_config - Data associated with the llcc slice 60 * @usecase_id: Unique id for the client's use case 61 * @slice_id: llcc slice id for each client 62 * @max_cap: The maximum capacity of the cache slice provided in KB 63 * @priority: Priority of the client used to select victim line for replacement 64 * @fixed_size: Boolean indicating if the slice has a fixed capacity 65 * @bonus_ways: Bonus ways are additional ways to be used for any slice, 66 * if client ends up using more than reserved cache ways. Bonus 67 * ways are allocated only if they are not reserved for some 68 * other client. 69 * @res_ways: Reserved ways for the cache slice, the reserved ways cannot 70 * be used by any other client than the one its assigned to. 71 * @cache_mode: Each slice operates as a cache, this controls the mode of the 72 * slice: normal or TCM(Tightly Coupled Memory) 73 * @probe_target_ways: Determines what ways to probe for access hit. When 74 * configured to 1 only bonus and reserved ways are probed. 75 * When configured to 0 all ways in llcc are probed. 76 * @dis_cap_alloc: Disable capacity based allocation for a client 77 * @retain_on_pc: If this bit is set and client has maintained active vote 78 * then the ways assigned to this client are not flushed on power 79 * collapse. 80 * @activate_on_init: Activate the slice immediately after it is programmed 81 * @write_scid_en: Bit enables write cache support for a given scid. 82 */ 83 struct llcc_slice_config { 84 u32 usecase_id; 85 u32 slice_id; 86 u32 max_cap; 87 u32 priority; 88 bool fixed_size; 89 u32 bonus_ways; 90 u32 res_ways; 91 u32 cache_mode; 92 u32 probe_target_ways; 93 bool dis_cap_alloc; 94 bool retain_on_pc; 95 bool activate_on_init; 96 bool write_scid_en; 97 }; 98 99 struct qcom_llcc_config { 100 const struct llcc_slice_config *sct_data; 101 int size; 102 bool need_llcc_cfg; 103 }; 104 105 static const struct llcc_slice_config sc7180_data[] = { 106 { LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 }, 107 { LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 108 { LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 109 { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 110 }; 111 112 static const struct llcc_slice_config sc7280_data[] = { 113 { LLCC_CPUSS, 1, 768, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 1, 0}, 114 { LLCC_MDMHPGRW, 7, 512, 2, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 115 { LLCC_CMPT, 10, 768, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 116 { LLCC_GPUHTW, 11, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 117 { LLCC_GPU, 12, 512, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 118 { LLCC_MMUHWT, 13, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 0, 1, 0}, 119 { LLCC_MDMPNG, 21, 768, 0, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 120 { LLCC_WLHW, 24, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 121 { LLCC_MODPE, 29, 64, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 122 }; 123 124 static const struct llcc_slice_config sdm845_data[] = { 125 { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 }, 126 { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 127 { LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 128 { LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 }, 129 { LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 130 { LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 131 { LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 }, 132 { LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 133 { LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 134 { LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 }, 135 { LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 }, 136 { LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 }, 137 { LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 138 { LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 139 { LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 140 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 }, 141 { LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 }, 142 { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 143 }; 144 145 static const struct llcc_slice_config sm6350_data[] = { 146 { LLCC_CPUSS, 1, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1 }, 147 { LLCC_MDM, 8, 512, 2, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 148 { LLCC_GPUHTW, 11, 256, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 149 { LLCC_GPU, 12, 512, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 150 { LLCC_MDMPNG, 21, 768, 0, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 151 { LLCC_NPU, 23, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 152 { LLCC_MODPE, 29, 64, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 153 }; 154 155 static const struct llcc_slice_config sm8150_data[] = { 156 { LLCC_CPUSS, 1, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1 }, 157 { LLCC_VIDSC0, 2, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 158 { LLCC_VIDSC1, 3, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 159 { LLCC_AUDIO, 6, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 160 { LLCC_MDMHPGRW, 7, 3072, 1, 0, 0xFF, 0xF00, 0, 0, 0, 1, 0 }, 161 { LLCC_MDM, 8, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 162 { LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 163 { LLCC_CMPT, 10, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 164 { LLCC_GPUHTW , 11, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 165 { LLCC_GPU, 12, 2560, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 166 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1 }, 167 { LLCC_CMPTDMA, 15, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 168 { LLCC_DISP, 16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 169 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 170 { LLCC_MDMHPFX, 21, 1024, 0, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 171 { LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 172 { LLCC_NPU, 23, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 173 { LLCC_WLHW, 24, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 174 { LLCC_MODPE, 29, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 175 { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 }, 176 { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 }, 177 }; 178 179 static const struct llcc_slice_config sm8250_data[] = { 180 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, 181 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 182 { LLCC_AUDIO, 6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 183 { LLCC_CMPT, 10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 184 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 185 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, 186 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 187 { LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 188 { LLCC_DISP, 16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 189 { LLCC_VIDFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 190 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 191 { LLCC_NPU, 23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 192 { LLCC_WLHW, 24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 193 { LLCC_CVP, 28, 256, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 194 { LLCC_APTCM, 30, 128, 3, 0, 0x0, 0x3, 1, 0, 0, 1, 0, 0 }, 195 { LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 196 }; 197 198 static const struct llcc_slice_config sm8350_data[] = { 199 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 1 }, 200 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 201 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 202 { LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 203 { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 204 { LLCC_CMPT, 10, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 205 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 206 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, 207 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, 208 { LLCC_DISP, 16, 3072, 2, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 209 { LLCC_MDMPNG, 21, 1024, 0, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 }, 210 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 211 { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 212 { LLCC_MODPE, 29, 256, 1, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 }, 213 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 0, 1, 0 }, 214 { LLCC_WRCACHE, 31, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, 215 { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 216 { LLCC_CPUSS1, 3, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 217 { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, 218 }; 219 220 static const struct qcom_llcc_config sc7180_cfg = { 221 .sct_data = sc7180_data, 222 .size = ARRAY_SIZE(sc7180_data), 223 .need_llcc_cfg = true, 224 }; 225 226 static const struct qcom_llcc_config sc7280_cfg = { 227 .sct_data = sc7280_data, 228 .size = ARRAY_SIZE(sc7280_data), 229 .need_llcc_cfg = true, 230 }; 231 232 static const struct qcom_llcc_config sdm845_cfg = { 233 .sct_data = sdm845_data, 234 .size = ARRAY_SIZE(sdm845_data), 235 .need_llcc_cfg = false, 236 }; 237 238 static const struct qcom_llcc_config sm6350_cfg = { 239 .sct_data = sm6350_data, 240 .size = ARRAY_SIZE(sm6350_data), 241 }; 242 243 static const struct qcom_llcc_config sm8150_cfg = { 244 .sct_data = sm8150_data, 245 .size = ARRAY_SIZE(sm8150_data), 246 }; 247 248 static const struct qcom_llcc_config sm8250_cfg = { 249 .sct_data = sm8250_data, 250 .size = ARRAY_SIZE(sm8250_data), 251 }; 252 253 static const struct qcom_llcc_config sm8350_cfg = { 254 .sct_data = sm8350_data, 255 .size = ARRAY_SIZE(sm8350_data), 256 }; 257 258 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; 259 260 /** 261 * llcc_slice_getd - get llcc slice descriptor 262 * @uid: usecase_id for the client 263 * 264 * A pointer to llcc slice descriptor will be returned on success and 265 * and error pointer is returned on failure 266 */ 267 struct llcc_slice_desc *llcc_slice_getd(u32 uid) 268 { 269 const struct llcc_slice_config *cfg; 270 struct llcc_slice_desc *desc; 271 u32 sz, count; 272 273 if (IS_ERR(drv_data)) 274 return ERR_CAST(drv_data); 275 276 cfg = drv_data->cfg; 277 sz = drv_data->cfg_size; 278 279 for (count = 0; cfg && count < sz; count++, cfg++) 280 if (cfg->usecase_id == uid) 281 break; 282 283 if (count == sz || !cfg) 284 return ERR_PTR(-ENODEV); 285 286 desc = kzalloc(sizeof(*desc), GFP_KERNEL); 287 if (!desc) 288 return ERR_PTR(-ENOMEM); 289 290 desc->slice_id = cfg->slice_id; 291 desc->slice_size = cfg->max_cap; 292 293 return desc; 294 } 295 EXPORT_SYMBOL_GPL(llcc_slice_getd); 296 297 /** 298 * llcc_slice_putd - llcc slice descritpor 299 * @desc: Pointer to llcc slice descriptor 300 */ 301 void llcc_slice_putd(struct llcc_slice_desc *desc) 302 { 303 if (!IS_ERR_OR_NULL(desc)) 304 kfree(desc); 305 } 306 EXPORT_SYMBOL_GPL(llcc_slice_putd); 307 308 static int llcc_update_act_ctrl(u32 sid, 309 u32 act_ctrl_reg_val, u32 status) 310 { 311 u32 act_ctrl_reg; 312 u32 status_reg; 313 u32 slice_status; 314 int ret; 315 316 if (IS_ERR(drv_data)) 317 return PTR_ERR(drv_data); 318 319 act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid); 320 status_reg = LLCC_TRP_STATUSn(sid); 321 322 /* Set the ACTIVE trigger */ 323 act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG; 324 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 325 act_ctrl_reg_val); 326 if (ret) 327 return ret; 328 329 /* Clear the ACTIVE trigger */ 330 act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG; 331 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 332 act_ctrl_reg_val); 333 if (ret) 334 return ret; 335 336 ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg, 337 slice_status, !(slice_status & status), 338 0, LLCC_STATUS_READ_DELAY); 339 return ret; 340 } 341 342 /** 343 * llcc_slice_activate - Activate the llcc slice 344 * @desc: Pointer to llcc slice descriptor 345 * 346 * A value of zero will be returned on success and a negative errno will 347 * be returned in error cases 348 */ 349 int llcc_slice_activate(struct llcc_slice_desc *desc) 350 { 351 int ret; 352 u32 act_ctrl_val; 353 354 if (IS_ERR(drv_data)) 355 return PTR_ERR(drv_data); 356 357 if (IS_ERR_OR_NULL(desc)) 358 return -EINVAL; 359 360 mutex_lock(&drv_data->lock); 361 if (test_bit(desc->slice_id, drv_data->bitmap)) { 362 mutex_unlock(&drv_data->lock); 363 return 0; 364 } 365 366 act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT; 367 368 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 369 DEACTIVATE); 370 if (ret) { 371 mutex_unlock(&drv_data->lock); 372 return ret; 373 } 374 375 __set_bit(desc->slice_id, drv_data->bitmap); 376 mutex_unlock(&drv_data->lock); 377 378 return ret; 379 } 380 EXPORT_SYMBOL_GPL(llcc_slice_activate); 381 382 /** 383 * llcc_slice_deactivate - Deactivate the llcc slice 384 * @desc: Pointer to llcc slice descriptor 385 * 386 * A value of zero will be returned on success and a negative errno will 387 * be returned in error cases 388 */ 389 int llcc_slice_deactivate(struct llcc_slice_desc *desc) 390 { 391 u32 act_ctrl_val; 392 int ret; 393 394 if (IS_ERR(drv_data)) 395 return PTR_ERR(drv_data); 396 397 if (IS_ERR_OR_NULL(desc)) 398 return -EINVAL; 399 400 mutex_lock(&drv_data->lock); 401 if (!test_bit(desc->slice_id, drv_data->bitmap)) { 402 mutex_unlock(&drv_data->lock); 403 return 0; 404 } 405 act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT; 406 407 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 408 ACTIVATE); 409 if (ret) { 410 mutex_unlock(&drv_data->lock); 411 return ret; 412 } 413 414 __clear_bit(desc->slice_id, drv_data->bitmap); 415 mutex_unlock(&drv_data->lock); 416 417 return ret; 418 } 419 EXPORT_SYMBOL_GPL(llcc_slice_deactivate); 420 421 /** 422 * llcc_get_slice_id - return the slice id 423 * @desc: Pointer to llcc slice descriptor 424 */ 425 int llcc_get_slice_id(struct llcc_slice_desc *desc) 426 { 427 if (IS_ERR_OR_NULL(desc)) 428 return -EINVAL; 429 430 return desc->slice_id; 431 } 432 EXPORT_SYMBOL_GPL(llcc_get_slice_id); 433 434 /** 435 * llcc_get_slice_size - return the slice id 436 * @desc: Pointer to llcc slice descriptor 437 */ 438 size_t llcc_get_slice_size(struct llcc_slice_desc *desc) 439 { 440 if (IS_ERR_OR_NULL(desc)) 441 return 0; 442 443 return desc->slice_size; 444 } 445 EXPORT_SYMBOL_GPL(llcc_get_slice_size); 446 447 static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, 448 const struct qcom_llcc_config *cfg) 449 { 450 int ret; 451 u32 attr1_cfg; 452 u32 attr0_cfg; 453 u32 attr1_val; 454 u32 attr0_val; 455 u32 max_cap_cacheline; 456 struct llcc_slice_desc desc; 457 458 attr1_val = config->cache_mode; 459 attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT; 460 attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT; 461 attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT; 462 463 max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap); 464 465 /* 466 * LLCC instances can vary for each target. 467 * The SW writes to broadcast register which gets propagated 468 * to each llcc instance (llcc0,.. llccN). 469 * Since the size of the memory is divided equally amongst the 470 * llcc instances, we need to configure the max cap accordingly. 471 */ 472 max_cap_cacheline = max_cap_cacheline / drv_data->num_banks; 473 max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT; 474 attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; 475 476 attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id); 477 478 ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val); 479 if (ret) 480 return ret; 481 482 attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK; 483 attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT; 484 485 attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id); 486 487 ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val); 488 if (ret) 489 return ret; 490 491 if (cfg->need_llcc_cfg) { 492 u32 disable_cap_alloc, retain_pc; 493 494 disable_cap_alloc = config->dis_cap_alloc << config->slice_id; 495 ret = regmap_write(drv_data->bcast_regmap, 496 LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc); 497 if (ret) 498 return ret; 499 500 retain_pc = config->retain_on_pc << config->slice_id; 501 ret = regmap_write(drv_data->bcast_regmap, 502 LLCC_TRP_PCB_ACT, retain_pc); 503 if (ret) 504 return ret; 505 } 506 507 if (drv_data->major_version == 2) { 508 u32 wren; 509 510 wren = config->write_scid_en << config->slice_id; 511 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN, 512 BIT(config->slice_id), wren); 513 if (ret) 514 return ret; 515 } 516 517 if (config->activate_on_init) { 518 desc.slice_id = config->slice_id; 519 ret = llcc_slice_activate(&desc); 520 } 521 522 return ret; 523 } 524 525 static int qcom_llcc_cfg_program(struct platform_device *pdev, 526 const struct qcom_llcc_config *cfg) 527 { 528 int i; 529 u32 sz; 530 int ret = 0; 531 const struct llcc_slice_config *llcc_table; 532 533 sz = drv_data->cfg_size; 534 llcc_table = drv_data->cfg; 535 536 for (i = 0; i < sz; i++) { 537 ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg); 538 if (ret) 539 return ret; 540 } 541 542 return ret; 543 } 544 545 static int qcom_llcc_remove(struct platform_device *pdev) 546 { 547 /* Set the global pointer to a error code to avoid referencing it */ 548 drv_data = ERR_PTR(-ENODEV); 549 return 0; 550 } 551 552 static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, 553 const char *name) 554 { 555 void __iomem *base; 556 struct regmap_config llcc_regmap_config = { 557 .reg_bits = 32, 558 .reg_stride = 4, 559 .val_bits = 32, 560 .fast_io = true, 561 }; 562 563 base = devm_platform_ioremap_resource_byname(pdev, name); 564 if (IS_ERR(base)) 565 return ERR_CAST(base); 566 567 llcc_regmap_config.name = name; 568 return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config); 569 } 570 571 static int qcom_llcc_probe(struct platform_device *pdev) 572 { 573 u32 num_banks; 574 struct device *dev = &pdev->dev; 575 int ret, i; 576 struct platform_device *llcc_edac; 577 const struct qcom_llcc_config *cfg; 578 const struct llcc_slice_config *llcc_cfg; 579 u32 sz; 580 u32 version; 581 582 drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); 583 if (!drv_data) { 584 ret = -ENOMEM; 585 goto err; 586 } 587 588 drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base"); 589 if (IS_ERR(drv_data->regmap)) { 590 ret = PTR_ERR(drv_data->regmap); 591 goto err; 592 } 593 594 drv_data->bcast_regmap = 595 qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); 596 if (IS_ERR(drv_data->bcast_regmap)) { 597 ret = PTR_ERR(drv_data->bcast_regmap); 598 goto err; 599 } 600 601 /* Extract major version of the IP */ 602 ret = regmap_read(drv_data->bcast_regmap, LLCC_COMMON_HW_INFO, &version); 603 if (ret) 604 goto err; 605 606 drv_data->major_version = FIELD_GET(LLCC_MAJOR_VERSION_MASK, version); 607 608 ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0, 609 &num_banks); 610 if (ret) 611 goto err; 612 613 num_banks &= LLCC_LB_CNT_MASK; 614 num_banks >>= LLCC_LB_CNT_SHIFT; 615 drv_data->num_banks = num_banks; 616 617 cfg = of_device_get_match_data(&pdev->dev); 618 llcc_cfg = cfg->sct_data; 619 sz = cfg->size; 620 621 for (i = 0; i < sz; i++) 622 if (llcc_cfg[i].slice_id > drv_data->max_slices) 623 drv_data->max_slices = llcc_cfg[i].slice_id; 624 625 drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), 626 GFP_KERNEL); 627 if (!drv_data->offsets) { 628 ret = -ENOMEM; 629 goto err; 630 } 631 632 for (i = 0; i < num_banks; i++) 633 drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; 634 635 drv_data->bitmap = devm_kcalloc(dev, 636 BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long), 637 GFP_KERNEL); 638 if (!drv_data->bitmap) { 639 ret = -ENOMEM; 640 goto err; 641 } 642 643 drv_data->cfg = llcc_cfg; 644 drv_data->cfg_size = sz; 645 mutex_init(&drv_data->lock); 646 platform_set_drvdata(pdev, drv_data); 647 648 ret = qcom_llcc_cfg_program(pdev, cfg); 649 if (ret) 650 goto err; 651 652 drv_data->ecc_irq = platform_get_irq(pdev, 0); 653 if (drv_data->ecc_irq >= 0) { 654 llcc_edac = platform_device_register_data(&pdev->dev, 655 "qcom_llcc_edac", -1, drv_data, 656 sizeof(*drv_data)); 657 if (IS_ERR(llcc_edac)) 658 dev_err(dev, "Failed to register llcc edac driver\n"); 659 } 660 661 return 0; 662 err: 663 drv_data = ERR_PTR(-ENODEV); 664 return ret; 665 } 666 667 static const struct of_device_id qcom_llcc_of_match[] = { 668 { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, 669 { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg }, 670 { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, 671 { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg }, 672 { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, 673 { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, 674 { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg }, 675 { } 676 }; 677 678 static struct platform_driver qcom_llcc_driver = { 679 .driver = { 680 .name = "qcom-llcc", 681 .of_match_table = qcom_llcc_of_match, 682 }, 683 .probe = qcom_llcc_probe, 684 .remove = qcom_llcc_remove, 685 }; 686 module_platform_driver(qcom_llcc_driver); 687 688 MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller"); 689 MODULE_LICENSE("GPL v2"); 690