xref: /openbmc/linux/drivers/soc/qcom/llcc-qcom.c (revision d3402925)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4  *
5  */
6 
7 #include <linux/bitfield.h>
8 #include <linux/bitmap.h>
9 #include <linux/bitops.h>
10 #include <linux/device.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/mutex.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17 #include <linux/regmap.h>
18 #include <linux/sizes.h>
19 #include <linux/slab.h>
20 #include <linux/soc/qcom/llcc-qcom.h>
21 
22 #define ACTIVATE                      BIT(0)
23 #define DEACTIVATE                    BIT(1)
24 #define ACT_CLEAR                     BIT(0)
25 #define ACT_COMPLETE                  BIT(4)
26 #define ACT_CTRL_OPCODE_ACTIVATE      BIT(0)
27 #define ACT_CTRL_OPCODE_DEACTIVATE    BIT(1)
28 #define ACT_CTRL_ACT_TRIG             BIT(0)
29 #define ACT_CTRL_OPCODE_SHIFT         0x01
30 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02
31 #define ATTR1_FIXED_SIZE_SHIFT        0x03
32 #define ATTR1_PRIORITY_SHIFT          0x04
33 #define ATTR1_MAX_CAP_SHIFT           0x10
34 #define ATTR0_RES_WAYS_MASK           GENMASK(15, 0)
35 #define ATTR0_BONUS_WAYS_MASK         GENMASK(31, 16)
36 #define ATTR0_BONUS_WAYS_SHIFT        0x10
37 #define LLCC_STATUS_READ_DELAY        100
38 
39 #define CACHE_LINE_SIZE_SHIFT         6
40 
41 #define LLCC_LB_CNT_MASK              GENMASK(31, 28)
42 #define LLCC_LB_CNT_SHIFT             28
43 
44 #define MAX_CAP_TO_BYTES(n)           (n * SZ_1K)
45 #define LLCC_TRP_ACT_CTRLn(n)         (n * SZ_4K)
46 #define LLCC_TRP_ACT_CLEARn(n)        (8 + n * SZ_4K)
47 #define LLCC_TRP_STATUSn(n)           (4 + n * SZ_4K)
48 #define LLCC_TRP_ATTR0_CFGn(n)        (0x21000 + SZ_8 * n)
49 #define LLCC_TRP_ATTR1_CFGn(n)        (0x21004 + SZ_8 * n)
50 #define LLCC_TRP_ATTR2_CFGn(n)        (0x21100 + SZ_8 * n)
51 
52 #define LLCC_TRP_SCID_DIS_CAP_ALLOC   0x21f00
53 #define LLCC_TRP_PCB_ACT              0x21f04
54 #define LLCC_TRP_ALGO_CFG1	      0x21f0c
55 #define LLCC_TRP_ALGO_CFG2	      0x21f10
56 #define LLCC_TRP_ALGO_CFG3	      0x21f14
57 #define LLCC_TRP_ALGO_CFG4	      0x21f18
58 #define LLCC_TRP_ALGO_CFG5	      0x21f1c
59 #define LLCC_TRP_WRSC_EN              0x21f20
60 #define LLCC_TRP_ALGO_CFG6	      0x21f24
61 #define LLCC_TRP_ALGO_CFG7	      0x21f28
62 #define LLCC_TRP_WRSC_CACHEABLE_EN    0x21f2c
63 #define LLCC_TRP_ALGO_CFG8	      0x21f30
64 
65 #define BANK_OFFSET_STRIDE	      0x80000
66 
67 #define LLCC_VERSION_2_0_0_0          0x02000000
68 #define LLCC_VERSION_2_1_0_0          0x02010000
69 #define LLCC_VERSION_4_1_0_0          0x04010000
70 
71 /**
72  * struct llcc_slice_config - Data associated with the llcc slice
73  * @usecase_id: Unique id for the client's use case
74  * @slice_id: llcc slice id for each client
75  * @max_cap: The maximum capacity of the cache slice provided in KB
76  * @priority: Priority of the client used to select victim line for replacement
77  * @fixed_size: Boolean indicating if the slice has a fixed capacity
78  * @bonus_ways: Bonus ways are additional ways to be used for any slice,
79  *		if client ends up using more than reserved cache ways. Bonus
80  *		ways are allocated only if they are not reserved for some
81  *		other client.
82  * @res_ways: Reserved ways for the cache slice, the reserved ways cannot
83  *		be used by any other client than the one its assigned to.
84  * @cache_mode: Each slice operates as a cache, this controls the mode of the
85  *             slice: normal or TCM(Tightly Coupled Memory)
86  * @probe_target_ways: Determines what ways to probe for access hit. When
87  *                    configured to 1 only bonus and reserved ways are probed.
88  *                    When configured to 0 all ways in llcc are probed.
89  * @dis_cap_alloc: Disable capacity based allocation for a client
90  * @retain_on_pc: If this bit is set and client has maintained active vote
91  *               then the ways assigned to this client are not flushed on power
92  *               collapse.
93  * @activate_on_init: Activate the slice immediately after it is programmed
94  * @write_scid_en: Bit enables write cache support for a given scid.
95  * @write_scid_cacheable_en: Enables write cache cacheable support for a
96  *			     given scid (not supported on v2 or older hardware).
97  */
98 struct llcc_slice_config {
99 	u32 usecase_id;
100 	u32 slice_id;
101 	u32 max_cap;
102 	u32 priority;
103 	bool fixed_size;
104 	u32 bonus_ways;
105 	u32 res_ways;
106 	u32 cache_mode;
107 	u32 probe_target_ways;
108 	bool dis_cap_alloc;
109 	bool retain_on_pc;
110 	bool activate_on_init;
111 	bool write_scid_en;
112 	bool write_scid_cacheable_en;
113 	bool stale_en;
114 	bool stale_cap_en;
115 	bool mru_uncap_en;
116 	bool mru_rollover;
117 	bool alloc_oneway_en;
118 	bool ovcap_en;
119 	bool ovcap_prio;
120 	bool vict_prio;
121 };
122 
123 struct qcom_llcc_config {
124 	const struct llcc_slice_config *sct_data;
125 	int size;
126 	bool need_llcc_cfg;
127 	const u32 *reg_offset;
128 	const struct llcc_edac_reg_offset *edac_reg_offset;
129 };
130 
131 enum llcc_reg_offset {
132 	LLCC_COMMON_HW_INFO,
133 	LLCC_COMMON_STATUS0,
134 };
135 
136 static const struct llcc_slice_config sc7180_data[] =  {
137 	{ LLCC_CPUSS,    1,  256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 },
138 	{ LLCC_MDM,      8,  128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
139 	{ LLCC_GPUHTW,   11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
140 	{ LLCC_GPU,      12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
141 };
142 
143 static const struct llcc_slice_config sc7280_data[] =  {
144 	{ LLCC_CPUSS,    1,  768, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 1, 0},
145 	{ LLCC_MDMHPGRW, 7,  512, 2, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
146 	{ LLCC_CMPT,     10, 768, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
147 	{ LLCC_GPUHTW,   11, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
148 	{ LLCC_GPU,      12, 512, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
149 	{ LLCC_MMUHWT,   13, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 0, 1, 0},
150 	{ LLCC_MDMPNG,   21, 768, 0, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
151 	{ LLCC_WLHW,     24, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
152 	{ LLCC_MODPE,    29, 64,  1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
153 };
154 
155 static const struct llcc_slice_config sc8180x_data[] = {
156 	{ LLCC_CPUSS,    1, 6144,  1, 1, 0xfff, 0x0,   0, 0, 0, 1, 1 },
157 	{ LLCC_VIDSC0,   2, 512,   2, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
158 	{ LLCC_VIDSC1,   3, 512,   2, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
159 	{ LLCC_AUDIO,    6, 1024,  1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
160 	{ LLCC_MDMHPGRW, 7, 3072,  1, 1, 0x3ff, 0xc00, 0, 0, 0, 1, 0 },
161 	{ LLCC_MDM,      8, 3072,  1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
162 	{ LLCC_MODHW,    9, 1024,  1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
163 	{ LLCC_CMPT,     10, 6144, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
164 	{ LLCC_GPUHTW,   11, 1024, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
165 	{ LLCC_GPU,      12, 5120, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
166 	{ LLCC_MMUHWT,   13, 1024, 1, 1, 0xfff, 0x0,   0, 0, 0, 0, 1 },
167 	{ LLCC_CMPTDMA,  15, 6144, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
168 	{ LLCC_DISP,     16, 6144, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
169 	{ LLCC_VIDFW,    17, 1024, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
170 	{ LLCC_MDMHPFX,  20, 1024, 2, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
171 	{ LLCC_MDMPNG,   21, 1024, 0, 1, 0xc,   0x0,   0, 0, 0, 1, 0 },
172 	{ LLCC_AUDHW,    22, 1024, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
173 	{ LLCC_NPU,      23, 6144, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
174 	{ LLCC_WLHW,     24, 6144, 1, 1, 0xfff, 0x0,   0, 0, 0, 1, 0 },
175 	{ LLCC_MODPE,    29, 512,  1, 1, 0xc,   0x0,   0, 0, 0, 1, 0 },
176 	{ LLCC_APTCM,    30, 512,  3, 1, 0x0,   0x1,   1, 0, 0, 1, 0 },
177 	{ LLCC_WRCACHE,  31, 128,  1, 1, 0xfff, 0x0,   0, 0, 0, 0, 0 },
178 };
179 
180 static const struct llcc_slice_config sc8280xp_data[] = {
181 	{ LLCC_CPUSS,    1,  6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 },
182 	{ LLCC_VIDSC0,   2,  512,  3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
183 	{ LLCC_AUDIO,    6,  1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
184 	{ LLCC_CMPT,     10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
185 	{ LLCC_GPUHTW,   11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
186 	{ LLCC_GPU,      12, 4096, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 },
187 	{ LLCC_MMUHWT,   13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
188 	{ LLCC_DISP,     16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
189 	{ LLCC_AUDHW,    22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
190 	{ LLCC_DRE,      26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
191 	{ LLCC_CVP,      28, 512,  3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
192 	{ LLCC_APTCM,    30, 1024, 3, 1, 0x0,   0x1, 1, 0, 0, 1, 0, 0 },
193 	{ LLCC_WRCACHE,  31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
194 	{ LLCC_CVPFW,    17, 512,  1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
195 	{ LLCC_CPUSS1,   3, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
196 	{ LLCC_CPUHWT,   5, 512,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
197 };
198 
199 static const struct llcc_slice_config sdm845_data[] =  {
200 	{ LLCC_CPUSS,    1,  2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 1 },
201 	{ LLCC_VIDSC0,   2,  512,  2, 1, 0x0,   0x0f0, 0, 0, 1, 1, 0 },
202 	{ LLCC_VIDSC1,   3,  512,  2, 1, 0x0,   0x0f0, 0, 0, 1, 1, 0 },
203 	{ LLCC_ROTATOR,  4,  563,  2, 1, 0x0,   0x00e, 2, 0, 1, 1, 0 },
204 	{ LLCC_VOICE,    5,  2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 0 },
205 	{ LLCC_AUDIO,    6,  2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 0 },
206 	{ LLCC_MDMHPGRW, 7,  1024, 2, 0, 0xfc,  0xf00, 0, 0, 1, 1, 0 },
207 	{ LLCC_MDM,      8,  2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 0 },
208 	{ LLCC_CMPT,     10, 2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 0 },
209 	{ LLCC_GPUHTW,   11, 512,  1, 1, 0xc,   0x0,   0, 0, 1, 1, 0 },
210 	{ LLCC_GPU,      12, 2304, 1, 0, 0xff0, 0x2,   0, 0, 1, 1, 0 },
211 	{ LLCC_MMUHWT,   13, 256,  2, 0, 0x0,   0x1,   0, 0, 1, 0, 1 },
212 	{ LLCC_CMPTDMA,  15, 2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 0 },
213 	{ LLCC_DISP,     16, 2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 0 },
214 	{ LLCC_VIDFW,    17, 2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 0 },
215 	{ LLCC_MDMHPFX,  20, 1024, 2, 1, 0x0,   0xf00, 0, 0, 1, 1, 0 },
216 	{ LLCC_MDMPNG,   21, 1024, 0, 1, 0x1e,  0x0,   0, 0, 1, 1, 0 },
217 	{ LLCC_AUDHW,    22, 1024, 1, 1, 0xffc, 0x2,   0, 0, 1, 1, 0 },
218 };
219 
220 static const struct llcc_slice_config sm6350_data[] =  {
221 	{ LLCC_CPUSS,    1,  768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1 },
222 	{ LLCC_MDM,      8,  512, 2, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
223 	{ LLCC_GPUHTW,   11, 256, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
224 	{ LLCC_GPU,      12, 512, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
225 	{ LLCC_MDMPNG,   21, 768, 0, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
226 	{ LLCC_NPU,      23, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
227 	{ LLCC_MODPE,    29,  64, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
228 };
229 
230 static const struct llcc_slice_config sm8150_data[] =  {
231 	{  LLCC_CPUSS,    1, 3072, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 1 },
232 	{  LLCC_VIDSC0,   2, 512,  2, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
233 	{  LLCC_VIDSC1,   3, 512,  2, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
234 	{  LLCC_AUDIO,    6, 1024, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
235 	{  LLCC_MDMHPGRW, 7, 3072, 1, 0, 0xFF,  0xF00, 0, 0, 0, 1, 0 },
236 	{  LLCC_MDM,      8, 3072, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
237 	{  LLCC_MODHW,    9, 1024, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
238 	{  LLCC_CMPT,    10, 3072, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
239 	{  LLCC_GPUHTW , 11, 512,  1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
240 	{  LLCC_GPU,     12, 2560, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
241 	{  LLCC_MMUHWT,  13, 1024, 1, 1, 0xFFF, 0x0,   0, 0, 0, 0, 1 },
242 	{  LLCC_CMPTDMA, 15, 3072, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
243 	{  LLCC_DISP,    16, 3072, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
244 	{  LLCC_MDMHPFX, 20, 1024, 2, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
245 	{  LLCC_MDMHPFX, 21, 1024, 0, 1, 0xF,   0x0,   0, 0, 0, 1, 0 },
246 	{  LLCC_AUDHW,   22, 1024, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
247 	{  LLCC_NPU,     23, 3072, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
248 	{  LLCC_WLHW,    24, 3072, 1, 1, 0xFFF, 0x0,   0, 0, 0, 1, 0 },
249 	{  LLCC_MODPE,   29, 256,  1, 1, 0xF,   0x0,   0, 0, 0, 1, 0 },
250 	{  LLCC_APTCM,   30, 256,  3, 1, 0x0,   0x1,   1, 0, 0, 1, 0 },
251 	{  LLCC_WRCACHE, 31, 128,  1, 1, 0xFFF, 0x0,   0, 0, 0, 0, 0 },
252 };
253 
254 static const struct llcc_slice_config sm8250_data[] =  {
255 	{ LLCC_CPUSS,    1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 },
256 	{ LLCC_VIDSC0,   2, 512,  3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
257 	{ LLCC_AUDIO,    6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
258 	{ LLCC_CMPT,    10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
259 	{ LLCC_GPUHTW,  11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
260 	{ LLCC_GPU,     12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 },
261 	{ LLCC_MMUHWT,  13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
262 	{ LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
263 	{ LLCC_DISP,    16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
264 	{ LLCC_VIDFW,   17, 512,  1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
265 	{ LLCC_AUDHW,   22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
266 	{ LLCC_NPU,     23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
267 	{ LLCC_WLHW,    24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
268 	{ LLCC_CVP,     28, 256,  3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
269 	{ LLCC_APTCM,   30, 128,  3, 0, 0x0,   0x3, 1, 0, 0, 1, 0, 0 },
270 	{ LLCC_WRCACHE, 31, 256,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
271 };
272 
273 static const struct llcc_slice_config sm8350_data[] =  {
274 	{ LLCC_CPUSS,    1, 3072,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 1 },
275 	{ LLCC_VIDSC0,   2, 512,   3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
276 	{ LLCC_AUDIO,    6, 1024,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
277 	{ LLCC_MDMHPGRW, 7, 1024,  3, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
278 	{ LLCC_MODHW,    9, 1024,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
279 	{ LLCC_CMPT,     10, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
280 	{ LLCC_GPUHTW,   11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
281 	{ LLCC_GPU,      12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 },
282 	{ LLCC_MMUHWT,   13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
283 	{ LLCC_DISP,     16, 3072, 2, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
284 	{ LLCC_MDMPNG,   21, 1024, 0, 1, 0xf,   0x0, 0, 0, 0, 0, 1, 0 },
285 	{ LLCC_AUDHW,    22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
286 	{ LLCC_CVP,      28, 512,  3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
287 	{ LLCC_MODPE,    29, 256,  1, 1, 0xf,   0x0, 0, 0, 0, 0, 1, 0 },
288 	{ LLCC_APTCM,    30, 1024, 3, 1, 0x0,   0x1, 1, 0, 0, 0, 1, 0 },
289 	{ LLCC_WRCACHE,  31, 512,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
290 	{ LLCC_CVPFW,    17, 512,  1, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
291 	{ LLCC_CPUSS1,   3, 1024,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
292 	{ LLCC_CPUHWT,   5, 512,   1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
293 };
294 
295 static const struct llcc_slice_config sm8450_data[] =  {
296 	{LLCC_CPUSS,     1, 3072, 1, 0, 0xFFFF, 0x0,   0, 0, 0, 1, 1, 0, 0 },
297 	{LLCC_VIDSC0,    2,  512, 3, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
298 	{LLCC_AUDIO,     6, 1024, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0 },
299 	{LLCC_MDMHPGRW,  7, 1024, 3, 0, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
300 	{LLCC_MODHW,     9, 1024, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
301 	{LLCC_CMPT,     10, 4096, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
302 	{LLCC_GPUHTW,   11,  512, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
303 	{LLCC_GPU,      12, 2048, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 1, 0 },
304 	{LLCC_MMUHWT,   13,  768, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 0, 1, 0, 0 },
305 	{LLCC_DISP,     16, 4096, 2, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
306 	{LLCC_MDMPNG,   21, 1024, 1, 1, 0xF000, 0x0,   0, 0, 0, 1, 0, 0, 0 },
307 	{LLCC_AUDHW,    22, 1024, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0 },
308 	{LLCC_CVP,      28,  256, 3, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
309 	{LLCC_MODPE,    29,   64, 1, 1, 0xF000, 0x0,   0, 0, 0, 1, 0, 0, 0 },
310 	{LLCC_APTCM,    30, 1024, 3, 1, 0x0,    0xF0,  1, 0, 0, 1, 0, 0, 0 },
311 	{LLCC_WRCACHE,  31,  512, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 0, 1, 0, 0 },
312 	{LLCC_CVPFW,    17,  512, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
313 	{LLCC_CPUSS1,    3, 1024, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
314 	{LLCC_CAMEXP0,   4,  256, 3, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
315 	{LLCC_CPUMTE,   23,  256, 1, 1, 0x0FFF, 0x0,   0, 0, 0, 0, 1, 0, 0 },
316 	{LLCC_CPUHWT,    5,  512, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 1, 0, 0 },
317 	{LLCC_CAMEXP1,  27,  256, 3, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },
318 	{LLCC_AENPU,     8, 2048, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0 },
319 };
320 
321 static const struct llcc_slice_config sm8550_data[] =  {
322 	{LLCC_CPUSS,     1, 5120, 1, 0, 0xFFFFFF, 0x0,   0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
323 	{LLCC_VIDSC0,    2,  512, 4, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
324 	{LLCC_AUDIO,     6, 1024, 1, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
325 	{LLCC_MDMHPGRW, 25, 1024, 4, 0, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
326 	{LLCC_MODHW,    26, 1024, 1, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
327 	{LLCC_CMPT,     10, 4096, 1, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
328 	{LLCC_GPUHTW,   11,  512, 1, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
329 	{LLCC_GPU,       9, 3096, 1, 0, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, },
330 	{LLCC_MMUHWT,   18,  768, 1, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
331 	{LLCC_DISP,     16, 6144, 1, 1, 0xFFFFFF, 0x0,   2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
332 	{LLCC_MDMPNG,   27, 1024, 0, 1, 0xF00000, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
333 	{LLCC_AUDHW,    22, 1024, 1, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
334 	{LLCC_CVP,       8,  256, 4, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
335 	{LLCC_MODPE,    29,   64, 1, 1, 0xF00000, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, },
336 	{LLCC_WRCACHE,  31,  512, 1, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
337 	{LLCC_CAMEXP0,   4,  256, 4, 1,      0xF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
338 	{LLCC_CPUHWT,    5,  512, 1, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
339 	{LLCC_CAMEXP1,   7, 3200, 3, 1, 0xFFFFF0, 0x0,   2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
340 	{LLCC_CMPTHCP,  17,  256, 4, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
341 	{LLCC_LCPDARE,  30,  128, 4, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, },
342 	{LLCC_AENPU,     3, 3072, 1, 1, 0xFE01FF, 0x0,   2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
343 	{LLCC_ISLAND1,  12, 1792, 7, 1,   0xFE00, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
344 	{LLCC_ISLAND4,  15,  256, 7, 1,  0x10000, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
345 	{LLCC_CAMEXP2,  19, 3200, 3, 1, 0xFFFFF0, 0x0,   2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
346 	{LLCC_CAMEXP3,  20, 3200, 2, 1, 0xFFFFF0, 0x0,   2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
347 	{LLCC_CAMEXP4,  21, 3200, 2, 1, 0xFFFFF0, 0x0,   2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
348 	{LLCC_DISP_WB,  23, 1024, 4, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
349 	{LLCC_DISP_1,   24, 6144, 1, 1, 0xFFFFFF, 0x0,   2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
350 	{LLCC_VIDVSP,   28,  256, 4, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
351 };
352 
353 static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = {
354 	.trp_ecc_error_status0 = 0x20344,
355 	.trp_ecc_error_status1 = 0x20348,
356 	.trp_ecc_sb_err_syn0 = 0x2304c,
357 	.trp_ecc_db_err_syn0 = 0x20370,
358 	.trp_ecc_error_cntr_clear = 0x20440,
359 	.trp_interrupt_0_status = 0x20480,
360 	.trp_interrupt_0_clear = 0x20484,
361 	.trp_interrupt_0_enable = 0x20488,
362 
363 	/* LLCC Common registers */
364 	.cmn_status0 = 0x3000c,
365 	.cmn_interrupt_0_enable = 0x3001c,
366 	.cmn_interrupt_2_enable = 0x3003c,
367 
368 	/* LLCC DRP registers */
369 	.drp_ecc_error_cfg = 0x40000,
370 	.drp_ecc_error_cntr_clear = 0x40004,
371 	.drp_interrupt_status = 0x41000,
372 	.drp_interrupt_clear = 0x41008,
373 	.drp_interrupt_enable = 0x4100c,
374 	.drp_ecc_error_status0 = 0x42044,
375 	.drp_ecc_error_status1 = 0x42048,
376 	.drp_ecc_sb_err_syn0 = 0x4204c,
377 	.drp_ecc_db_err_syn0 = 0x42070,
378 };
379 
380 static const struct llcc_edac_reg_offset llcc_v2_1_edac_reg_offset = {
381 	.trp_ecc_error_status0 = 0x20344,
382 	.trp_ecc_error_status1 = 0x20348,
383 	.trp_ecc_sb_err_syn0 = 0x2034c,
384 	.trp_ecc_db_err_syn0 = 0x20370,
385 	.trp_ecc_error_cntr_clear = 0x20440,
386 	.trp_interrupt_0_status = 0x20480,
387 	.trp_interrupt_0_clear = 0x20484,
388 	.trp_interrupt_0_enable = 0x20488,
389 
390 	/* LLCC Common registers */
391 	.cmn_status0 = 0x3400c,
392 	.cmn_interrupt_0_enable = 0x3401c,
393 	.cmn_interrupt_2_enable = 0x3403c,
394 
395 	/* LLCC DRP registers */
396 	.drp_ecc_error_cfg = 0x50000,
397 	.drp_ecc_error_cntr_clear = 0x50004,
398 	.drp_interrupt_status = 0x50020,
399 	.drp_interrupt_clear = 0x50028,
400 	.drp_interrupt_enable = 0x5002c,
401 	.drp_ecc_error_status0 = 0x520f4,
402 	.drp_ecc_error_status1 = 0x520f8,
403 	.drp_ecc_sb_err_syn0 = 0x520fc,
404 	.drp_ecc_db_err_syn0 = 0x52120,
405 };
406 
407 /* LLCC register offset starting from v1.0.0 */
408 static const u32 llcc_v1_reg_offset[] = {
409 	[LLCC_COMMON_HW_INFO]	= 0x00030000,
410 	[LLCC_COMMON_STATUS0]	= 0x0003000c,
411 };
412 
413 /* LLCC register offset starting from v2.0.1 */
414 static const u32 llcc_v2_1_reg_offset[] = {
415 	[LLCC_COMMON_HW_INFO]	= 0x00034000,
416 	[LLCC_COMMON_STATUS0]	= 0x0003400c,
417 };
418 
419 static const struct qcom_llcc_config sc7180_cfg = {
420 	.sct_data	= sc7180_data,
421 	.size		= ARRAY_SIZE(sc7180_data),
422 	.need_llcc_cfg	= true,
423 	.reg_offset	= llcc_v1_reg_offset,
424 	.edac_reg_offset = &llcc_v1_edac_reg_offset,
425 };
426 
427 static const struct qcom_llcc_config sc7280_cfg = {
428 	.sct_data	= sc7280_data,
429 	.size		= ARRAY_SIZE(sc7280_data),
430 	.need_llcc_cfg	= true,
431 	.reg_offset	= llcc_v1_reg_offset,
432 	.edac_reg_offset = &llcc_v1_edac_reg_offset,
433 };
434 
435 static const struct qcom_llcc_config sc8180x_cfg = {
436 	.sct_data	= sc8180x_data,
437 	.size		= ARRAY_SIZE(sc8180x_data),
438 	.need_llcc_cfg	= true,
439 	.reg_offset	= llcc_v1_reg_offset,
440 	.edac_reg_offset = &llcc_v1_edac_reg_offset,
441 };
442 
443 static const struct qcom_llcc_config sc8280xp_cfg = {
444 	.sct_data	= sc8280xp_data,
445 	.size		= ARRAY_SIZE(sc8280xp_data),
446 	.need_llcc_cfg	= true,
447 	.reg_offset	= llcc_v1_reg_offset,
448 	.edac_reg_offset = &llcc_v1_edac_reg_offset,
449 };
450 
451 static const struct qcom_llcc_config sdm845_cfg = {
452 	.sct_data	= sdm845_data,
453 	.size		= ARRAY_SIZE(sdm845_data),
454 	.need_llcc_cfg	= false,
455 	.reg_offset	= llcc_v1_reg_offset,
456 	.edac_reg_offset = &llcc_v1_edac_reg_offset,
457 };
458 
459 static const struct qcom_llcc_config sm6350_cfg = {
460 	.sct_data	= sm6350_data,
461 	.size		= ARRAY_SIZE(sm6350_data),
462 	.need_llcc_cfg	= true,
463 	.reg_offset	= llcc_v1_reg_offset,
464 	.edac_reg_offset = &llcc_v1_edac_reg_offset,
465 };
466 
467 static const struct qcom_llcc_config sm8150_cfg = {
468 	.sct_data       = sm8150_data,
469 	.size           = ARRAY_SIZE(sm8150_data),
470 	.need_llcc_cfg	= true,
471 	.reg_offset	= llcc_v1_reg_offset,
472 	.edac_reg_offset = &llcc_v1_edac_reg_offset,
473 };
474 
475 static const struct qcom_llcc_config sm8250_cfg = {
476 	.sct_data       = sm8250_data,
477 	.size           = ARRAY_SIZE(sm8250_data),
478 	.need_llcc_cfg	= true,
479 	.reg_offset	= llcc_v1_reg_offset,
480 	.edac_reg_offset = &llcc_v1_edac_reg_offset,
481 };
482 
483 static const struct qcom_llcc_config sm8350_cfg = {
484 	.sct_data       = sm8350_data,
485 	.size           = ARRAY_SIZE(sm8350_data),
486 	.need_llcc_cfg	= true,
487 	.reg_offset	= llcc_v1_reg_offset,
488 	.edac_reg_offset = &llcc_v1_edac_reg_offset,
489 };
490 
491 static const struct qcom_llcc_config sm8450_cfg = {
492 	.sct_data       = sm8450_data,
493 	.size           = ARRAY_SIZE(sm8450_data),
494 	.need_llcc_cfg	= true,
495 	.reg_offset	= llcc_v2_1_reg_offset,
496 	.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
497 };
498 
499 static const struct qcom_llcc_config sm8550_cfg = {
500 	.sct_data       = sm8550_data,
501 	.size           = ARRAY_SIZE(sm8550_data),
502 	.need_llcc_cfg	= true,
503 	.reg_offset	= llcc_v2_1_reg_offset,
504 	.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
505 };
506 
507 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
508 
509 /**
510  * llcc_slice_getd - get llcc slice descriptor
511  * @uid: usecase_id for the client
512  *
513  * A pointer to llcc slice descriptor will be returned on success
514  * and error pointer is returned on failure
515  */
516 struct llcc_slice_desc *llcc_slice_getd(u32 uid)
517 {
518 	const struct llcc_slice_config *cfg;
519 	struct llcc_slice_desc *desc;
520 	u32 sz, count;
521 
522 	if (IS_ERR(drv_data))
523 		return ERR_CAST(drv_data);
524 
525 	cfg = drv_data->cfg;
526 	sz = drv_data->cfg_size;
527 
528 	for (count = 0; cfg && count < sz; count++, cfg++)
529 		if (cfg->usecase_id == uid)
530 			break;
531 
532 	if (count == sz || !cfg)
533 		return ERR_PTR(-ENODEV);
534 
535 	desc = kzalloc(sizeof(*desc), GFP_KERNEL);
536 	if (!desc)
537 		return ERR_PTR(-ENOMEM);
538 
539 	desc->slice_id = cfg->slice_id;
540 	desc->slice_size = cfg->max_cap;
541 
542 	return desc;
543 }
544 EXPORT_SYMBOL_GPL(llcc_slice_getd);
545 
546 /**
547  * llcc_slice_putd - llcc slice descritpor
548  * @desc: Pointer to llcc slice descriptor
549  */
550 void llcc_slice_putd(struct llcc_slice_desc *desc)
551 {
552 	if (!IS_ERR_OR_NULL(desc))
553 		kfree(desc);
554 }
555 EXPORT_SYMBOL_GPL(llcc_slice_putd);
556 
557 static int llcc_update_act_ctrl(u32 sid,
558 				u32 act_ctrl_reg_val, u32 status)
559 {
560 	u32 act_ctrl_reg;
561 	u32 act_clear_reg;
562 	u32 status_reg;
563 	u32 slice_status;
564 	int ret;
565 
566 	if (IS_ERR(drv_data))
567 		return PTR_ERR(drv_data);
568 
569 	act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid);
570 	act_clear_reg = LLCC_TRP_ACT_CLEARn(sid);
571 	status_reg = LLCC_TRP_STATUSn(sid);
572 
573 	/* Set the ACTIVE trigger */
574 	act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG;
575 	ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
576 				act_ctrl_reg_val);
577 	if (ret)
578 		return ret;
579 
580 	/* Clear the ACTIVE trigger */
581 	act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG;
582 	ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
583 				act_ctrl_reg_val);
584 	if (ret)
585 		return ret;
586 
587 	if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
588 		ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
589 				      slice_status, (slice_status & ACT_COMPLETE),
590 				      0, LLCC_STATUS_READ_DELAY);
591 		if (ret)
592 			return ret;
593 	}
594 
595 	ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
596 				      slice_status, !(slice_status & status),
597 				      0, LLCC_STATUS_READ_DELAY);
598 
599 	if (drv_data->version >= LLCC_VERSION_4_1_0_0)
600 		ret = regmap_write(drv_data->bcast_regmap, act_clear_reg,
601 					ACT_CLEAR);
602 
603 	return ret;
604 }
605 
606 /**
607  * llcc_slice_activate - Activate the llcc slice
608  * @desc: Pointer to llcc slice descriptor
609  *
610  * A value of zero will be returned on success and a negative errno will
611  * be returned in error cases
612  */
613 int llcc_slice_activate(struct llcc_slice_desc *desc)
614 {
615 	int ret;
616 	u32 act_ctrl_val;
617 
618 	if (IS_ERR(drv_data))
619 		return PTR_ERR(drv_data);
620 
621 	if (IS_ERR_OR_NULL(desc))
622 		return -EINVAL;
623 
624 	mutex_lock(&drv_data->lock);
625 	if (test_bit(desc->slice_id, drv_data->bitmap)) {
626 		mutex_unlock(&drv_data->lock);
627 		return 0;
628 	}
629 
630 	act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT;
631 
632 	ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
633 				  DEACTIVATE);
634 	if (ret) {
635 		mutex_unlock(&drv_data->lock);
636 		return ret;
637 	}
638 
639 	__set_bit(desc->slice_id, drv_data->bitmap);
640 	mutex_unlock(&drv_data->lock);
641 
642 	return ret;
643 }
644 EXPORT_SYMBOL_GPL(llcc_slice_activate);
645 
646 /**
647  * llcc_slice_deactivate - Deactivate the llcc slice
648  * @desc: Pointer to llcc slice descriptor
649  *
650  * A value of zero will be returned on success and a negative errno will
651  * be returned in error cases
652  */
653 int llcc_slice_deactivate(struct llcc_slice_desc *desc)
654 {
655 	u32 act_ctrl_val;
656 	int ret;
657 
658 	if (IS_ERR(drv_data))
659 		return PTR_ERR(drv_data);
660 
661 	if (IS_ERR_OR_NULL(desc))
662 		return -EINVAL;
663 
664 	mutex_lock(&drv_data->lock);
665 	if (!test_bit(desc->slice_id, drv_data->bitmap)) {
666 		mutex_unlock(&drv_data->lock);
667 		return 0;
668 	}
669 	act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT;
670 
671 	ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
672 				  ACTIVATE);
673 	if (ret) {
674 		mutex_unlock(&drv_data->lock);
675 		return ret;
676 	}
677 
678 	__clear_bit(desc->slice_id, drv_data->bitmap);
679 	mutex_unlock(&drv_data->lock);
680 
681 	return ret;
682 }
683 EXPORT_SYMBOL_GPL(llcc_slice_deactivate);
684 
685 /**
686  * llcc_get_slice_id - return the slice id
687  * @desc: Pointer to llcc slice descriptor
688  */
689 int llcc_get_slice_id(struct llcc_slice_desc *desc)
690 {
691 	if (IS_ERR_OR_NULL(desc))
692 		return -EINVAL;
693 
694 	return desc->slice_id;
695 }
696 EXPORT_SYMBOL_GPL(llcc_get_slice_id);
697 
698 /**
699  * llcc_get_slice_size - return the slice id
700  * @desc: Pointer to llcc slice descriptor
701  */
702 size_t llcc_get_slice_size(struct llcc_slice_desc *desc)
703 {
704 	if (IS_ERR_OR_NULL(desc))
705 		return 0;
706 
707 	return desc->slice_size;
708 }
709 EXPORT_SYMBOL_GPL(llcc_get_slice_size);
710 
711 static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
712 				  const struct qcom_llcc_config *cfg)
713 {
714 	int ret;
715 	u32 attr2_cfg;
716 	u32 attr1_cfg;
717 	u32 attr0_cfg;
718 	u32 attr2_val;
719 	u32 attr1_val;
720 	u32 attr0_val;
721 	u32 max_cap_cacheline;
722 	struct llcc_slice_desc desc;
723 
724 	attr1_val = config->cache_mode;
725 	attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT;
726 	attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT;
727 	attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT;
728 
729 	max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap);
730 
731 	/*
732 	 * LLCC instances can vary for each target.
733 	 * The SW writes to broadcast register which gets propagated
734 	 * to each llcc instance (llcc0,.. llccN).
735 	 * Since the size of the memory is divided equally amongst the
736 	 * llcc instances, we need to configure the max cap accordingly.
737 	 */
738 	max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
739 	max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
740 	attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
741 
742 	attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id);
743 
744 	ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val);
745 	if (ret)
746 		return ret;
747 
748 	if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
749 		attr2_cfg = LLCC_TRP_ATTR2_CFGn(config->slice_id);
750 		attr0_val = config->res_ways;
751 		attr2_val = config->bonus_ways;
752 	} else {
753 		attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK;
754 		attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
755 	}
756 
757 	attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id);
758 
759 	ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val);
760 	if (ret)
761 		return ret;
762 
763 	if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
764 		ret = regmap_write(drv_data->bcast_regmap, attr2_cfg, attr2_val);
765 		if (ret)
766 			return ret;
767 	}
768 
769 	if (cfg->need_llcc_cfg) {
770 		u32 disable_cap_alloc, retain_pc;
771 
772 		disable_cap_alloc = config->dis_cap_alloc << config->slice_id;
773 		ret = regmap_write(drv_data->bcast_regmap,
774 				LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc);
775 		if (ret)
776 			return ret;
777 
778 		if (drv_data->version < LLCC_VERSION_4_1_0_0) {
779 			retain_pc = config->retain_on_pc << config->slice_id;
780 			ret = regmap_write(drv_data->bcast_regmap,
781 					LLCC_TRP_PCB_ACT, retain_pc);
782 			if (ret)
783 				return ret;
784 		}
785 	}
786 
787 	if (drv_data->version >= LLCC_VERSION_2_0_0_0) {
788 		u32 wren;
789 
790 		wren = config->write_scid_en << config->slice_id;
791 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN,
792 					 BIT(config->slice_id), wren);
793 		if (ret)
794 			return ret;
795 	}
796 
797 	if (drv_data->version >= LLCC_VERSION_2_1_0_0) {
798 		u32 wr_cache_en;
799 
800 		wr_cache_en = config->write_scid_cacheable_en << config->slice_id;
801 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_CACHEABLE_EN,
802 					 BIT(config->slice_id), wr_cache_en);
803 		if (ret)
804 			return ret;
805 	}
806 
807 	if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
808 		u32 stale_en;
809 		u32 stale_cap_en;
810 		u32 mru_uncap_en;
811 		u32 mru_rollover;
812 		u32 alloc_oneway_en;
813 		u32 ovcap_en;
814 		u32 ovcap_prio;
815 		u32 vict_prio;
816 
817 		stale_en = config->stale_en << config->slice_id;
818 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG1,
819 					 BIT(config->slice_id), stale_en);
820 		if (ret)
821 			return ret;
822 
823 		stale_cap_en = config->stale_cap_en << config->slice_id;
824 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG2,
825 					 BIT(config->slice_id), stale_cap_en);
826 		if (ret)
827 			return ret;
828 
829 		mru_uncap_en = config->mru_uncap_en << config->slice_id;
830 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG3,
831 					 BIT(config->slice_id), mru_uncap_en);
832 		if (ret)
833 			return ret;
834 
835 		mru_rollover = config->mru_rollover << config->slice_id;
836 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG4,
837 					 BIT(config->slice_id), mru_rollover);
838 		if (ret)
839 			return ret;
840 
841 		alloc_oneway_en = config->alloc_oneway_en << config->slice_id;
842 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG5,
843 					 BIT(config->slice_id), alloc_oneway_en);
844 		if (ret)
845 			return ret;
846 
847 		ovcap_en = config->ovcap_en << config->slice_id;
848 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG6,
849 					 BIT(config->slice_id), ovcap_en);
850 		if (ret)
851 			return ret;
852 
853 		ovcap_prio = config->ovcap_prio << config->slice_id;
854 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG7,
855 					 BIT(config->slice_id), ovcap_prio);
856 		if (ret)
857 			return ret;
858 
859 		vict_prio = config->vict_prio << config->slice_id;
860 		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG8,
861 					 BIT(config->slice_id), vict_prio);
862 		if (ret)
863 			return ret;
864 	}
865 
866 	if (config->activate_on_init) {
867 		desc.slice_id = config->slice_id;
868 		ret = llcc_slice_activate(&desc);
869 	}
870 
871 	return ret;
872 }
873 
874 static int qcom_llcc_cfg_program(struct platform_device *pdev,
875 				 const struct qcom_llcc_config *cfg)
876 {
877 	int i;
878 	u32 sz;
879 	int ret = 0;
880 	const struct llcc_slice_config *llcc_table;
881 
882 	sz = drv_data->cfg_size;
883 	llcc_table = drv_data->cfg;
884 
885 	for (i = 0; i < sz; i++) {
886 		ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg);
887 		if (ret)
888 			return ret;
889 	}
890 
891 	return ret;
892 }
893 
894 static int qcom_llcc_remove(struct platform_device *pdev)
895 {
896 	/* Set the global pointer to a error code to avoid referencing it */
897 	drv_data = ERR_PTR(-ENODEV);
898 	return 0;
899 }
900 
901 static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev,
902 		const char *name)
903 {
904 	void __iomem *base;
905 	struct regmap_config llcc_regmap_config = {
906 		.reg_bits = 32,
907 		.reg_stride = 4,
908 		.val_bits = 32,
909 		.fast_io = true,
910 	};
911 
912 	base = devm_platform_ioremap_resource_byname(pdev, name);
913 	if (IS_ERR(base))
914 		return ERR_CAST(base);
915 
916 	llcc_regmap_config.name = name;
917 	return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config);
918 }
919 
920 static int qcom_llcc_probe(struct platform_device *pdev)
921 {
922 	u32 num_banks;
923 	struct device *dev = &pdev->dev;
924 	int ret, i;
925 	struct platform_device *llcc_edac;
926 	const struct qcom_llcc_config *cfg;
927 	const struct llcc_slice_config *llcc_cfg;
928 	u32 sz;
929 	u32 version;
930 
931 	drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
932 	if (!drv_data) {
933 		ret = -ENOMEM;
934 		goto err;
935 	}
936 
937 	drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base");
938 	if (IS_ERR(drv_data->regmap)) {
939 		ret = PTR_ERR(drv_data->regmap);
940 		goto err;
941 	}
942 
943 	drv_data->bcast_regmap =
944 		qcom_llcc_init_mmio(pdev, "llcc_broadcast_base");
945 	if (IS_ERR(drv_data->bcast_regmap)) {
946 		ret = PTR_ERR(drv_data->bcast_regmap);
947 		goto err;
948 	}
949 
950 	cfg = of_device_get_match_data(&pdev->dev);
951 
952 	/* Extract version of the IP */
953 	ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO],
954 			  &version);
955 	if (ret)
956 		goto err;
957 
958 	drv_data->version = version;
959 
960 	ret = regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0],
961 			  &num_banks);
962 	if (ret)
963 		goto err;
964 
965 	num_banks &= LLCC_LB_CNT_MASK;
966 	num_banks >>= LLCC_LB_CNT_SHIFT;
967 	drv_data->num_banks = num_banks;
968 
969 	llcc_cfg = cfg->sct_data;
970 	sz = cfg->size;
971 
972 	for (i = 0; i < sz; i++)
973 		if (llcc_cfg[i].slice_id > drv_data->max_slices)
974 			drv_data->max_slices = llcc_cfg[i].slice_id;
975 
976 	drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32),
977 							GFP_KERNEL);
978 	if (!drv_data->offsets) {
979 		ret = -ENOMEM;
980 		goto err;
981 	}
982 
983 	for (i = 0; i < num_banks; i++)
984 		drv_data->offsets[i] = i * BANK_OFFSET_STRIDE;
985 
986 	drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices,
987 					      GFP_KERNEL);
988 	if (!drv_data->bitmap) {
989 		ret = -ENOMEM;
990 		goto err;
991 	}
992 
993 	drv_data->cfg = llcc_cfg;
994 	drv_data->cfg_size = sz;
995 	drv_data->edac_reg_offset = cfg->edac_reg_offset;
996 	mutex_init(&drv_data->lock);
997 	platform_set_drvdata(pdev, drv_data);
998 
999 	ret = qcom_llcc_cfg_program(pdev, cfg);
1000 	if (ret)
1001 		goto err;
1002 
1003 	drv_data->ecc_irq = platform_get_irq_optional(pdev, 0);
1004 	if (drv_data->ecc_irq >= 0) {
1005 		llcc_edac = platform_device_register_data(&pdev->dev,
1006 						"qcom_llcc_edac", -1, drv_data,
1007 						sizeof(*drv_data));
1008 		if (IS_ERR(llcc_edac))
1009 			dev_err(dev, "Failed to register llcc edac driver\n");
1010 	}
1011 
1012 	return 0;
1013 err:
1014 	drv_data = ERR_PTR(-ENODEV);
1015 	return ret;
1016 }
1017 
1018 static const struct of_device_id qcom_llcc_of_match[] = {
1019 	{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
1020 	{ .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg },
1021 	{ .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg },
1022 	{ .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg },
1023 	{ .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
1024 	{ .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg },
1025 	{ .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },
1026 	{ .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg },
1027 	{ .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg },
1028 	{ .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg },
1029 	{ .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfg },
1030 	{ }
1031 };
1032 MODULE_DEVICE_TABLE(of, qcom_llcc_of_match);
1033 
1034 static struct platform_driver qcom_llcc_driver = {
1035 	.driver = {
1036 		.name = "qcom-llcc",
1037 		.of_match_table = qcom_llcc_of_match,
1038 	},
1039 	.probe = qcom_llcc_probe,
1040 	.remove = qcom_llcc_remove,
1041 };
1042 module_platform_driver(qcom_llcc_driver);
1043 
1044 MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller");
1045 MODULE_LICENSE("GPL v2");
1046