1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bitmap.h> 9 #include <linux/bitops.h> 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/regmap.h> 18 #include <linux/sizes.h> 19 #include <linux/slab.h> 20 #include <linux/soc/qcom/llcc-qcom.h> 21 22 #define ACTIVATE BIT(0) 23 #define DEACTIVATE BIT(1) 24 #define ACT_CTRL_OPCODE_ACTIVATE BIT(0) 25 #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1) 26 #define ACT_CTRL_ACT_TRIG BIT(0) 27 #define ACT_CTRL_OPCODE_SHIFT 0x01 28 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02 29 #define ATTR1_FIXED_SIZE_SHIFT 0x03 30 #define ATTR1_PRIORITY_SHIFT 0x04 31 #define ATTR1_MAX_CAP_SHIFT 0x10 32 #define ATTR0_RES_WAYS_MASK GENMASK(15, 0) 33 #define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16) 34 #define ATTR0_BONUS_WAYS_SHIFT 0x10 35 #define LLCC_STATUS_READ_DELAY 100 36 37 #define CACHE_LINE_SIZE_SHIFT 6 38 39 #define LLCC_LB_CNT_MASK GENMASK(31, 28) 40 #define LLCC_LB_CNT_SHIFT 28 41 42 #define MAX_CAP_TO_BYTES(n) (n * SZ_1K) 43 #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K) 44 #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K) 45 #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) 46 #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) 47 48 #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 49 #define LLCC_TRP_PCB_ACT 0x21f04 50 #define LLCC_TRP_WRSC_EN 0x21f20 51 #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c 52 53 #define BANK_OFFSET_STRIDE 0x80000 54 55 #define LLCC_VERSION_2_0_0_0 0x02000000 56 #define LLCC_VERSION_2_1_0_0 0x02010000 57 58 /** 59 * struct llcc_slice_config - Data associated with the llcc slice 60 * @usecase_id: Unique id for the client's use case 61 * @slice_id: llcc slice id for each client 62 * @max_cap: The maximum capacity of the cache slice provided in KB 63 * @priority: Priority of the client used to select victim line for replacement 64 * @fixed_size: Boolean indicating if the slice has a fixed capacity 65 * @bonus_ways: Bonus ways are additional ways to be used for any slice, 66 * if client ends up using more than reserved cache ways. Bonus 67 * ways are allocated only if they are not reserved for some 68 * other client. 69 * @res_ways: Reserved ways for the cache slice, the reserved ways cannot 70 * be used by any other client than the one its assigned to. 71 * @cache_mode: Each slice operates as a cache, this controls the mode of the 72 * slice: normal or TCM(Tightly Coupled Memory) 73 * @probe_target_ways: Determines what ways to probe for access hit. When 74 * configured to 1 only bonus and reserved ways are probed. 75 * When configured to 0 all ways in llcc are probed. 76 * @dis_cap_alloc: Disable capacity based allocation for a client 77 * @retain_on_pc: If this bit is set and client has maintained active vote 78 * then the ways assigned to this client are not flushed on power 79 * collapse. 80 * @activate_on_init: Activate the slice immediately after it is programmed 81 * @write_scid_en: Bit enables write cache support for a given scid. 82 * @write_scid_cacheable_en: Enables write cache cacheable support for a 83 * given scid (not supported on v2 or older hardware). 84 */ 85 struct llcc_slice_config { 86 u32 usecase_id; 87 u32 slice_id; 88 u32 max_cap; 89 u32 priority; 90 bool fixed_size; 91 u32 bonus_ways; 92 u32 res_ways; 93 u32 cache_mode; 94 u32 probe_target_ways; 95 bool dis_cap_alloc; 96 bool retain_on_pc; 97 bool activate_on_init; 98 bool write_scid_en; 99 bool write_scid_cacheable_en; 100 }; 101 102 struct qcom_llcc_config { 103 const struct llcc_slice_config *sct_data; 104 int size; 105 bool need_llcc_cfg; 106 const u32 *reg_offset; 107 }; 108 109 enum llcc_reg_offset { 110 LLCC_COMMON_HW_INFO, 111 LLCC_COMMON_STATUS0, 112 }; 113 114 static const struct llcc_slice_config sc7180_data[] = { 115 { LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 }, 116 { LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 117 { LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 118 { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 119 }; 120 121 static const struct llcc_slice_config sc7280_data[] = { 122 { LLCC_CPUSS, 1, 768, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 1, 0}, 123 { LLCC_MDMHPGRW, 7, 512, 2, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 124 { LLCC_CMPT, 10, 768, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 125 { LLCC_GPUHTW, 11, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 126 { LLCC_GPU, 12, 512, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 127 { LLCC_MMUHWT, 13, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 0, 1, 0}, 128 { LLCC_MDMPNG, 21, 768, 0, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 129 { LLCC_WLHW, 24, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 130 { LLCC_MODPE, 29, 64, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 131 }; 132 133 static const struct llcc_slice_config sdm845_data[] = { 134 { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 }, 135 { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 136 { LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 137 { LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 }, 138 { LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 139 { LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 140 { LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 }, 141 { LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 142 { LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 143 { LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 }, 144 { LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 }, 145 { LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 }, 146 { LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 147 { LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 148 { LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 149 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 }, 150 { LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 }, 151 { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 152 }; 153 154 static const struct llcc_slice_config sm6350_data[] = { 155 { LLCC_CPUSS, 1, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1 }, 156 { LLCC_MDM, 8, 512, 2, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 157 { LLCC_GPUHTW, 11, 256, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 158 { LLCC_GPU, 12, 512, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 159 { LLCC_MDMPNG, 21, 768, 0, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 160 { LLCC_NPU, 23, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 161 { LLCC_MODPE, 29, 64, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 162 }; 163 164 static const struct llcc_slice_config sm8150_data[] = { 165 { LLCC_CPUSS, 1, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1 }, 166 { LLCC_VIDSC0, 2, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 167 { LLCC_VIDSC1, 3, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 168 { LLCC_AUDIO, 6, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 169 { LLCC_MDMHPGRW, 7, 3072, 1, 0, 0xFF, 0xF00, 0, 0, 0, 1, 0 }, 170 { LLCC_MDM, 8, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 171 { LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 172 { LLCC_CMPT, 10, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 173 { LLCC_GPUHTW , 11, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 174 { LLCC_GPU, 12, 2560, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 175 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1 }, 176 { LLCC_CMPTDMA, 15, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 177 { LLCC_DISP, 16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 178 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 179 { LLCC_MDMHPFX, 21, 1024, 0, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 180 { LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 181 { LLCC_NPU, 23, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 182 { LLCC_WLHW, 24, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 183 { LLCC_MODPE, 29, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 184 { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 }, 185 { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 }, 186 }; 187 188 static const struct llcc_slice_config sm8250_data[] = { 189 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, 190 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 191 { LLCC_AUDIO, 6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 192 { LLCC_CMPT, 10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 193 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 194 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, 195 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 196 { LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 197 { LLCC_DISP, 16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 198 { LLCC_VIDFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 199 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 200 { LLCC_NPU, 23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 201 { LLCC_WLHW, 24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 202 { LLCC_CVP, 28, 256, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 203 { LLCC_APTCM, 30, 128, 3, 0, 0x0, 0x3, 1, 0, 0, 1, 0, 0 }, 204 { LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 205 }; 206 207 static const struct llcc_slice_config sm8350_data[] = { 208 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 1 }, 209 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 210 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 211 { LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 212 { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 213 { LLCC_CMPT, 10, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 214 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 215 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, 216 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, 217 { LLCC_DISP, 16, 3072, 2, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 218 { LLCC_MDMPNG, 21, 1024, 0, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 }, 219 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 220 { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 221 { LLCC_MODPE, 29, 256, 1, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 }, 222 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 0, 1, 0 }, 223 { LLCC_WRCACHE, 31, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, 224 { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 225 { LLCC_CPUSS1, 3, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 226 { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, 227 }; 228 229 static const struct llcc_slice_config sm8450_data[] = { 230 {LLCC_CPUSS, 1, 3072, 1, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 }, 231 {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 232 {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, 233 {LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 234 {LLCC_MODHW, 9, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 235 {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 236 {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 237 {LLCC_GPU, 12, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 1, 0 }, 238 {LLCC_MMUHWT, 13, 768, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 239 {LLCC_DISP, 16, 4096, 2, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 240 {LLCC_MDMPNG, 21, 1024, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 241 {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, 242 {LLCC_CVP, 28, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 243 {LLCC_MODPE, 29, 64, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 244 {LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xF0, 1, 0, 0, 1, 0, 0, 0 }, 245 {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 246 {LLCC_CVPFW, 17, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 247 {LLCC_CPUSS1, 3, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 248 {LLCC_CAMEXP0, 4, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 249 {LLCC_CPUMTE, 23, 256, 1, 1, 0x0FFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 250 {LLCC_CPUHWT, 5, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 }, 251 {LLCC_CAMEXP1, 27, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 252 {LLCC_AENPU, 8, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, 253 }; 254 255 static const u32 llcc_v1_2_reg_offset[] = { 256 [LLCC_COMMON_HW_INFO] = 0x00030000, 257 [LLCC_COMMON_STATUS0] = 0x0003000c, 258 }; 259 260 static const u32 llcc_v21_reg_offset[] = { 261 [LLCC_COMMON_HW_INFO] = 0x00034000, 262 [LLCC_COMMON_STATUS0] = 0x0003400c, 263 }; 264 265 static const struct qcom_llcc_config sc7180_cfg = { 266 .sct_data = sc7180_data, 267 .size = ARRAY_SIZE(sc7180_data), 268 .need_llcc_cfg = true, 269 .reg_offset = llcc_v1_2_reg_offset, 270 }; 271 272 static const struct qcom_llcc_config sc7280_cfg = { 273 .sct_data = sc7280_data, 274 .size = ARRAY_SIZE(sc7280_data), 275 .need_llcc_cfg = true, 276 .reg_offset = llcc_v1_2_reg_offset, 277 }; 278 279 static const struct qcom_llcc_config sdm845_cfg = { 280 .sct_data = sdm845_data, 281 .size = ARRAY_SIZE(sdm845_data), 282 .need_llcc_cfg = false, 283 .reg_offset = llcc_v1_2_reg_offset, 284 }; 285 286 static const struct qcom_llcc_config sm6350_cfg = { 287 .sct_data = sm6350_data, 288 .size = ARRAY_SIZE(sm6350_data), 289 .need_llcc_cfg = true, 290 .reg_offset = llcc_v1_2_reg_offset, 291 }; 292 293 static const struct qcom_llcc_config sm8150_cfg = { 294 .sct_data = sm8150_data, 295 .size = ARRAY_SIZE(sm8150_data), 296 .need_llcc_cfg = true, 297 .reg_offset = llcc_v1_2_reg_offset, 298 }; 299 300 static const struct qcom_llcc_config sm8250_cfg = { 301 .sct_data = sm8250_data, 302 .size = ARRAY_SIZE(sm8250_data), 303 .need_llcc_cfg = true, 304 .reg_offset = llcc_v1_2_reg_offset, 305 }; 306 307 static const struct qcom_llcc_config sm8350_cfg = { 308 .sct_data = sm8350_data, 309 .size = ARRAY_SIZE(sm8350_data), 310 .need_llcc_cfg = true, 311 .reg_offset = llcc_v1_2_reg_offset, 312 }; 313 314 static const struct qcom_llcc_config sm8450_cfg = { 315 .sct_data = sm8450_data, 316 .size = ARRAY_SIZE(sm8450_data), 317 .need_llcc_cfg = true, 318 .reg_offset = llcc_v21_reg_offset, 319 }; 320 321 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; 322 323 /** 324 * llcc_slice_getd - get llcc slice descriptor 325 * @uid: usecase_id for the client 326 * 327 * A pointer to llcc slice descriptor will be returned on success and 328 * and error pointer is returned on failure 329 */ 330 struct llcc_slice_desc *llcc_slice_getd(u32 uid) 331 { 332 const struct llcc_slice_config *cfg; 333 struct llcc_slice_desc *desc; 334 u32 sz, count; 335 336 if (IS_ERR(drv_data)) 337 return ERR_CAST(drv_data); 338 339 cfg = drv_data->cfg; 340 sz = drv_data->cfg_size; 341 342 for (count = 0; cfg && count < sz; count++, cfg++) 343 if (cfg->usecase_id == uid) 344 break; 345 346 if (count == sz || !cfg) 347 return ERR_PTR(-ENODEV); 348 349 desc = kzalloc(sizeof(*desc), GFP_KERNEL); 350 if (!desc) 351 return ERR_PTR(-ENOMEM); 352 353 desc->slice_id = cfg->slice_id; 354 desc->slice_size = cfg->max_cap; 355 356 return desc; 357 } 358 EXPORT_SYMBOL_GPL(llcc_slice_getd); 359 360 /** 361 * llcc_slice_putd - llcc slice descritpor 362 * @desc: Pointer to llcc slice descriptor 363 */ 364 void llcc_slice_putd(struct llcc_slice_desc *desc) 365 { 366 if (!IS_ERR_OR_NULL(desc)) 367 kfree(desc); 368 } 369 EXPORT_SYMBOL_GPL(llcc_slice_putd); 370 371 static int llcc_update_act_ctrl(u32 sid, 372 u32 act_ctrl_reg_val, u32 status) 373 { 374 u32 act_ctrl_reg; 375 u32 status_reg; 376 u32 slice_status; 377 int ret; 378 379 if (IS_ERR(drv_data)) 380 return PTR_ERR(drv_data); 381 382 act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid); 383 status_reg = LLCC_TRP_STATUSn(sid); 384 385 /* Set the ACTIVE trigger */ 386 act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG; 387 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 388 act_ctrl_reg_val); 389 if (ret) 390 return ret; 391 392 /* Clear the ACTIVE trigger */ 393 act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG; 394 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 395 act_ctrl_reg_val); 396 if (ret) 397 return ret; 398 399 ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg, 400 slice_status, !(slice_status & status), 401 0, LLCC_STATUS_READ_DELAY); 402 return ret; 403 } 404 405 /** 406 * llcc_slice_activate - Activate the llcc slice 407 * @desc: Pointer to llcc slice descriptor 408 * 409 * A value of zero will be returned on success and a negative errno will 410 * be returned in error cases 411 */ 412 int llcc_slice_activate(struct llcc_slice_desc *desc) 413 { 414 int ret; 415 u32 act_ctrl_val; 416 417 if (IS_ERR(drv_data)) 418 return PTR_ERR(drv_data); 419 420 if (IS_ERR_OR_NULL(desc)) 421 return -EINVAL; 422 423 mutex_lock(&drv_data->lock); 424 if (test_bit(desc->slice_id, drv_data->bitmap)) { 425 mutex_unlock(&drv_data->lock); 426 return 0; 427 } 428 429 act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT; 430 431 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 432 DEACTIVATE); 433 if (ret) { 434 mutex_unlock(&drv_data->lock); 435 return ret; 436 } 437 438 __set_bit(desc->slice_id, drv_data->bitmap); 439 mutex_unlock(&drv_data->lock); 440 441 return ret; 442 } 443 EXPORT_SYMBOL_GPL(llcc_slice_activate); 444 445 /** 446 * llcc_slice_deactivate - Deactivate the llcc slice 447 * @desc: Pointer to llcc slice descriptor 448 * 449 * A value of zero will be returned on success and a negative errno will 450 * be returned in error cases 451 */ 452 int llcc_slice_deactivate(struct llcc_slice_desc *desc) 453 { 454 u32 act_ctrl_val; 455 int ret; 456 457 if (IS_ERR(drv_data)) 458 return PTR_ERR(drv_data); 459 460 if (IS_ERR_OR_NULL(desc)) 461 return -EINVAL; 462 463 mutex_lock(&drv_data->lock); 464 if (!test_bit(desc->slice_id, drv_data->bitmap)) { 465 mutex_unlock(&drv_data->lock); 466 return 0; 467 } 468 act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT; 469 470 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 471 ACTIVATE); 472 if (ret) { 473 mutex_unlock(&drv_data->lock); 474 return ret; 475 } 476 477 __clear_bit(desc->slice_id, drv_data->bitmap); 478 mutex_unlock(&drv_data->lock); 479 480 return ret; 481 } 482 EXPORT_SYMBOL_GPL(llcc_slice_deactivate); 483 484 /** 485 * llcc_get_slice_id - return the slice id 486 * @desc: Pointer to llcc slice descriptor 487 */ 488 int llcc_get_slice_id(struct llcc_slice_desc *desc) 489 { 490 if (IS_ERR_OR_NULL(desc)) 491 return -EINVAL; 492 493 return desc->slice_id; 494 } 495 EXPORT_SYMBOL_GPL(llcc_get_slice_id); 496 497 /** 498 * llcc_get_slice_size - return the slice id 499 * @desc: Pointer to llcc slice descriptor 500 */ 501 size_t llcc_get_slice_size(struct llcc_slice_desc *desc) 502 { 503 if (IS_ERR_OR_NULL(desc)) 504 return 0; 505 506 return desc->slice_size; 507 } 508 EXPORT_SYMBOL_GPL(llcc_get_slice_size); 509 510 static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, 511 const struct qcom_llcc_config *cfg) 512 { 513 int ret; 514 u32 attr1_cfg; 515 u32 attr0_cfg; 516 u32 attr1_val; 517 u32 attr0_val; 518 u32 max_cap_cacheline; 519 struct llcc_slice_desc desc; 520 521 attr1_val = config->cache_mode; 522 attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT; 523 attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT; 524 attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT; 525 526 max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap); 527 528 /* 529 * LLCC instances can vary for each target. 530 * The SW writes to broadcast register which gets propagated 531 * to each llcc instance (llcc0,.. llccN). 532 * Since the size of the memory is divided equally amongst the 533 * llcc instances, we need to configure the max cap accordingly. 534 */ 535 max_cap_cacheline = max_cap_cacheline / drv_data->num_banks; 536 max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT; 537 attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; 538 539 attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id); 540 541 ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val); 542 if (ret) 543 return ret; 544 545 attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK; 546 attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT; 547 548 attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id); 549 550 ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val); 551 if (ret) 552 return ret; 553 554 if (cfg->need_llcc_cfg) { 555 u32 disable_cap_alloc, retain_pc; 556 557 disable_cap_alloc = config->dis_cap_alloc << config->slice_id; 558 ret = regmap_write(drv_data->bcast_regmap, 559 LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc); 560 if (ret) 561 return ret; 562 563 retain_pc = config->retain_on_pc << config->slice_id; 564 ret = regmap_write(drv_data->bcast_regmap, 565 LLCC_TRP_PCB_ACT, retain_pc); 566 if (ret) 567 return ret; 568 } 569 570 if (drv_data->version >= LLCC_VERSION_2_0_0_0) { 571 u32 wren; 572 573 wren = config->write_scid_en << config->slice_id; 574 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN, 575 BIT(config->slice_id), wren); 576 if (ret) 577 return ret; 578 } 579 580 if (drv_data->version >= LLCC_VERSION_2_1_0_0) { 581 u32 wr_cache_en; 582 583 wr_cache_en = config->write_scid_cacheable_en << config->slice_id; 584 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_CACHEABLE_EN, 585 BIT(config->slice_id), wr_cache_en); 586 if (ret) 587 return ret; 588 } 589 590 if (config->activate_on_init) { 591 desc.slice_id = config->slice_id; 592 ret = llcc_slice_activate(&desc); 593 } 594 595 return ret; 596 } 597 598 static int qcom_llcc_cfg_program(struct platform_device *pdev, 599 const struct qcom_llcc_config *cfg) 600 { 601 int i; 602 u32 sz; 603 int ret = 0; 604 const struct llcc_slice_config *llcc_table; 605 606 sz = drv_data->cfg_size; 607 llcc_table = drv_data->cfg; 608 609 for (i = 0; i < sz; i++) { 610 ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg); 611 if (ret) 612 return ret; 613 } 614 615 return ret; 616 } 617 618 static int qcom_llcc_remove(struct platform_device *pdev) 619 { 620 /* Set the global pointer to a error code to avoid referencing it */ 621 drv_data = ERR_PTR(-ENODEV); 622 return 0; 623 } 624 625 static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, 626 const char *name) 627 { 628 void __iomem *base; 629 struct regmap_config llcc_regmap_config = { 630 .reg_bits = 32, 631 .reg_stride = 4, 632 .val_bits = 32, 633 .fast_io = true, 634 }; 635 636 base = devm_platform_ioremap_resource_byname(pdev, name); 637 if (IS_ERR(base)) 638 return ERR_CAST(base); 639 640 llcc_regmap_config.name = name; 641 return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config); 642 } 643 644 static int qcom_llcc_probe(struct platform_device *pdev) 645 { 646 u32 num_banks; 647 struct device *dev = &pdev->dev; 648 int ret, i; 649 struct platform_device *llcc_edac; 650 const struct qcom_llcc_config *cfg; 651 const struct llcc_slice_config *llcc_cfg; 652 u32 sz; 653 u32 version; 654 655 drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); 656 if (!drv_data) { 657 ret = -ENOMEM; 658 goto err; 659 } 660 661 drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base"); 662 if (IS_ERR(drv_data->regmap)) { 663 ret = PTR_ERR(drv_data->regmap); 664 goto err; 665 } 666 667 drv_data->bcast_regmap = 668 qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); 669 if (IS_ERR(drv_data->bcast_regmap)) { 670 ret = PTR_ERR(drv_data->bcast_regmap); 671 goto err; 672 } 673 674 cfg = of_device_get_match_data(&pdev->dev); 675 676 /* Extract version of the IP */ 677 ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO], 678 &version); 679 if (ret) 680 goto err; 681 682 drv_data->version = version; 683 684 ret = regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], 685 &num_banks); 686 if (ret) 687 goto err; 688 689 num_banks &= LLCC_LB_CNT_MASK; 690 num_banks >>= LLCC_LB_CNT_SHIFT; 691 drv_data->num_banks = num_banks; 692 693 llcc_cfg = cfg->sct_data; 694 sz = cfg->size; 695 696 for (i = 0; i < sz; i++) 697 if (llcc_cfg[i].slice_id > drv_data->max_slices) 698 drv_data->max_slices = llcc_cfg[i].slice_id; 699 700 drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), 701 GFP_KERNEL); 702 if (!drv_data->offsets) { 703 ret = -ENOMEM; 704 goto err; 705 } 706 707 for (i = 0; i < num_banks; i++) 708 drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; 709 710 drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices, 711 GFP_KERNEL); 712 if (!drv_data->bitmap) { 713 ret = -ENOMEM; 714 goto err; 715 } 716 717 drv_data->cfg = llcc_cfg; 718 drv_data->cfg_size = sz; 719 mutex_init(&drv_data->lock); 720 platform_set_drvdata(pdev, drv_data); 721 722 ret = qcom_llcc_cfg_program(pdev, cfg); 723 if (ret) 724 goto err; 725 726 drv_data->ecc_irq = platform_get_irq(pdev, 0); 727 if (drv_data->ecc_irq >= 0) { 728 llcc_edac = platform_device_register_data(&pdev->dev, 729 "qcom_llcc_edac", -1, drv_data, 730 sizeof(*drv_data)); 731 if (IS_ERR(llcc_edac)) 732 dev_err(dev, "Failed to register llcc edac driver\n"); 733 } 734 735 return 0; 736 err: 737 drv_data = ERR_PTR(-ENODEV); 738 return ret; 739 } 740 741 static const struct of_device_id qcom_llcc_of_match[] = { 742 { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, 743 { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg }, 744 { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, 745 { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg }, 746 { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, 747 { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, 748 { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg }, 749 { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg }, 750 { } 751 }; 752 753 static struct platform_driver qcom_llcc_driver = { 754 .driver = { 755 .name = "qcom-llcc", 756 .of_match_table = qcom_llcc_of_match, 757 }, 758 .probe = qcom_llcc_probe, 759 .remove = qcom_llcc_remove, 760 }; 761 module_platform_driver(qcom_llcc_driver); 762 763 MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller"); 764 MODULE_LICENSE("GPL v2"); 765