1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bitmap.h> 9 #include <linux/bitops.h> 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/regmap.h> 18 #include <linux/sizes.h> 19 #include <linux/slab.h> 20 #include <linux/soc/qcom/llcc-qcom.h> 21 22 #define ACTIVATE BIT(0) 23 #define DEACTIVATE BIT(1) 24 #define ACT_CTRL_OPCODE_ACTIVATE BIT(0) 25 #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1) 26 #define ACT_CTRL_ACT_TRIG BIT(0) 27 #define ACT_CTRL_OPCODE_SHIFT 0x01 28 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02 29 #define ATTR1_FIXED_SIZE_SHIFT 0x03 30 #define ATTR1_PRIORITY_SHIFT 0x04 31 #define ATTR1_MAX_CAP_SHIFT 0x10 32 #define ATTR0_RES_WAYS_MASK GENMASK(15, 0) 33 #define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16) 34 #define ATTR0_BONUS_WAYS_SHIFT 0x10 35 #define LLCC_STATUS_READ_DELAY 100 36 37 #define CACHE_LINE_SIZE_SHIFT 6 38 39 #define LLCC_LB_CNT_MASK GENMASK(31, 28) 40 #define LLCC_LB_CNT_SHIFT 28 41 42 #define MAX_CAP_TO_BYTES(n) (n * SZ_1K) 43 #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K) 44 #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K) 45 #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) 46 #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) 47 48 #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 49 #define LLCC_TRP_PCB_ACT 0x21f04 50 #define LLCC_TRP_WRSC_EN 0x21f20 51 #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c 52 53 #define BANK_OFFSET_STRIDE 0x80000 54 55 #define LLCC_VERSION_2_0_0_0 0x02000000 56 #define LLCC_VERSION_2_1_0_0 0x02010000 57 58 /** 59 * struct llcc_slice_config - Data associated with the llcc slice 60 * @usecase_id: Unique id for the client's use case 61 * @slice_id: llcc slice id for each client 62 * @max_cap: The maximum capacity of the cache slice provided in KB 63 * @priority: Priority of the client used to select victim line for replacement 64 * @fixed_size: Boolean indicating if the slice has a fixed capacity 65 * @bonus_ways: Bonus ways are additional ways to be used for any slice, 66 * if client ends up using more than reserved cache ways. Bonus 67 * ways are allocated only if they are not reserved for some 68 * other client. 69 * @res_ways: Reserved ways for the cache slice, the reserved ways cannot 70 * be used by any other client than the one its assigned to. 71 * @cache_mode: Each slice operates as a cache, this controls the mode of the 72 * slice: normal or TCM(Tightly Coupled Memory) 73 * @probe_target_ways: Determines what ways to probe for access hit. When 74 * configured to 1 only bonus and reserved ways are probed. 75 * When configured to 0 all ways in llcc are probed. 76 * @dis_cap_alloc: Disable capacity based allocation for a client 77 * @retain_on_pc: If this bit is set and client has maintained active vote 78 * then the ways assigned to this client are not flushed on power 79 * collapse. 80 * @activate_on_init: Activate the slice immediately after it is programmed 81 * @write_scid_en: Bit enables write cache support for a given scid. 82 * @write_scid_cacheable_en: Enables write cache cacheable support for a 83 * given scid (not supported on v2 or older hardware). 84 */ 85 struct llcc_slice_config { 86 u32 usecase_id; 87 u32 slice_id; 88 u32 max_cap; 89 u32 priority; 90 bool fixed_size; 91 u32 bonus_ways; 92 u32 res_ways; 93 u32 cache_mode; 94 u32 probe_target_ways; 95 bool dis_cap_alloc; 96 bool retain_on_pc; 97 bool activate_on_init; 98 bool write_scid_en; 99 bool write_scid_cacheable_en; 100 }; 101 102 struct qcom_llcc_config { 103 const struct llcc_slice_config *sct_data; 104 int size; 105 bool need_llcc_cfg; 106 const u32 *reg_offset; 107 }; 108 109 enum llcc_reg_offset { 110 LLCC_COMMON_HW_INFO, 111 LLCC_COMMON_STATUS0, 112 }; 113 114 static const struct llcc_slice_config sc7180_data[] = { 115 { LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 }, 116 { LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 117 { LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 118 { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 119 }; 120 121 static const struct llcc_slice_config sc7280_data[] = { 122 { LLCC_CPUSS, 1, 768, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 1, 0}, 123 { LLCC_MDMHPGRW, 7, 512, 2, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 124 { LLCC_CMPT, 10, 768, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 125 { LLCC_GPUHTW, 11, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 126 { LLCC_GPU, 12, 512, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 127 { LLCC_MMUHWT, 13, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 0, 1, 0}, 128 { LLCC_MDMPNG, 21, 768, 0, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 129 { LLCC_WLHW, 24, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 130 { LLCC_MODPE, 29, 64, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 131 }; 132 133 static const struct llcc_slice_config sc8180x_data[] = { 134 { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1 }, 135 { LLCC_VIDSC0, 2, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 136 { LLCC_VIDSC1, 3, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 137 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 138 { LLCC_MDMHPGRW, 7, 3072, 1, 1, 0x3ff, 0xc00, 0, 0, 0, 1, 0 }, 139 { LLCC_MDM, 8, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 140 { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 141 { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 142 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 143 { LLCC_GPU, 12, 5120, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 144 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1 }, 145 { LLCC_CMPTDMA, 15, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 146 { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 147 { LLCC_VIDFW, 17, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 148 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 149 { LLCC_MDMPNG, 21, 1024, 0, 1, 0xc, 0x0, 0, 0, 0, 1, 0 }, 150 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 151 { LLCC_NPU, 23, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 152 { LLCC_WLHW, 24, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 153 { LLCC_MODPE, 29, 512, 1, 1, 0xc, 0x0, 0, 0, 0, 1, 0 }, 154 { LLCC_APTCM, 30, 512, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 }, 155 { LLCC_WRCACHE, 31, 128, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0 }, 156 }; 157 158 static const struct llcc_slice_config sc8280xp_data[] = { 159 { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, 160 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 161 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 162 { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 163 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 164 { LLCC_GPU, 12, 4096, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, 165 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 166 { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 167 { LLCC_AUDHW, 22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 168 { LLCC_DRE, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 169 { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 170 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 }, 171 { LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 172 { LLCC_CVPFW, 32, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 173 { LLCC_CPUSS1, 33, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 174 { LLCC_CPUHWT, 36, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 175 }; 176 177 static const struct llcc_slice_config sdm845_data[] = { 178 { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 }, 179 { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 180 { LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 181 { LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 }, 182 { LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 183 { LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 184 { LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 }, 185 { LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 186 { LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 187 { LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 }, 188 { LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 }, 189 { LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 }, 190 { LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 191 { LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 192 { LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 193 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 }, 194 { LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 }, 195 { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 196 }; 197 198 static const struct llcc_slice_config sm6350_data[] = { 199 { LLCC_CPUSS, 1, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1 }, 200 { LLCC_MDM, 8, 512, 2, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 201 { LLCC_GPUHTW, 11, 256, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 202 { LLCC_GPU, 12, 512, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 203 { LLCC_MDMPNG, 21, 768, 0, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 204 { LLCC_NPU, 23, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 205 { LLCC_MODPE, 29, 64, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 206 }; 207 208 static const struct llcc_slice_config sm8150_data[] = { 209 { LLCC_CPUSS, 1, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1 }, 210 { LLCC_VIDSC0, 2, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 211 { LLCC_VIDSC1, 3, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 212 { LLCC_AUDIO, 6, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 213 { LLCC_MDMHPGRW, 7, 3072, 1, 0, 0xFF, 0xF00, 0, 0, 0, 1, 0 }, 214 { LLCC_MDM, 8, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 215 { LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 216 { LLCC_CMPT, 10, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 217 { LLCC_GPUHTW , 11, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 218 { LLCC_GPU, 12, 2560, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 219 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1 }, 220 { LLCC_CMPTDMA, 15, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 221 { LLCC_DISP, 16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 222 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 223 { LLCC_MDMHPFX, 21, 1024, 0, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 224 { LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 225 { LLCC_NPU, 23, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 226 { LLCC_WLHW, 24, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 227 { LLCC_MODPE, 29, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 228 { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 }, 229 { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 }, 230 }; 231 232 static const struct llcc_slice_config sm8250_data[] = { 233 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, 234 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 235 { LLCC_AUDIO, 6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 236 { LLCC_CMPT, 10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 237 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 238 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, 239 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 240 { LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 241 { LLCC_DISP, 16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 242 { LLCC_VIDFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 243 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 244 { LLCC_NPU, 23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 245 { LLCC_WLHW, 24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 246 { LLCC_CVP, 28, 256, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 247 { LLCC_APTCM, 30, 128, 3, 0, 0x0, 0x3, 1, 0, 0, 1, 0, 0 }, 248 { LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 249 }; 250 251 static const struct llcc_slice_config sm8350_data[] = { 252 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 1 }, 253 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 254 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 255 { LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 256 { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 257 { LLCC_CMPT, 10, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 258 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 259 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, 260 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, 261 { LLCC_DISP, 16, 3072, 2, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 262 { LLCC_MDMPNG, 21, 1024, 0, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 }, 263 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 264 { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 265 { LLCC_MODPE, 29, 256, 1, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 }, 266 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 0, 1, 0 }, 267 { LLCC_WRCACHE, 31, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, 268 { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 269 { LLCC_CPUSS1, 3, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 270 { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, 271 }; 272 273 static const struct llcc_slice_config sm8450_data[] = { 274 {LLCC_CPUSS, 1, 3072, 1, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 }, 275 {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 276 {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, 277 {LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 278 {LLCC_MODHW, 9, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 279 {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 280 {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 281 {LLCC_GPU, 12, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 1, 0 }, 282 {LLCC_MMUHWT, 13, 768, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 283 {LLCC_DISP, 16, 4096, 2, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 284 {LLCC_MDMPNG, 21, 1024, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 285 {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, 286 {LLCC_CVP, 28, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 287 {LLCC_MODPE, 29, 64, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 288 {LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xF0, 1, 0, 0, 1, 0, 0, 0 }, 289 {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 290 {LLCC_CVPFW, 17, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 291 {LLCC_CPUSS1, 3, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 292 {LLCC_CAMEXP0, 4, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 293 {LLCC_CPUMTE, 23, 256, 1, 1, 0x0FFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 294 {LLCC_CPUHWT, 5, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 }, 295 {LLCC_CAMEXP1, 27, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 296 {LLCC_AENPU, 8, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, 297 }; 298 299 static const u32 llcc_v1_2_reg_offset[] = { 300 [LLCC_COMMON_HW_INFO] = 0x00030000, 301 [LLCC_COMMON_STATUS0] = 0x0003000c, 302 }; 303 304 static const u32 llcc_v21_reg_offset[] = { 305 [LLCC_COMMON_HW_INFO] = 0x00034000, 306 [LLCC_COMMON_STATUS0] = 0x0003400c, 307 }; 308 309 static const struct qcom_llcc_config sc7180_cfg = { 310 .sct_data = sc7180_data, 311 .size = ARRAY_SIZE(sc7180_data), 312 .need_llcc_cfg = true, 313 .reg_offset = llcc_v1_2_reg_offset, 314 }; 315 316 static const struct qcom_llcc_config sc7280_cfg = { 317 .sct_data = sc7280_data, 318 .size = ARRAY_SIZE(sc7280_data), 319 .need_llcc_cfg = true, 320 .reg_offset = llcc_v1_2_reg_offset, 321 }; 322 323 static const struct qcom_llcc_config sc8180x_cfg = { 324 .sct_data = sc8180x_data, 325 .size = ARRAY_SIZE(sc8180x_data), 326 .need_llcc_cfg = true, 327 .reg_offset = llcc_v1_2_reg_offset, 328 }; 329 330 static const struct qcom_llcc_config sc8280xp_cfg = { 331 .sct_data = sc8280xp_data, 332 .size = ARRAY_SIZE(sc8280xp_data), 333 .need_llcc_cfg = true, 334 .reg_offset = llcc_v1_2_reg_offset, 335 }; 336 337 static const struct qcom_llcc_config sdm845_cfg = { 338 .sct_data = sdm845_data, 339 .size = ARRAY_SIZE(sdm845_data), 340 .need_llcc_cfg = false, 341 .reg_offset = llcc_v1_2_reg_offset, 342 }; 343 344 static const struct qcom_llcc_config sm6350_cfg = { 345 .sct_data = sm6350_data, 346 .size = ARRAY_SIZE(sm6350_data), 347 .need_llcc_cfg = true, 348 .reg_offset = llcc_v1_2_reg_offset, 349 }; 350 351 static const struct qcom_llcc_config sm8150_cfg = { 352 .sct_data = sm8150_data, 353 .size = ARRAY_SIZE(sm8150_data), 354 .need_llcc_cfg = true, 355 .reg_offset = llcc_v1_2_reg_offset, 356 }; 357 358 static const struct qcom_llcc_config sm8250_cfg = { 359 .sct_data = sm8250_data, 360 .size = ARRAY_SIZE(sm8250_data), 361 .need_llcc_cfg = true, 362 .reg_offset = llcc_v1_2_reg_offset, 363 }; 364 365 static const struct qcom_llcc_config sm8350_cfg = { 366 .sct_data = sm8350_data, 367 .size = ARRAY_SIZE(sm8350_data), 368 .need_llcc_cfg = true, 369 .reg_offset = llcc_v1_2_reg_offset, 370 }; 371 372 static const struct qcom_llcc_config sm8450_cfg = { 373 .sct_data = sm8450_data, 374 .size = ARRAY_SIZE(sm8450_data), 375 .need_llcc_cfg = true, 376 .reg_offset = llcc_v21_reg_offset, 377 }; 378 379 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; 380 381 /** 382 * llcc_slice_getd - get llcc slice descriptor 383 * @uid: usecase_id for the client 384 * 385 * A pointer to llcc slice descriptor will be returned on success and 386 * and error pointer is returned on failure 387 */ 388 struct llcc_slice_desc *llcc_slice_getd(u32 uid) 389 { 390 const struct llcc_slice_config *cfg; 391 struct llcc_slice_desc *desc; 392 u32 sz, count; 393 394 if (IS_ERR(drv_data)) 395 return ERR_CAST(drv_data); 396 397 cfg = drv_data->cfg; 398 sz = drv_data->cfg_size; 399 400 for (count = 0; cfg && count < sz; count++, cfg++) 401 if (cfg->usecase_id == uid) 402 break; 403 404 if (count == sz || !cfg) 405 return ERR_PTR(-ENODEV); 406 407 desc = kzalloc(sizeof(*desc), GFP_KERNEL); 408 if (!desc) 409 return ERR_PTR(-ENOMEM); 410 411 desc->slice_id = cfg->slice_id; 412 desc->slice_size = cfg->max_cap; 413 414 return desc; 415 } 416 EXPORT_SYMBOL_GPL(llcc_slice_getd); 417 418 /** 419 * llcc_slice_putd - llcc slice descritpor 420 * @desc: Pointer to llcc slice descriptor 421 */ 422 void llcc_slice_putd(struct llcc_slice_desc *desc) 423 { 424 if (!IS_ERR_OR_NULL(desc)) 425 kfree(desc); 426 } 427 EXPORT_SYMBOL_GPL(llcc_slice_putd); 428 429 static int llcc_update_act_ctrl(u32 sid, 430 u32 act_ctrl_reg_val, u32 status) 431 { 432 u32 act_ctrl_reg; 433 u32 status_reg; 434 u32 slice_status; 435 int ret; 436 437 if (IS_ERR(drv_data)) 438 return PTR_ERR(drv_data); 439 440 act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid); 441 status_reg = LLCC_TRP_STATUSn(sid); 442 443 /* Set the ACTIVE trigger */ 444 act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG; 445 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 446 act_ctrl_reg_val); 447 if (ret) 448 return ret; 449 450 /* Clear the ACTIVE trigger */ 451 act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG; 452 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 453 act_ctrl_reg_val); 454 if (ret) 455 return ret; 456 457 ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg, 458 slice_status, !(slice_status & status), 459 0, LLCC_STATUS_READ_DELAY); 460 return ret; 461 } 462 463 /** 464 * llcc_slice_activate - Activate the llcc slice 465 * @desc: Pointer to llcc slice descriptor 466 * 467 * A value of zero will be returned on success and a negative errno will 468 * be returned in error cases 469 */ 470 int llcc_slice_activate(struct llcc_slice_desc *desc) 471 { 472 int ret; 473 u32 act_ctrl_val; 474 475 if (IS_ERR(drv_data)) 476 return PTR_ERR(drv_data); 477 478 if (IS_ERR_OR_NULL(desc)) 479 return -EINVAL; 480 481 mutex_lock(&drv_data->lock); 482 if (test_bit(desc->slice_id, drv_data->bitmap)) { 483 mutex_unlock(&drv_data->lock); 484 return 0; 485 } 486 487 act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT; 488 489 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 490 DEACTIVATE); 491 if (ret) { 492 mutex_unlock(&drv_data->lock); 493 return ret; 494 } 495 496 __set_bit(desc->slice_id, drv_data->bitmap); 497 mutex_unlock(&drv_data->lock); 498 499 return ret; 500 } 501 EXPORT_SYMBOL_GPL(llcc_slice_activate); 502 503 /** 504 * llcc_slice_deactivate - Deactivate the llcc slice 505 * @desc: Pointer to llcc slice descriptor 506 * 507 * A value of zero will be returned on success and a negative errno will 508 * be returned in error cases 509 */ 510 int llcc_slice_deactivate(struct llcc_slice_desc *desc) 511 { 512 u32 act_ctrl_val; 513 int ret; 514 515 if (IS_ERR(drv_data)) 516 return PTR_ERR(drv_data); 517 518 if (IS_ERR_OR_NULL(desc)) 519 return -EINVAL; 520 521 mutex_lock(&drv_data->lock); 522 if (!test_bit(desc->slice_id, drv_data->bitmap)) { 523 mutex_unlock(&drv_data->lock); 524 return 0; 525 } 526 act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT; 527 528 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 529 ACTIVATE); 530 if (ret) { 531 mutex_unlock(&drv_data->lock); 532 return ret; 533 } 534 535 __clear_bit(desc->slice_id, drv_data->bitmap); 536 mutex_unlock(&drv_data->lock); 537 538 return ret; 539 } 540 EXPORT_SYMBOL_GPL(llcc_slice_deactivate); 541 542 /** 543 * llcc_get_slice_id - return the slice id 544 * @desc: Pointer to llcc slice descriptor 545 */ 546 int llcc_get_slice_id(struct llcc_slice_desc *desc) 547 { 548 if (IS_ERR_OR_NULL(desc)) 549 return -EINVAL; 550 551 return desc->slice_id; 552 } 553 EXPORT_SYMBOL_GPL(llcc_get_slice_id); 554 555 /** 556 * llcc_get_slice_size - return the slice id 557 * @desc: Pointer to llcc slice descriptor 558 */ 559 size_t llcc_get_slice_size(struct llcc_slice_desc *desc) 560 { 561 if (IS_ERR_OR_NULL(desc)) 562 return 0; 563 564 return desc->slice_size; 565 } 566 EXPORT_SYMBOL_GPL(llcc_get_slice_size); 567 568 static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, 569 const struct qcom_llcc_config *cfg) 570 { 571 int ret; 572 u32 attr1_cfg; 573 u32 attr0_cfg; 574 u32 attr1_val; 575 u32 attr0_val; 576 u32 max_cap_cacheline; 577 struct llcc_slice_desc desc; 578 579 attr1_val = config->cache_mode; 580 attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT; 581 attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT; 582 attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT; 583 584 max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap); 585 586 /* 587 * LLCC instances can vary for each target. 588 * The SW writes to broadcast register which gets propagated 589 * to each llcc instance (llcc0,.. llccN). 590 * Since the size of the memory is divided equally amongst the 591 * llcc instances, we need to configure the max cap accordingly. 592 */ 593 max_cap_cacheline = max_cap_cacheline / drv_data->num_banks; 594 max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT; 595 attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; 596 597 attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id); 598 599 ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val); 600 if (ret) 601 return ret; 602 603 attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK; 604 attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT; 605 606 attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id); 607 608 ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val); 609 if (ret) 610 return ret; 611 612 if (cfg->need_llcc_cfg) { 613 u32 disable_cap_alloc, retain_pc; 614 615 disable_cap_alloc = config->dis_cap_alloc << config->slice_id; 616 ret = regmap_write(drv_data->bcast_regmap, 617 LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc); 618 if (ret) 619 return ret; 620 621 retain_pc = config->retain_on_pc << config->slice_id; 622 ret = regmap_write(drv_data->bcast_regmap, 623 LLCC_TRP_PCB_ACT, retain_pc); 624 if (ret) 625 return ret; 626 } 627 628 if (drv_data->version >= LLCC_VERSION_2_0_0_0) { 629 u32 wren; 630 631 wren = config->write_scid_en << config->slice_id; 632 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN, 633 BIT(config->slice_id), wren); 634 if (ret) 635 return ret; 636 } 637 638 if (drv_data->version >= LLCC_VERSION_2_1_0_0) { 639 u32 wr_cache_en; 640 641 wr_cache_en = config->write_scid_cacheable_en << config->slice_id; 642 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_CACHEABLE_EN, 643 BIT(config->slice_id), wr_cache_en); 644 if (ret) 645 return ret; 646 } 647 648 if (config->activate_on_init) { 649 desc.slice_id = config->slice_id; 650 ret = llcc_slice_activate(&desc); 651 } 652 653 return ret; 654 } 655 656 static int qcom_llcc_cfg_program(struct platform_device *pdev, 657 const struct qcom_llcc_config *cfg) 658 { 659 int i; 660 u32 sz; 661 int ret = 0; 662 const struct llcc_slice_config *llcc_table; 663 664 sz = drv_data->cfg_size; 665 llcc_table = drv_data->cfg; 666 667 for (i = 0; i < sz; i++) { 668 ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg); 669 if (ret) 670 return ret; 671 } 672 673 return ret; 674 } 675 676 static int qcom_llcc_remove(struct platform_device *pdev) 677 { 678 /* Set the global pointer to a error code to avoid referencing it */ 679 drv_data = ERR_PTR(-ENODEV); 680 return 0; 681 } 682 683 static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, 684 const char *name) 685 { 686 void __iomem *base; 687 struct regmap_config llcc_regmap_config = { 688 .reg_bits = 32, 689 .reg_stride = 4, 690 .val_bits = 32, 691 .fast_io = true, 692 }; 693 694 base = devm_platform_ioremap_resource_byname(pdev, name); 695 if (IS_ERR(base)) 696 return ERR_CAST(base); 697 698 llcc_regmap_config.name = name; 699 return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config); 700 } 701 702 static int qcom_llcc_probe(struct platform_device *pdev) 703 { 704 u32 num_banks; 705 struct device *dev = &pdev->dev; 706 int ret, i; 707 struct platform_device *llcc_edac; 708 const struct qcom_llcc_config *cfg; 709 const struct llcc_slice_config *llcc_cfg; 710 u32 sz; 711 u32 version; 712 713 drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); 714 if (!drv_data) { 715 ret = -ENOMEM; 716 goto err; 717 } 718 719 drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base"); 720 if (IS_ERR(drv_data->regmap)) { 721 ret = PTR_ERR(drv_data->regmap); 722 goto err; 723 } 724 725 drv_data->bcast_regmap = 726 qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); 727 if (IS_ERR(drv_data->bcast_regmap)) { 728 ret = PTR_ERR(drv_data->bcast_regmap); 729 goto err; 730 } 731 732 cfg = of_device_get_match_data(&pdev->dev); 733 734 /* Extract version of the IP */ 735 ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO], 736 &version); 737 if (ret) 738 goto err; 739 740 drv_data->version = version; 741 742 ret = regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], 743 &num_banks); 744 if (ret) 745 goto err; 746 747 num_banks &= LLCC_LB_CNT_MASK; 748 num_banks >>= LLCC_LB_CNT_SHIFT; 749 drv_data->num_banks = num_banks; 750 751 llcc_cfg = cfg->sct_data; 752 sz = cfg->size; 753 754 for (i = 0; i < sz; i++) 755 if (llcc_cfg[i].slice_id > drv_data->max_slices) 756 drv_data->max_slices = llcc_cfg[i].slice_id; 757 758 drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), 759 GFP_KERNEL); 760 if (!drv_data->offsets) { 761 ret = -ENOMEM; 762 goto err; 763 } 764 765 for (i = 0; i < num_banks; i++) 766 drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; 767 768 drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices, 769 GFP_KERNEL); 770 if (!drv_data->bitmap) { 771 ret = -ENOMEM; 772 goto err; 773 } 774 775 drv_data->cfg = llcc_cfg; 776 drv_data->cfg_size = sz; 777 mutex_init(&drv_data->lock); 778 platform_set_drvdata(pdev, drv_data); 779 780 ret = qcom_llcc_cfg_program(pdev, cfg); 781 if (ret) 782 goto err; 783 784 drv_data->ecc_irq = platform_get_irq(pdev, 0); 785 if (drv_data->ecc_irq >= 0) { 786 llcc_edac = platform_device_register_data(&pdev->dev, 787 "qcom_llcc_edac", -1, drv_data, 788 sizeof(*drv_data)); 789 if (IS_ERR(llcc_edac)) 790 dev_err(dev, "Failed to register llcc edac driver\n"); 791 } 792 793 return 0; 794 err: 795 drv_data = ERR_PTR(-ENODEV); 796 return ret; 797 } 798 799 static const struct of_device_id qcom_llcc_of_match[] = { 800 { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, 801 { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg }, 802 { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg }, 803 { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg }, 804 { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, 805 { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg }, 806 { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, 807 { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, 808 { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg }, 809 { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg }, 810 { } 811 }; 812 MODULE_DEVICE_TABLE(of, qcom_llcc_of_match); 813 814 static struct platform_driver qcom_llcc_driver = { 815 .driver = { 816 .name = "qcom-llcc", 817 .of_match_table = qcom_llcc_of_match, 818 }, 819 .probe = qcom_llcc_probe, 820 .remove = qcom_llcc_remove, 821 }; 822 module_platform_driver(qcom_llcc_driver); 823 824 MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller"); 825 MODULE_LICENSE("GPL v2"); 826