1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bitmap.h> 9 #include <linux/bitops.h> 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/regmap.h> 18 #include <linux/sizes.h> 19 #include <linux/slab.h> 20 #include <linux/soc/qcom/llcc-qcom.h> 21 22 #define ACTIVATE BIT(0) 23 #define DEACTIVATE BIT(1) 24 #define ACT_CTRL_OPCODE_ACTIVATE BIT(0) 25 #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1) 26 #define ACT_CTRL_ACT_TRIG BIT(0) 27 #define ACT_CTRL_OPCODE_SHIFT 0x01 28 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02 29 #define ATTR1_FIXED_SIZE_SHIFT 0x03 30 #define ATTR1_PRIORITY_SHIFT 0x04 31 #define ATTR1_MAX_CAP_SHIFT 0x10 32 #define ATTR0_RES_WAYS_MASK GENMASK(15, 0) 33 #define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16) 34 #define ATTR0_BONUS_WAYS_SHIFT 0x10 35 #define LLCC_STATUS_READ_DELAY 100 36 37 #define CACHE_LINE_SIZE_SHIFT 6 38 39 #define LLCC_LB_CNT_MASK GENMASK(31, 28) 40 #define LLCC_LB_CNT_SHIFT 28 41 42 #define MAX_CAP_TO_BYTES(n) (n * SZ_1K) 43 #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K) 44 #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K) 45 #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) 46 #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) 47 48 #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 49 #define LLCC_TRP_PCB_ACT 0x21f04 50 #define LLCC_TRP_WRSC_EN 0x21f20 51 #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c 52 53 #define BANK_OFFSET_STRIDE 0x80000 54 55 #define LLCC_VERSION_2_0_0_0 0x02000000 56 #define LLCC_VERSION_2_1_0_0 0x02010000 57 58 /** 59 * struct llcc_slice_config - Data associated with the llcc slice 60 * @usecase_id: Unique id for the client's use case 61 * @slice_id: llcc slice id for each client 62 * @max_cap: The maximum capacity of the cache slice provided in KB 63 * @priority: Priority of the client used to select victim line for replacement 64 * @fixed_size: Boolean indicating if the slice has a fixed capacity 65 * @bonus_ways: Bonus ways are additional ways to be used for any slice, 66 * if client ends up using more than reserved cache ways. Bonus 67 * ways are allocated only if they are not reserved for some 68 * other client. 69 * @res_ways: Reserved ways for the cache slice, the reserved ways cannot 70 * be used by any other client than the one its assigned to. 71 * @cache_mode: Each slice operates as a cache, this controls the mode of the 72 * slice: normal or TCM(Tightly Coupled Memory) 73 * @probe_target_ways: Determines what ways to probe for access hit. When 74 * configured to 1 only bonus and reserved ways are probed. 75 * When configured to 0 all ways in llcc are probed. 76 * @dis_cap_alloc: Disable capacity based allocation for a client 77 * @retain_on_pc: If this bit is set and client has maintained active vote 78 * then the ways assigned to this client are not flushed on power 79 * collapse. 80 * @activate_on_init: Activate the slice immediately after it is programmed 81 * @write_scid_en: Bit enables write cache support for a given scid. 82 * @write_scid_cacheable_en: Enables write cache cacheable support for a 83 * given scid (not supported on v2 or older hardware). 84 */ 85 struct llcc_slice_config { 86 u32 usecase_id; 87 u32 slice_id; 88 u32 max_cap; 89 u32 priority; 90 bool fixed_size; 91 u32 bonus_ways; 92 u32 res_ways; 93 u32 cache_mode; 94 u32 probe_target_ways; 95 bool dis_cap_alloc; 96 bool retain_on_pc; 97 bool activate_on_init; 98 bool write_scid_en; 99 bool write_scid_cacheable_en; 100 }; 101 102 struct qcom_llcc_config { 103 const struct llcc_slice_config *sct_data; 104 int size; 105 bool need_llcc_cfg; 106 const u32 *reg_offset; 107 const struct llcc_edac_reg_offset *edac_reg_offset; 108 }; 109 110 enum llcc_reg_offset { 111 LLCC_COMMON_HW_INFO, 112 LLCC_COMMON_STATUS0, 113 }; 114 115 static const struct llcc_slice_config sc7180_data[] = { 116 { LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 }, 117 { LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 118 { LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 119 { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 120 }; 121 122 static const struct llcc_slice_config sc7280_data[] = { 123 { LLCC_CPUSS, 1, 768, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 1, 0}, 124 { LLCC_MDMHPGRW, 7, 512, 2, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 125 { LLCC_CMPT, 10, 768, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 126 { LLCC_GPUHTW, 11, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 127 { LLCC_GPU, 12, 512, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 128 { LLCC_MMUHWT, 13, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 0, 1, 0}, 129 { LLCC_MDMPNG, 21, 768, 0, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 130 { LLCC_WLHW, 24, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 131 { LLCC_MODPE, 29, 64, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 132 }; 133 134 static const struct llcc_slice_config sc8180x_data[] = { 135 { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1 }, 136 { LLCC_VIDSC0, 2, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 137 { LLCC_VIDSC1, 3, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 138 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 139 { LLCC_MDMHPGRW, 7, 3072, 1, 1, 0x3ff, 0xc00, 0, 0, 0, 1, 0 }, 140 { LLCC_MDM, 8, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 141 { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 142 { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 143 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 144 { LLCC_GPU, 12, 5120, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 145 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1 }, 146 { LLCC_CMPTDMA, 15, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 147 { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 148 { LLCC_VIDFW, 17, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 149 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 150 { LLCC_MDMPNG, 21, 1024, 0, 1, 0xc, 0x0, 0, 0, 0, 1, 0 }, 151 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 152 { LLCC_NPU, 23, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 153 { LLCC_WLHW, 24, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, 154 { LLCC_MODPE, 29, 512, 1, 1, 0xc, 0x0, 0, 0, 0, 1, 0 }, 155 { LLCC_APTCM, 30, 512, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 }, 156 { LLCC_WRCACHE, 31, 128, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0 }, 157 }; 158 159 static const struct llcc_slice_config sc8280xp_data[] = { 160 { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, 161 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 162 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 163 { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 164 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 165 { LLCC_GPU, 12, 4096, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, 166 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 167 { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 168 { LLCC_AUDHW, 22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 169 { LLCC_DRE, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 170 { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 171 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 }, 172 { LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 173 { LLCC_CVPFW, 32, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 174 { LLCC_CPUSS1, 33, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 175 { LLCC_CPUHWT, 36, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 176 }; 177 178 static const struct llcc_slice_config sdm845_data[] = { 179 { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 }, 180 { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 181 { LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 182 { LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 }, 183 { LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 184 { LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 185 { LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 }, 186 { LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 187 { LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 188 { LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 }, 189 { LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 }, 190 { LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 }, 191 { LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 192 { LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 193 { LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 194 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 }, 195 { LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 }, 196 { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 197 }; 198 199 static const struct llcc_slice_config sm6350_data[] = { 200 { LLCC_CPUSS, 1, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1 }, 201 { LLCC_MDM, 8, 512, 2, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 202 { LLCC_GPUHTW, 11, 256, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 203 { LLCC_GPU, 12, 512, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 204 { LLCC_MDMPNG, 21, 768, 0, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 205 { LLCC_NPU, 23, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 206 { LLCC_MODPE, 29, 64, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 207 }; 208 209 static const struct llcc_slice_config sm8150_data[] = { 210 { LLCC_CPUSS, 1, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1 }, 211 { LLCC_VIDSC0, 2, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 212 { LLCC_VIDSC1, 3, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 213 { LLCC_AUDIO, 6, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 214 { LLCC_MDMHPGRW, 7, 3072, 1, 0, 0xFF, 0xF00, 0, 0, 0, 1, 0 }, 215 { LLCC_MDM, 8, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 216 { LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 217 { LLCC_CMPT, 10, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 218 { LLCC_GPUHTW , 11, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 219 { LLCC_GPU, 12, 2560, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 220 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1 }, 221 { LLCC_CMPTDMA, 15, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 222 { LLCC_DISP, 16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 223 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 224 { LLCC_MDMHPFX, 21, 1024, 0, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 225 { LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 226 { LLCC_NPU, 23, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 227 { LLCC_WLHW, 24, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 228 { LLCC_MODPE, 29, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 229 { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 }, 230 { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 }, 231 }; 232 233 static const struct llcc_slice_config sm8250_data[] = { 234 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, 235 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 236 { LLCC_AUDIO, 6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 237 { LLCC_CMPT, 10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 238 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 239 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, 240 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 241 { LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 242 { LLCC_DISP, 16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 243 { LLCC_VIDFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 244 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 245 { LLCC_NPU, 23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 246 { LLCC_WLHW, 24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 247 { LLCC_CVP, 28, 256, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 248 { LLCC_APTCM, 30, 128, 3, 0, 0x0, 0x3, 1, 0, 0, 1, 0, 0 }, 249 { LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 250 }; 251 252 static const struct llcc_slice_config sm8350_data[] = { 253 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 1 }, 254 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 255 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 256 { LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 257 { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 258 { LLCC_CMPT, 10, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 259 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 260 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, 261 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, 262 { LLCC_DISP, 16, 3072, 2, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 263 { LLCC_MDMPNG, 21, 1024, 0, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 }, 264 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 265 { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 266 { LLCC_MODPE, 29, 256, 1, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 }, 267 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 0, 1, 0 }, 268 { LLCC_WRCACHE, 31, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, 269 { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 270 { LLCC_CPUSS1, 3, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 271 { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, 272 }; 273 274 static const struct llcc_slice_config sm8450_data[] = { 275 {LLCC_CPUSS, 1, 3072, 1, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 }, 276 {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 277 {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, 278 {LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 279 {LLCC_MODHW, 9, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 280 {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 281 {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 282 {LLCC_GPU, 12, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 1, 0 }, 283 {LLCC_MMUHWT, 13, 768, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 284 {LLCC_DISP, 16, 4096, 2, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 285 {LLCC_MDMPNG, 21, 1024, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 286 {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, 287 {LLCC_CVP, 28, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 288 {LLCC_MODPE, 29, 64, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 289 {LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xF0, 1, 0, 0, 1, 0, 0, 0 }, 290 {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 291 {LLCC_CVPFW, 17, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 292 {LLCC_CPUSS1, 3, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 293 {LLCC_CAMEXP0, 4, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 294 {LLCC_CPUMTE, 23, 256, 1, 1, 0x0FFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, 295 {LLCC_CPUHWT, 5, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 }, 296 {LLCC_CAMEXP1, 27, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, 297 {LLCC_AENPU, 8, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, 298 }; 299 300 static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = { 301 .trp_ecc_error_status0 = 0x20344, 302 .trp_ecc_error_status1 = 0x20348, 303 .trp_ecc_sb_err_syn0 = 0x2304c, 304 .trp_ecc_db_err_syn0 = 0x20370, 305 .trp_ecc_error_cntr_clear = 0x20440, 306 .trp_interrupt_0_status = 0x20480, 307 .trp_interrupt_0_clear = 0x20484, 308 .trp_interrupt_0_enable = 0x20488, 309 310 /* LLCC Common registers */ 311 .cmn_status0 = 0x3000c, 312 .cmn_interrupt_0_enable = 0x3001c, 313 .cmn_interrupt_2_enable = 0x3003c, 314 315 /* LLCC DRP registers */ 316 .drp_ecc_error_cfg = 0x40000, 317 .drp_ecc_error_cntr_clear = 0x40004, 318 .drp_interrupt_status = 0x41000, 319 .drp_interrupt_clear = 0x41008, 320 .drp_interrupt_enable = 0x4100c, 321 .drp_ecc_error_status0 = 0x42044, 322 .drp_ecc_error_status1 = 0x42048, 323 .drp_ecc_sb_err_syn0 = 0x4204c, 324 .drp_ecc_db_err_syn0 = 0x42070, 325 }; 326 327 static const struct llcc_edac_reg_offset llcc_v2_1_edac_reg_offset = { 328 .trp_ecc_error_status0 = 0x20344, 329 .trp_ecc_error_status1 = 0x20348, 330 .trp_ecc_sb_err_syn0 = 0x2034c, 331 .trp_ecc_db_err_syn0 = 0x20370, 332 .trp_ecc_error_cntr_clear = 0x20440, 333 .trp_interrupt_0_status = 0x20480, 334 .trp_interrupt_0_clear = 0x20484, 335 .trp_interrupt_0_enable = 0x20488, 336 337 /* LLCC Common registers */ 338 .cmn_status0 = 0x3400c, 339 .cmn_interrupt_0_enable = 0x3401c, 340 .cmn_interrupt_2_enable = 0x3403c, 341 342 /* LLCC DRP registers */ 343 .drp_ecc_error_cfg = 0x50000, 344 .drp_ecc_error_cntr_clear = 0x50004, 345 .drp_interrupt_status = 0x50020, 346 .drp_interrupt_clear = 0x50028, 347 .drp_interrupt_enable = 0x5002c, 348 .drp_ecc_error_status0 = 0x520f4, 349 .drp_ecc_error_status1 = 0x520f8, 350 .drp_ecc_sb_err_syn0 = 0x520fc, 351 .drp_ecc_db_err_syn0 = 0x52120, 352 }; 353 354 /* LLCC register offset starting from v1.0.0 */ 355 static const u32 llcc_v1_reg_offset[] = { 356 [LLCC_COMMON_HW_INFO] = 0x00030000, 357 [LLCC_COMMON_STATUS0] = 0x0003000c, 358 }; 359 360 /* LLCC register offset starting from v2.0.1 */ 361 static const u32 llcc_v2_1_reg_offset[] = { 362 [LLCC_COMMON_HW_INFO] = 0x00034000, 363 [LLCC_COMMON_STATUS0] = 0x0003400c, 364 }; 365 366 static const struct qcom_llcc_config sc7180_cfg = { 367 .sct_data = sc7180_data, 368 .size = ARRAY_SIZE(sc7180_data), 369 .need_llcc_cfg = true, 370 .reg_offset = llcc_v1_reg_offset, 371 .edac_reg_offset = &llcc_v1_edac_reg_offset, 372 }; 373 374 static const struct qcom_llcc_config sc7280_cfg = { 375 .sct_data = sc7280_data, 376 .size = ARRAY_SIZE(sc7280_data), 377 .need_llcc_cfg = true, 378 .reg_offset = llcc_v1_reg_offset, 379 .edac_reg_offset = &llcc_v1_edac_reg_offset, 380 }; 381 382 static const struct qcom_llcc_config sc8180x_cfg = { 383 .sct_data = sc8180x_data, 384 .size = ARRAY_SIZE(sc8180x_data), 385 .need_llcc_cfg = true, 386 .reg_offset = llcc_v1_reg_offset, 387 .edac_reg_offset = &llcc_v1_edac_reg_offset, 388 }; 389 390 static const struct qcom_llcc_config sc8280xp_cfg = { 391 .sct_data = sc8280xp_data, 392 .size = ARRAY_SIZE(sc8280xp_data), 393 .need_llcc_cfg = true, 394 .reg_offset = llcc_v1_reg_offset, 395 .edac_reg_offset = &llcc_v1_edac_reg_offset, 396 }; 397 398 static const struct qcom_llcc_config sdm845_cfg = { 399 .sct_data = sdm845_data, 400 .size = ARRAY_SIZE(sdm845_data), 401 .need_llcc_cfg = false, 402 .reg_offset = llcc_v1_reg_offset, 403 .edac_reg_offset = &llcc_v1_edac_reg_offset, 404 }; 405 406 static const struct qcom_llcc_config sm6350_cfg = { 407 .sct_data = sm6350_data, 408 .size = ARRAY_SIZE(sm6350_data), 409 .need_llcc_cfg = true, 410 .reg_offset = llcc_v1_reg_offset, 411 .edac_reg_offset = &llcc_v1_edac_reg_offset, 412 }; 413 414 static const struct qcom_llcc_config sm8150_cfg = { 415 .sct_data = sm8150_data, 416 .size = ARRAY_SIZE(sm8150_data), 417 .need_llcc_cfg = true, 418 .reg_offset = llcc_v1_reg_offset, 419 .edac_reg_offset = &llcc_v1_edac_reg_offset, 420 }; 421 422 static const struct qcom_llcc_config sm8250_cfg = { 423 .sct_data = sm8250_data, 424 .size = ARRAY_SIZE(sm8250_data), 425 .need_llcc_cfg = true, 426 .reg_offset = llcc_v1_reg_offset, 427 .edac_reg_offset = &llcc_v1_edac_reg_offset, 428 }; 429 430 static const struct qcom_llcc_config sm8350_cfg = { 431 .sct_data = sm8350_data, 432 .size = ARRAY_SIZE(sm8350_data), 433 .need_llcc_cfg = true, 434 .reg_offset = llcc_v1_reg_offset, 435 .edac_reg_offset = &llcc_v1_edac_reg_offset, 436 }; 437 438 static const struct qcom_llcc_config sm8450_cfg = { 439 .sct_data = sm8450_data, 440 .size = ARRAY_SIZE(sm8450_data), 441 .need_llcc_cfg = true, 442 .reg_offset = llcc_v2_1_reg_offset, 443 .edac_reg_offset = &llcc_v2_1_edac_reg_offset, 444 }; 445 446 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; 447 448 /** 449 * llcc_slice_getd - get llcc slice descriptor 450 * @uid: usecase_id for the client 451 * 452 * A pointer to llcc slice descriptor will be returned on success 453 * and error pointer is returned on failure 454 */ 455 struct llcc_slice_desc *llcc_slice_getd(u32 uid) 456 { 457 const struct llcc_slice_config *cfg; 458 struct llcc_slice_desc *desc; 459 u32 sz, count; 460 461 if (IS_ERR(drv_data)) 462 return ERR_CAST(drv_data); 463 464 cfg = drv_data->cfg; 465 sz = drv_data->cfg_size; 466 467 for (count = 0; cfg && count < sz; count++, cfg++) 468 if (cfg->usecase_id == uid) 469 break; 470 471 if (count == sz || !cfg) 472 return ERR_PTR(-ENODEV); 473 474 desc = kzalloc(sizeof(*desc), GFP_KERNEL); 475 if (!desc) 476 return ERR_PTR(-ENOMEM); 477 478 desc->slice_id = cfg->slice_id; 479 desc->slice_size = cfg->max_cap; 480 481 return desc; 482 } 483 EXPORT_SYMBOL_GPL(llcc_slice_getd); 484 485 /** 486 * llcc_slice_putd - llcc slice descritpor 487 * @desc: Pointer to llcc slice descriptor 488 */ 489 void llcc_slice_putd(struct llcc_slice_desc *desc) 490 { 491 if (!IS_ERR_OR_NULL(desc)) 492 kfree(desc); 493 } 494 EXPORT_SYMBOL_GPL(llcc_slice_putd); 495 496 static int llcc_update_act_ctrl(u32 sid, 497 u32 act_ctrl_reg_val, u32 status) 498 { 499 u32 act_ctrl_reg; 500 u32 status_reg; 501 u32 slice_status; 502 int ret; 503 504 if (IS_ERR(drv_data)) 505 return PTR_ERR(drv_data); 506 507 act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid); 508 status_reg = LLCC_TRP_STATUSn(sid); 509 510 /* Set the ACTIVE trigger */ 511 act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG; 512 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 513 act_ctrl_reg_val); 514 if (ret) 515 return ret; 516 517 /* Clear the ACTIVE trigger */ 518 act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG; 519 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 520 act_ctrl_reg_val); 521 if (ret) 522 return ret; 523 524 ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg, 525 slice_status, !(slice_status & status), 526 0, LLCC_STATUS_READ_DELAY); 527 return ret; 528 } 529 530 /** 531 * llcc_slice_activate - Activate the llcc slice 532 * @desc: Pointer to llcc slice descriptor 533 * 534 * A value of zero will be returned on success and a negative errno will 535 * be returned in error cases 536 */ 537 int llcc_slice_activate(struct llcc_slice_desc *desc) 538 { 539 int ret; 540 u32 act_ctrl_val; 541 542 if (IS_ERR(drv_data)) 543 return PTR_ERR(drv_data); 544 545 if (IS_ERR_OR_NULL(desc)) 546 return -EINVAL; 547 548 mutex_lock(&drv_data->lock); 549 if (test_bit(desc->slice_id, drv_data->bitmap)) { 550 mutex_unlock(&drv_data->lock); 551 return 0; 552 } 553 554 act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT; 555 556 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 557 DEACTIVATE); 558 if (ret) { 559 mutex_unlock(&drv_data->lock); 560 return ret; 561 } 562 563 __set_bit(desc->slice_id, drv_data->bitmap); 564 mutex_unlock(&drv_data->lock); 565 566 return ret; 567 } 568 EXPORT_SYMBOL_GPL(llcc_slice_activate); 569 570 /** 571 * llcc_slice_deactivate - Deactivate the llcc slice 572 * @desc: Pointer to llcc slice descriptor 573 * 574 * A value of zero will be returned on success and a negative errno will 575 * be returned in error cases 576 */ 577 int llcc_slice_deactivate(struct llcc_slice_desc *desc) 578 { 579 u32 act_ctrl_val; 580 int ret; 581 582 if (IS_ERR(drv_data)) 583 return PTR_ERR(drv_data); 584 585 if (IS_ERR_OR_NULL(desc)) 586 return -EINVAL; 587 588 mutex_lock(&drv_data->lock); 589 if (!test_bit(desc->slice_id, drv_data->bitmap)) { 590 mutex_unlock(&drv_data->lock); 591 return 0; 592 } 593 act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT; 594 595 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 596 ACTIVATE); 597 if (ret) { 598 mutex_unlock(&drv_data->lock); 599 return ret; 600 } 601 602 __clear_bit(desc->slice_id, drv_data->bitmap); 603 mutex_unlock(&drv_data->lock); 604 605 return ret; 606 } 607 EXPORT_SYMBOL_GPL(llcc_slice_deactivate); 608 609 /** 610 * llcc_get_slice_id - return the slice id 611 * @desc: Pointer to llcc slice descriptor 612 */ 613 int llcc_get_slice_id(struct llcc_slice_desc *desc) 614 { 615 if (IS_ERR_OR_NULL(desc)) 616 return -EINVAL; 617 618 return desc->slice_id; 619 } 620 EXPORT_SYMBOL_GPL(llcc_get_slice_id); 621 622 /** 623 * llcc_get_slice_size - return the slice id 624 * @desc: Pointer to llcc slice descriptor 625 */ 626 size_t llcc_get_slice_size(struct llcc_slice_desc *desc) 627 { 628 if (IS_ERR_OR_NULL(desc)) 629 return 0; 630 631 return desc->slice_size; 632 } 633 EXPORT_SYMBOL_GPL(llcc_get_slice_size); 634 635 static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, 636 const struct qcom_llcc_config *cfg) 637 { 638 int ret; 639 u32 attr1_cfg; 640 u32 attr0_cfg; 641 u32 attr1_val; 642 u32 attr0_val; 643 u32 max_cap_cacheline; 644 struct llcc_slice_desc desc; 645 646 attr1_val = config->cache_mode; 647 attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT; 648 attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT; 649 attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT; 650 651 max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap); 652 653 /* 654 * LLCC instances can vary for each target. 655 * The SW writes to broadcast register which gets propagated 656 * to each llcc instance (llcc0,.. llccN). 657 * Since the size of the memory is divided equally amongst the 658 * llcc instances, we need to configure the max cap accordingly. 659 */ 660 max_cap_cacheline = max_cap_cacheline / drv_data->num_banks; 661 max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT; 662 attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; 663 664 attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id); 665 666 ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val); 667 if (ret) 668 return ret; 669 670 attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK; 671 attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT; 672 673 attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id); 674 675 ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val); 676 if (ret) 677 return ret; 678 679 if (cfg->need_llcc_cfg) { 680 u32 disable_cap_alloc, retain_pc; 681 682 disable_cap_alloc = config->dis_cap_alloc << config->slice_id; 683 ret = regmap_write(drv_data->bcast_regmap, 684 LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc); 685 if (ret) 686 return ret; 687 688 retain_pc = config->retain_on_pc << config->slice_id; 689 ret = regmap_write(drv_data->bcast_regmap, 690 LLCC_TRP_PCB_ACT, retain_pc); 691 if (ret) 692 return ret; 693 } 694 695 if (drv_data->version >= LLCC_VERSION_2_0_0_0) { 696 u32 wren; 697 698 wren = config->write_scid_en << config->slice_id; 699 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN, 700 BIT(config->slice_id), wren); 701 if (ret) 702 return ret; 703 } 704 705 if (drv_data->version >= LLCC_VERSION_2_1_0_0) { 706 u32 wr_cache_en; 707 708 wr_cache_en = config->write_scid_cacheable_en << config->slice_id; 709 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_CACHEABLE_EN, 710 BIT(config->slice_id), wr_cache_en); 711 if (ret) 712 return ret; 713 } 714 715 if (config->activate_on_init) { 716 desc.slice_id = config->slice_id; 717 ret = llcc_slice_activate(&desc); 718 } 719 720 return ret; 721 } 722 723 static int qcom_llcc_cfg_program(struct platform_device *pdev, 724 const struct qcom_llcc_config *cfg) 725 { 726 int i; 727 u32 sz; 728 int ret = 0; 729 const struct llcc_slice_config *llcc_table; 730 731 sz = drv_data->cfg_size; 732 llcc_table = drv_data->cfg; 733 734 for (i = 0; i < sz; i++) { 735 ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg); 736 if (ret) 737 return ret; 738 } 739 740 return ret; 741 } 742 743 static int qcom_llcc_remove(struct platform_device *pdev) 744 { 745 /* Set the global pointer to a error code to avoid referencing it */ 746 drv_data = ERR_PTR(-ENODEV); 747 return 0; 748 } 749 750 static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, 751 const char *name) 752 { 753 void __iomem *base; 754 struct regmap_config llcc_regmap_config = { 755 .reg_bits = 32, 756 .reg_stride = 4, 757 .val_bits = 32, 758 .fast_io = true, 759 }; 760 761 base = devm_platform_ioremap_resource_byname(pdev, name); 762 if (IS_ERR(base)) 763 return ERR_CAST(base); 764 765 llcc_regmap_config.name = name; 766 return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config); 767 } 768 769 static int qcom_llcc_probe(struct platform_device *pdev) 770 { 771 u32 num_banks; 772 struct device *dev = &pdev->dev; 773 int ret, i; 774 struct platform_device *llcc_edac; 775 const struct qcom_llcc_config *cfg; 776 const struct llcc_slice_config *llcc_cfg; 777 u32 sz; 778 u32 version; 779 780 drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); 781 if (!drv_data) { 782 ret = -ENOMEM; 783 goto err; 784 } 785 786 drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base"); 787 if (IS_ERR(drv_data->regmap)) { 788 ret = PTR_ERR(drv_data->regmap); 789 goto err; 790 } 791 792 drv_data->bcast_regmap = 793 qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); 794 if (IS_ERR(drv_data->bcast_regmap)) { 795 ret = PTR_ERR(drv_data->bcast_regmap); 796 goto err; 797 } 798 799 cfg = of_device_get_match_data(&pdev->dev); 800 801 /* Extract version of the IP */ 802 ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO], 803 &version); 804 if (ret) 805 goto err; 806 807 drv_data->version = version; 808 809 ret = regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], 810 &num_banks); 811 if (ret) 812 goto err; 813 814 num_banks &= LLCC_LB_CNT_MASK; 815 num_banks >>= LLCC_LB_CNT_SHIFT; 816 drv_data->num_banks = num_banks; 817 818 llcc_cfg = cfg->sct_data; 819 sz = cfg->size; 820 821 for (i = 0; i < sz; i++) 822 if (llcc_cfg[i].slice_id > drv_data->max_slices) 823 drv_data->max_slices = llcc_cfg[i].slice_id; 824 825 drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), 826 GFP_KERNEL); 827 if (!drv_data->offsets) { 828 ret = -ENOMEM; 829 goto err; 830 } 831 832 for (i = 0; i < num_banks; i++) 833 drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; 834 835 drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices, 836 GFP_KERNEL); 837 if (!drv_data->bitmap) { 838 ret = -ENOMEM; 839 goto err; 840 } 841 842 drv_data->cfg = llcc_cfg; 843 drv_data->cfg_size = sz; 844 drv_data->edac_reg_offset = cfg->edac_reg_offset; 845 mutex_init(&drv_data->lock); 846 platform_set_drvdata(pdev, drv_data); 847 848 ret = qcom_llcc_cfg_program(pdev, cfg); 849 if (ret) 850 goto err; 851 852 drv_data->ecc_irq = platform_get_irq(pdev, 0); 853 if (drv_data->ecc_irq >= 0) { 854 llcc_edac = platform_device_register_data(&pdev->dev, 855 "qcom_llcc_edac", -1, drv_data, 856 sizeof(*drv_data)); 857 if (IS_ERR(llcc_edac)) 858 dev_err(dev, "Failed to register llcc edac driver\n"); 859 } 860 861 return 0; 862 err: 863 drv_data = ERR_PTR(-ENODEV); 864 return ret; 865 } 866 867 static const struct of_device_id qcom_llcc_of_match[] = { 868 { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, 869 { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg }, 870 { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg }, 871 { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg }, 872 { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, 873 { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg }, 874 { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, 875 { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, 876 { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg }, 877 { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg }, 878 { } 879 }; 880 MODULE_DEVICE_TABLE(of, qcom_llcc_of_match); 881 882 static struct platform_driver qcom_llcc_driver = { 883 .driver = { 884 .name = "qcom-llcc", 885 .of_match_table = qcom_llcc_of_match, 886 }, 887 .probe = qcom_llcc_probe, 888 .remove = qcom_llcc_remove, 889 }; 890 module_platform_driver(qcom_llcc_driver); 891 892 MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller"); 893 MODULE_LICENSE("GPL v2"); 894