1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bitmap.h> 9 #include <linux/bitops.h> 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/regmap.h> 18 #include <linux/sizes.h> 19 #include <linux/slab.h> 20 #include <linux/soc/qcom/llcc-qcom.h> 21 22 #define ACTIVATE BIT(0) 23 #define DEACTIVATE BIT(1) 24 #define ACT_CTRL_OPCODE_ACTIVATE BIT(0) 25 #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1) 26 #define ACT_CTRL_ACT_TRIG BIT(0) 27 #define ACT_CTRL_OPCODE_SHIFT 0x01 28 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02 29 #define ATTR1_FIXED_SIZE_SHIFT 0x03 30 #define ATTR1_PRIORITY_SHIFT 0x04 31 #define ATTR1_MAX_CAP_SHIFT 0x10 32 #define ATTR0_RES_WAYS_MASK GENMASK(11, 0) 33 #define ATTR0_BONUS_WAYS_MASK GENMASK(27, 16) 34 #define ATTR0_BONUS_WAYS_SHIFT 0x10 35 #define LLCC_STATUS_READ_DELAY 100 36 37 #define CACHE_LINE_SIZE_SHIFT 6 38 39 #define LLCC_COMMON_HW_INFO 0x00030000 40 #define LLCC_MAJOR_VERSION_MASK GENMASK(31, 24) 41 42 #define LLCC_COMMON_STATUS0 0x0003000c 43 #define LLCC_LB_CNT_MASK GENMASK(31, 28) 44 #define LLCC_LB_CNT_SHIFT 28 45 46 #define MAX_CAP_TO_BYTES(n) (n * SZ_1K) 47 #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K) 48 #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K) 49 #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) 50 #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) 51 52 #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 53 #define LLCC_TRP_PCB_ACT 0x21f04 54 #define LLCC_TRP_WRSC_EN 0x21f20 55 56 #define BANK_OFFSET_STRIDE 0x80000 57 58 /** 59 * struct llcc_slice_config - Data associated with the llcc slice 60 * @usecase_id: Unique id for the client's use case 61 * @slice_id: llcc slice id for each client 62 * @max_cap: The maximum capacity of the cache slice provided in KB 63 * @priority: Priority of the client used to select victim line for replacement 64 * @fixed_size: Boolean indicating if the slice has a fixed capacity 65 * @bonus_ways: Bonus ways are additional ways to be used for any slice, 66 * if client ends up using more than reserved cache ways. Bonus 67 * ways are allocated only if they are not reserved for some 68 * other client. 69 * @res_ways: Reserved ways for the cache slice, the reserved ways cannot 70 * be used by any other client than the one its assigned to. 71 * @cache_mode: Each slice operates as a cache, this controls the mode of the 72 * slice: normal or TCM(Tightly Coupled Memory) 73 * @probe_target_ways: Determines what ways to probe for access hit. When 74 * configured to 1 only bonus and reserved ways are probed. 75 * When configured to 0 all ways in llcc are probed. 76 * @dis_cap_alloc: Disable capacity based allocation for a client 77 * @retain_on_pc: If this bit is set and client has maintained active vote 78 * then the ways assigned to this client are not flushed on power 79 * collapse. 80 * @activate_on_init: Activate the slice immediately after it is programmed 81 * @write_scid_en: Bit enables write cache support for a given scid. 82 */ 83 struct llcc_slice_config { 84 u32 usecase_id; 85 u32 slice_id; 86 u32 max_cap; 87 u32 priority; 88 bool fixed_size; 89 u32 bonus_ways; 90 u32 res_ways; 91 u32 cache_mode; 92 u32 probe_target_ways; 93 bool dis_cap_alloc; 94 bool retain_on_pc; 95 bool activate_on_init; 96 bool write_scid_en; 97 }; 98 99 struct qcom_llcc_config { 100 const struct llcc_slice_config *sct_data; 101 int size; 102 bool need_llcc_cfg; 103 }; 104 105 static const struct llcc_slice_config sc7180_data[] = { 106 { LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 }, 107 { LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 108 { LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 109 { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 110 }; 111 112 static const struct llcc_slice_config sdm845_data[] = { 113 { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 }, 114 { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 115 { LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 116 { LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 }, 117 { LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 118 { LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 119 { LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 }, 120 { LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 121 { LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 122 { LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 }, 123 { LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 }, 124 { LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 }, 125 { LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 126 { LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 127 { LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 128 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 }, 129 { LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 }, 130 { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 131 }; 132 133 static const struct llcc_slice_config sm8150_data[] = { 134 { LLCC_CPUSS, 1, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1 }, 135 { LLCC_VIDSC0, 2, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 136 { LLCC_VIDSC1, 3, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 137 { LLCC_AUDIO, 6, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 138 { LLCC_MDMHPGRW, 7, 3072, 1, 0, 0xFF, 0xF00, 0, 0, 0, 1, 0 }, 139 { LLCC_MDM, 8, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 140 { LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 141 { LLCC_CMPT, 10, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 142 { LLCC_GPUHTW , 11, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 143 { LLCC_GPU, 12, 2560, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 144 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1 }, 145 { LLCC_CMPTDMA, 15, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 146 { LLCC_DISP, 16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 147 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 148 { LLCC_MDMHPFX, 21, 1024, 0, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 149 { LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 150 { LLCC_NPU, 23, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 151 { LLCC_WLHW, 24, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 152 { LLCC_MODPE, 29, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 153 { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 }, 154 { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 }, 155 }; 156 157 static const struct llcc_slice_config sm8250_data[] = { 158 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, 159 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 160 { LLCC_AUDIO, 6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 161 { LLCC_CMPT, 10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 162 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 163 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, 164 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 165 { LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 166 { LLCC_DISP, 16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 167 { LLCC_VIDFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 168 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 169 { LLCC_NPU, 23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 170 { LLCC_WLHW, 24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 171 { LLCC_CVP, 28, 256, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 172 { LLCC_APTCM, 30, 128, 3, 0, 0x0, 0x3, 1, 0, 0, 1, 0, 0 }, 173 { LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 174 }; 175 176 static const struct qcom_llcc_config sc7180_cfg = { 177 .sct_data = sc7180_data, 178 .size = ARRAY_SIZE(sc7180_data), 179 .need_llcc_cfg = true, 180 }; 181 182 static const struct qcom_llcc_config sdm845_cfg = { 183 .sct_data = sdm845_data, 184 .size = ARRAY_SIZE(sdm845_data), 185 .need_llcc_cfg = false, 186 }; 187 188 static const struct qcom_llcc_config sm8150_cfg = { 189 .sct_data = sm8150_data, 190 .size = ARRAY_SIZE(sm8150_data), 191 }; 192 193 static const struct qcom_llcc_config sm8250_cfg = { 194 .sct_data = sm8250_data, 195 .size = ARRAY_SIZE(sm8250_data), 196 }; 197 198 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; 199 200 /** 201 * llcc_slice_getd - get llcc slice descriptor 202 * @uid: usecase_id for the client 203 * 204 * A pointer to llcc slice descriptor will be returned on success and 205 * and error pointer is returned on failure 206 */ 207 struct llcc_slice_desc *llcc_slice_getd(u32 uid) 208 { 209 const struct llcc_slice_config *cfg; 210 struct llcc_slice_desc *desc; 211 u32 sz, count; 212 213 if (IS_ERR(drv_data)) 214 return ERR_CAST(drv_data); 215 216 cfg = drv_data->cfg; 217 sz = drv_data->cfg_size; 218 219 for (count = 0; cfg && count < sz; count++, cfg++) 220 if (cfg->usecase_id == uid) 221 break; 222 223 if (count == sz || !cfg) 224 return ERR_PTR(-ENODEV); 225 226 desc = kzalloc(sizeof(*desc), GFP_KERNEL); 227 if (!desc) 228 return ERR_PTR(-ENOMEM); 229 230 desc->slice_id = cfg->slice_id; 231 desc->slice_size = cfg->max_cap; 232 233 return desc; 234 } 235 EXPORT_SYMBOL_GPL(llcc_slice_getd); 236 237 /** 238 * llcc_slice_putd - llcc slice descritpor 239 * @desc: Pointer to llcc slice descriptor 240 */ 241 void llcc_slice_putd(struct llcc_slice_desc *desc) 242 { 243 if (!IS_ERR_OR_NULL(desc)) 244 kfree(desc); 245 } 246 EXPORT_SYMBOL_GPL(llcc_slice_putd); 247 248 static int llcc_update_act_ctrl(u32 sid, 249 u32 act_ctrl_reg_val, u32 status) 250 { 251 u32 act_ctrl_reg; 252 u32 status_reg; 253 u32 slice_status; 254 int ret; 255 256 if (IS_ERR(drv_data)) 257 return PTR_ERR(drv_data); 258 259 act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid); 260 status_reg = LLCC_TRP_STATUSn(sid); 261 262 /* Set the ACTIVE trigger */ 263 act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG; 264 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 265 act_ctrl_reg_val); 266 if (ret) 267 return ret; 268 269 /* Clear the ACTIVE trigger */ 270 act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG; 271 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 272 act_ctrl_reg_val); 273 if (ret) 274 return ret; 275 276 ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg, 277 slice_status, !(slice_status & status), 278 0, LLCC_STATUS_READ_DELAY); 279 return ret; 280 } 281 282 /** 283 * llcc_slice_activate - Activate the llcc slice 284 * @desc: Pointer to llcc slice descriptor 285 * 286 * A value of zero will be returned on success and a negative errno will 287 * be returned in error cases 288 */ 289 int llcc_slice_activate(struct llcc_slice_desc *desc) 290 { 291 int ret; 292 u32 act_ctrl_val; 293 294 if (IS_ERR(drv_data)) 295 return PTR_ERR(drv_data); 296 297 if (IS_ERR_OR_NULL(desc)) 298 return -EINVAL; 299 300 mutex_lock(&drv_data->lock); 301 if (test_bit(desc->slice_id, drv_data->bitmap)) { 302 mutex_unlock(&drv_data->lock); 303 return 0; 304 } 305 306 act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT; 307 308 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 309 DEACTIVATE); 310 if (ret) { 311 mutex_unlock(&drv_data->lock); 312 return ret; 313 } 314 315 __set_bit(desc->slice_id, drv_data->bitmap); 316 mutex_unlock(&drv_data->lock); 317 318 return ret; 319 } 320 EXPORT_SYMBOL_GPL(llcc_slice_activate); 321 322 /** 323 * llcc_slice_deactivate - Deactivate the llcc slice 324 * @desc: Pointer to llcc slice descriptor 325 * 326 * A value of zero will be returned on success and a negative errno will 327 * be returned in error cases 328 */ 329 int llcc_slice_deactivate(struct llcc_slice_desc *desc) 330 { 331 u32 act_ctrl_val; 332 int ret; 333 334 if (IS_ERR(drv_data)) 335 return PTR_ERR(drv_data); 336 337 if (IS_ERR_OR_NULL(desc)) 338 return -EINVAL; 339 340 mutex_lock(&drv_data->lock); 341 if (!test_bit(desc->slice_id, drv_data->bitmap)) { 342 mutex_unlock(&drv_data->lock); 343 return 0; 344 } 345 act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT; 346 347 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 348 ACTIVATE); 349 if (ret) { 350 mutex_unlock(&drv_data->lock); 351 return ret; 352 } 353 354 __clear_bit(desc->slice_id, drv_data->bitmap); 355 mutex_unlock(&drv_data->lock); 356 357 return ret; 358 } 359 EXPORT_SYMBOL_GPL(llcc_slice_deactivate); 360 361 /** 362 * llcc_get_slice_id - return the slice id 363 * @desc: Pointer to llcc slice descriptor 364 */ 365 int llcc_get_slice_id(struct llcc_slice_desc *desc) 366 { 367 if (IS_ERR_OR_NULL(desc)) 368 return -EINVAL; 369 370 return desc->slice_id; 371 } 372 EXPORT_SYMBOL_GPL(llcc_get_slice_id); 373 374 /** 375 * llcc_get_slice_size - return the slice id 376 * @desc: Pointer to llcc slice descriptor 377 */ 378 size_t llcc_get_slice_size(struct llcc_slice_desc *desc) 379 { 380 if (IS_ERR_OR_NULL(desc)) 381 return 0; 382 383 return desc->slice_size; 384 } 385 EXPORT_SYMBOL_GPL(llcc_get_slice_size); 386 387 static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, 388 const struct qcom_llcc_config *cfg) 389 { 390 int ret; 391 u32 attr1_cfg; 392 u32 attr0_cfg; 393 u32 attr1_val; 394 u32 attr0_val; 395 u32 max_cap_cacheline; 396 struct llcc_slice_desc desc; 397 398 attr1_val = config->cache_mode; 399 attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT; 400 attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT; 401 attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT; 402 403 max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap); 404 405 /* 406 * LLCC instances can vary for each target. 407 * The SW writes to broadcast register which gets propagated 408 * to each llcc instance (llcc0,.. llccN). 409 * Since the size of the memory is divided equally amongst the 410 * llcc instances, we need to configure the max cap accordingly. 411 */ 412 max_cap_cacheline = max_cap_cacheline / drv_data->num_banks; 413 max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT; 414 attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; 415 416 attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id); 417 418 ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val); 419 if (ret) 420 return ret; 421 422 attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK; 423 attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT; 424 425 attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id); 426 427 ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val); 428 if (ret) 429 return ret; 430 431 if (cfg->need_llcc_cfg) { 432 u32 disable_cap_alloc, retain_pc; 433 434 disable_cap_alloc = config->dis_cap_alloc << config->slice_id; 435 ret = regmap_write(drv_data->bcast_regmap, 436 LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc); 437 if (ret) 438 return ret; 439 440 retain_pc = config->retain_on_pc << config->slice_id; 441 ret = regmap_write(drv_data->bcast_regmap, 442 LLCC_TRP_PCB_ACT, retain_pc); 443 if (ret) 444 return ret; 445 } 446 447 if (drv_data->major_version == 2) { 448 u32 wren; 449 450 wren = config->write_scid_en << config->slice_id; 451 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN, 452 BIT(config->slice_id), wren); 453 if (ret) 454 return ret; 455 } 456 457 if (config->activate_on_init) { 458 desc.slice_id = config->slice_id; 459 ret = llcc_slice_activate(&desc); 460 } 461 462 return ret; 463 } 464 465 static int qcom_llcc_cfg_program(struct platform_device *pdev, 466 const struct qcom_llcc_config *cfg) 467 { 468 int i; 469 u32 sz; 470 int ret = 0; 471 const struct llcc_slice_config *llcc_table; 472 473 sz = drv_data->cfg_size; 474 llcc_table = drv_data->cfg; 475 476 for (i = 0; i < sz; i++) { 477 ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg); 478 if (ret) 479 return ret; 480 } 481 482 return ret; 483 } 484 485 static int qcom_llcc_remove(struct platform_device *pdev) 486 { 487 /* Set the global pointer to a error code to avoid referencing it */ 488 drv_data = ERR_PTR(-ENODEV); 489 return 0; 490 } 491 492 static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, 493 const char *name) 494 { 495 void __iomem *base; 496 struct regmap_config llcc_regmap_config = { 497 .reg_bits = 32, 498 .reg_stride = 4, 499 .val_bits = 32, 500 .fast_io = true, 501 }; 502 503 base = devm_platform_ioremap_resource_byname(pdev, name); 504 if (IS_ERR(base)) 505 return ERR_CAST(base); 506 507 llcc_regmap_config.name = name; 508 return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config); 509 } 510 511 static int qcom_llcc_probe(struct platform_device *pdev) 512 { 513 u32 num_banks; 514 struct device *dev = &pdev->dev; 515 int ret, i; 516 struct platform_device *llcc_edac; 517 const struct qcom_llcc_config *cfg; 518 const struct llcc_slice_config *llcc_cfg; 519 u32 sz; 520 u32 version; 521 522 drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); 523 if (!drv_data) { 524 ret = -ENOMEM; 525 goto err; 526 } 527 528 drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base"); 529 if (IS_ERR(drv_data->regmap)) { 530 ret = PTR_ERR(drv_data->regmap); 531 goto err; 532 } 533 534 drv_data->bcast_regmap = 535 qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); 536 if (IS_ERR(drv_data->bcast_regmap)) { 537 ret = PTR_ERR(drv_data->bcast_regmap); 538 goto err; 539 } 540 541 /* Extract major version of the IP */ 542 ret = regmap_read(drv_data->bcast_regmap, LLCC_COMMON_HW_INFO, &version); 543 if (ret) 544 goto err; 545 546 drv_data->major_version = FIELD_GET(LLCC_MAJOR_VERSION_MASK, version); 547 548 ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0, 549 &num_banks); 550 if (ret) 551 goto err; 552 553 num_banks &= LLCC_LB_CNT_MASK; 554 num_banks >>= LLCC_LB_CNT_SHIFT; 555 drv_data->num_banks = num_banks; 556 557 cfg = of_device_get_match_data(&pdev->dev); 558 llcc_cfg = cfg->sct_data; 559 sz = cfg->size; 560 561 for (i = 0; i < sz; i++) 562 if (llcc_cfg[i].slice_id > drv_data->max_slices) 563 drv_data->max_slices = llcc_cfg[i].slice_id; 564 565 drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), 566 GFP_KERNEL); 567 if (!drv_data->offsets) { 568 ret = -ENOMEM; 569 goto err; 570 } 571 572 for (i = 0; i < num_banks; i++) 573 drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; 574 575 drv_data->bitmap = devm_kcalloc(dev, 576 BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long), 577 GFP_KERNEL); 578 if (!drv_data->bitmap) { 579 ret = -ENOMEM; 580 goto err; 581 } 582 583 drv_data->cfg = llcc_cfg; 584 drv_data->cfg_size = sz; 585 mutex_init(&drv_data->lock); 586 platform_set_drvdata(pdev, drv_data); 587 588 ret = qcom_llcc_cfg_program(pdev, cfg); 589 if (ret) 590 goto err; 591 592 drv_data->ecc_irq = platform_get_irq(pdev, 0); 593 if (drv_data->ecc_irq >= 0) { 594 llcc_edac = platform_device_register_data(&pdev->dev, 595 "qcom_llcc_edac", -1, drv_data, 596 sizeof(*drv_data)); 597 if (IS_ERR(llcc_edac)) 598 dev_err(dev, "Failed to register llcc edac driver\n"); 599 } 600 601 return 0; 602 err: 603 drv_data = ERR_PTR(-ENODEV); 604 return ret; 605 } 606 607 static const struct of_device_id qcom_llcc_of_match[] = { 608 { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, 609 { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, 610 { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, 611 { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, 612 { } 613 }; 614 615 static struct platform_driver qcom_llcc_driver = { 616 .driver = { 617 .name = "qcom-llcc", 618 .of_match_table = qcom_llcc_of_match, 619 }, 620 .probe = qcom_llcc_probe, 621 .remove = qcom_llcc_remove, 622 }; 623 module_platform_driver(qcom_llcc_driver); 624 625 MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller"); 626 MODULE_LICENSE("GPL v2"); 627