1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bitmap.h> 9 #include <linux/bitops.h> 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/regmap.h> 18 #include <linux/sizes.h> 19 #include <linux/slab.h> 20 #include <linux/soc/qcom/llcc-qcom.h> 21 22 #define ACTIVATE BIT(0) 23 #define DEACTIVATE BIT(1) 24 #define ACT_CTRL_OPCODE_ACTIVATE BIT(0) 25 #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1) 26 #define ACT_CTRL_ACT_TRIG BIT(0) 27 #define ACT_CTRL_OPCODE_SHIFT 0x01 28 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02 29 #define ATTR1_FIXED_SIZE_SHIFT 0x03 30 #define ATTR1_PRIORITY_SHIFT 0x04 31 #define ATTR1_MAX_CAP_SHIFT 0x10 32 #define ATTR0_RES_WAYS_MASK GENMASK(11, 0) 33 #define ATTR0_BONUS_WAYS_MASK GENMASK(27, 16) 34 #define ATTR0_BONUS_WAYS_SHIFT 0x10 35 #define LLCC_STATUS_READ_DELAY 100 36 37 #define CACHE_LINE_SIZE_SHIFT 6 38 39 #define LLCC_COMMON_HW_INFO 0x00030000 40 #define LLCC_MAJOR_VERSION_MASK GENMASK(31, 24) 41 42 #define LLCC_COMMON_STATUS0 0x0003000c 43 #define LLCC_LB_CNT_MASK GENMASK(31, 28) 44 #define LLCC_LB_CNT_SHIFT 28 45 46 #define MAX_CAP_TO_BYTES(n) (n * SZ_1K) 47 #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K) 48 #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K) 49 #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) 50 #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) 51 52 #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 53 #define LLCC_TRP_PCB_ACT 0x21f04 54 #define LLCC_TRP_WRSC_EN 0x21f20 55 56 #define BANK_OFFSET_STRIDE 0x80000 57 58 /** 59 * struct llcc_slice_config - Data associated with the llcc slice 60 * @usecase_id: Unique id for the client's use case 61 * @slice_id: llcc slice id for each client 62 * @max_cap: The maximum capacity of the cache slice provided in KB 63 * @priority: Priority of the client used to select victim line for replacement 64 * @fixed_size: Boolean indicating if the slice has a fixed capacity 65 * @bonus_ways: Bonus ways are additional ways to be used for any slice, 66 * if client ends up using more than reserved cache ways. Bonus 67 * ways are allocated only if they are not reserved for some 68 * other client. 69 * @res_ways: Reserved ways for the cache slice, the reserved ways cannot 70 * be used by any other client than the one its assigned to. 71 * @cache_mode: Each slice operates as a cache, this controls the mode of the 72 * slice: normal or TCM(Tightly Coupled Memory) 73 * @probe_target_ways: Determines what ways to probe for access hit. When 74 * configured to 1 only bonus and reserved ways are probed. 75 * When configured to 0 all ways in llcc are probed. 76 * @dis_cap_alloc: Disable capacity based allocation for a client 77 * @retain_on_pc: If this bit is set and client has maintained active vote 78 * then the ways assigned to this client are not flushed on power 79 * collapse. 80 * @activate_on_init: Activate the slice immediately after it is programmed 81 * @write_scid_en: Bit enables write cache support for a given scid. 82 */ 83 struct llcc_slice_config { 84 u32 usecase_id; 85 u32 slice_id; 86 u32 max_cap; 87 u32 priority; 88 bool fixed_size; 89 u32 bonus_ways; 90 u32 res_ways; 91 u32 cache_mode; 92 u32 probe_target_ways; 93 bool dis_cap_alloc; 94 bool retain_on_pc; 95 bool activate_on_init; 96 bool write_scid_en; 97 }; 98 99 struct qcom_llcc_config { 100 const struct llcc_slice_config *sct_data; 101 int size; 102 bool need_llcc_cfg; 103 }; 104 105 static const struct llcc_slice_config sc7180_data[] = { 106 { LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 }, 107 { LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 108 { LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 109 { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 110 }; 111 112 static const struct llcc_slice_config sc7280_data[] = { 113 { LLCC_CPUSS, 1, 768, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 1, 0}, 114 { LLCC_MDMHPGRW, 7, 512, 2, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 115 { LLCC_CMPT, 10, 768, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 116 { LLCC_GPUHTW, 11, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 117 { LLCC_GPU, 12, 512, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 118 { LLCC_MMUHWT, 13, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 1, 0}, 119 { LLCC_MDMPNG, 21, 768, 0, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 120 { LLCC_WLHW, 24, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 121 { LLCC_MODPE, 29, 64, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 122 }; 123 124 static const struct llcc_slice_config sdm845_data[] = { 125 { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 }, 126 { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 127 { LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 128 { LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 }, 129 { LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 130 { LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 131 { LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 }, 132 { LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 133 { LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 134 { LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 }, 135 { LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 }, 136 { LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 }, 137 { LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 138 { LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 139 { LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 140 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 }, 141 { LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 }, 142 { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 143 }; 144 145 static const struct llcc_slice_config sm8150_data[] = { 146 { LLCC_CPUSS, 1, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1 }, 147 { LLCC_VIDSC0, 2, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 148 { LLCC_VIDSC1, 3, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 149 { LLCC_AUDIO, 6, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 150 { LLCC_MDMHPGRW, 7, 3072, 1, 0, 0xFF, 0xF00, 0, 0, 0, 1, 0 }, 151 { LLCC_MDM, 8, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 152 { LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 153 { LLCC_CMPT, 10, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 154 { LLCC_GPUHTW , 11, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 155 { LLCC_GPU, 12, 2560, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 156 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1 }, 157 { LLCC_CMPTDMA, 15, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 158 { LLCC_DISP, 16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 159 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 160 { LLCC_MDMHPFX, 21, 1024, 0, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 161 { LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 162 { LLCC_NPU, 23, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 163 { LLCC_WLHW, 24, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 164 { LLCC_MODPE, 29, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 165 { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 }, 166 { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 }, 167 }; 168 169 static const struct llcc_slice_config sm8250_data[] = { 170 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, 171 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 172 { LLCC_AUDIO, 6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 173 { LLCC_CMPT, 10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 174 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 175 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, 176 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 177 { LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 178 { LLCC_DISP, 16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 179 { LLCC_VIDFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 180 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 181 { LLCC_NPU, 23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 182 { LLCC_WLHW, 24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 183 { LLCC_CVP, 28, 256, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 184 { LLCC_APTCM, 30, 128, 3, 0, 0x0, 0x3, 1, 0, 0, 1, 0, 0 }, 185 { LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 186 }; 187 188 static const struct qcom_llcc_config sc7180_cfg = { 189 .sct_data = sc7180_data, 190 .size = ARRAY_SIZE(sc7180_data), 191 .need_llcc_cfg = true, 192 }; 193 194 static const struct qcom_llcc_config sc7280_cfg = { 195 .sct_data = sc7280_data, 196 .size = ARRAY_SIZE(sc7280_data), 197 .need_llcc_cfg = true, 198 }; 199 200 static const struct qcom_llcc_config sdm845_cfg = { 201 .sct_data = sdm845_data, 202 .size = ARRAY_SIZE(sdm845_data), 203 .need_llcc_cfg = false, 204 }; 205 206 static const struct qcom_llcc_config sm8150_cfg = { 207 .sct_data = sm8150_data, 208 .size = ARRAY_SIZE(sm8150_data), 209 }; 210 211 static const struct qcom_llcc_config sm8250_cfg = { 212 .sct_data = sm8250_data, 213 .size = ARRAY_SIZE(sm8250_data), 214 }; 215 216 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; 217 218 /** 219 * llcc_slice_getd - get llcc slice descriptor 220 * @uid: usecase_id for the client 221 * 222 * A pointer to llcc slice descriptor will be returned on success and 223 * and error pointer is returned on failure 224 */ 225 struct llcc_slice_desc *llcc_slice_getd(u32 uid) 226 { 227 const struct llcc_slice_config *cfg; 228 struct llcc_slice_desc *desc; 229 u32 sz, count; 230 231 if (IS_ERR(drv_data)) 232 return ERR_CAST(drv_data); 233 234 cfg = drv_data->cfg; 235 sz = drv_data->cfg_size; 236 237 for (count = 0; cfg && count < sz; count++, cfg++) 238 if (cfg->usecase_id == uid) 239 break; 240 241 if (count == sz || !cfg) 242 return ERR_PTR(-ENODEV); 243 244 desc = kzalloc(sizeof(*desc), GFP_KERNEL); 245 if (!desc) 246 return ERR_PTR(-ENOMEM); 247 248 desc->slice_id = cfg->slice_id; 249 desc->slice_size = cfg->max_cap; 250 251 return desc; 252 } 253 EXPORT_SYMBOL_GPL(llcc_slice_getd); 254 255 /** 256 * llcc_slice_putd - llcc slice descritpor 257 * @desc: Pointer to llcc slice descriptor 258 */ 259 void llcc_slice_putd(struct llcc_slice_desc *desc) 260 { 261 if (!IS_ERR_OR_NULL(desc)) 262 kfree(desc); 263 } 264 EXPORT_SYMBOL_GPL(llcc_slice_putd); 265 266 static int llcc_update_act_ctrl(u32 sid, 267 u32 act_ctrl_reg_val, u32 status) 268 { 269 u32 act_ctrl_reg; 270 u32 status_reg; 271 u32 slice_status; 272 int ret; 273 274 if (IS_ERR(drv_data)) 275 return PTR_ERR(drv_data); 276 277 act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid); 278 status_reg = LLCC_TRP_STATUSn(sid); 279 280 /* Set the ACTIVE trigger */ 281 act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG; 282 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 283 act_ctrl_reg_val); 284 if (ret) 285 return ret; 286 287 /* Clear the ACTIVE trigger */ 288 act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG; 289 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 290 act_ctrl_reg_val); 291 if (ret) 292 return ret; 293 294 ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg, 295 slice_status, !(slice_status & status), 296 0, LLCC_STATUS_READ_DELAY); 297 return ret; 298 } 299 300 /** 301 * llcc_slice_activate - Activate the llcc slice 302 * @desc: Pointer to llcc slice descriptor 303 * 304 * A value of zero will be returned on success and a negative errno will 305 * be returned in error cases 306 */ 307 int llcc_slice_activate(struct llcc_slice_desc *desc) 308 { 309 int ret; 310 u32 act_ctrl_val; 311 312 if (IS_ERR(drv_data)) 313 return PTR_ERR(drv_data); 314 315 if (IS_ERR_OR_NULL(desc)) 316 return -EINVAL; 317 318 mutex_lock(&drv_data->lock); 319 if (test_bit(desc->slice_id, drv_data->bitmap)) { 320 mutex_unlock(&drv_data->lock); 321 return 0; 322 } 323 324 act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT; 325 326 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 327 DEACTIVATE); 328 if (ret) { 329 mutex_unlock(&drv_data->lock); 330 return ret; 331 } 332 333 __set_bit(desc->slice_id, drv_data->bitmap); 334 mutex_unlock(&drv_data->lock); 335 336 return ret; 337 } 338 EXPORT_SYMBOL_GPL(llcc_slice_activate); 339 340 /** 341 * llcc_slice_deactivate - Deactivate the llcc slice 342 * @desc: Pointer to llcc slice descriptor 343 * 344 * A value of zero will be returned on success and a negative errno will 345 * be returned in error cases 346 */ 347 int llcc_slice_deactivate(struct llcc_slice_desc *desc) 348 { 349 u32 act_ctrl_val; 350 int ret; 351 352 if (IS_ERR(drv_data)) 353 return PTR_ERR(drv_data); 354 355 if (IS_ERR_OR_NULL(desc)) 356 return -EINVAL; 357 358 mutex_lock(&drv_data->lock); 359 if (!test_bit(desc->slice_id, drv_data->bitmap)) { 360 mutex_unlock(&drv_data->lock); 361 return 0; 362 } 363 act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT; 364 365 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 366 ACTIVATE); 367 if (ret) { 368 mutex_unlock(&drv_data->lock); 369 return ret; 370 } 371 372 __clear_bit(desc->slice_id, drv_data->bitmap); 373 mutex_unlock(&drv_data->lock); 374 375 return ret; 376 } 377 EXPORT_SYMBOL_GPL(llcc_slice_deactivate); 378 379 /** 380 * llcc_get_slice_id - return the slice id 381 * @desc: Pointer to llcc slice descriptor 382 */ 383 int llcc_get_slice_id(struct llcc_slice_desc *desc) 384 { 385 if (IS_ERR_OR_NULL(desc)) 386 return -EINVAL; 387 388 return desc->slice_id; 389 } 390 EXPORT_SYMBOL_GPL(llcc_get_slice_id); 391 392 /** 393 * llcc_get_slice_size - return the slice id 394 * @desc: Pointer to llcc slice descriptor 395 */ 396 size_t llcc_get_slice_size(struct llcc_slice_desc *desc) 397 { 398 if (IS_ERR_OR_NULL(desc)) 399 return 0; 400 401 return desc->slice_size; 402 } 403 EXPORT_SYMBOL_GPL(llcc_get_slice_size); 404 405 static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, 406 const struct qcom_llcc_config *cfg) 407 { 408 int ret; 409 u32 attr1_cfg; 410 u32 attr0_cfg; 411 u32 attr1_val; 412 u32 attr0_val; 413 u32 max_cap_cacheline; 414 struct llcc_slice_desc desc; 415 416 attr1_val = config->cache_mode; 417 attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT; 418 attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT; 419 attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT; 420 421 max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap); 422 423 /* 424 * LLCC instances can vary for each target. 425 * The SW writes to broadcast register which gets propagated 426 * to each llcc instance (llcc0,.. llccN). 427 * Since the size of the memory is divided equally amongst the 428 * llcc instances, we need to configure the max cap accordingly. 429 */ 430 max_cap_cacheline = max_cap_cacheline / drv_data->num_banks; 431 max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT; 432 attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; 433 434 attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id); 435 436 ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val); 437 if (ret) 438 return ret; 439 440 attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK; 441 attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT; 442 443 attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id); 444 445 ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val); 446 if (ret) 447 return ret; 448 449 if (cfg->need_llcc_cfg) { 450 u32 disable_cap_alloc, retain_pc; 451 452 disable_cap_alloc = config->dis_cap_alloc << config->slice_id; 453 ret = regmap_write(drv_data->bcast_regmap, 454 LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc); 455 if (ret) 456 return ret; 457 458 retain_pc = config->retain_on_pc << config->slice_id; 459 ret = regmap_write(drv_data->bcast_regmap, 460 LLCC_TRP_PCB_ACT, retain_pc); 461 if (ret) 462 return ret; 463 } 464 465 if (drv_data->major_version == 2) { 466 u32 wren; 467 468 wren = config->write_scid_en << config->slice_id; 469 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN, 470 BIT(config->slice_id), wren); 471 if (ret) 472 return ret; 473 } 474 475 if (config->activate_on_init) { 476 desc.slice_id = config->slice_id; 477 ret = llcc_slice_activate(&desc); 478 } 479 480 return ret; 481 } 482 483 static int qcom_llcc_cfg_program(struct platform_device *pdev, 484 const struct qcom_llcc_config *cfg) 485 { 486 int i; 487 u32 sz; 488 int ret = 0; 489 const struct llcc_slice_config *llcc_table; 490 491 sz = drv_data->cfg_size; 492 llcc_table = drv_data->cfg; 493 494 for (i = 0; i < sz; i++) { 495 ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg); 496 if (ret) 497 return ret; 498 } 499 500 return ret; 501 } 502 503 static int qcom_llcc_remove(struct platform_device *pdev) 504 { 505 /* Set the global pointer to a error code to avoid referencing it */ 506 drv_data = ERR_PTR(-ENODEV); 507 return 0; 508 } 509 510 static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, 511 const char *name) 512 { 513 void __iomem *base; 514 struct regmap_config llcc_regmap_config = { 515 .reg_bits = 32, 516 .reg_stride = 4, 517 .val_bits = 32, 518 .fast_io = true, 519 }; 520 521 base = devm_platform_ioremap_resource_byname(pdev, name); 522 if (IS_ERR(base)) 523 return ERR_CAST(base); 524 525 llcc_regmap_config.name = name; 526 return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config); 527 } 528 529 static int qcom_llcc_probe(struct platform_device *pdev) 530 { 531 u32 num_banks; 532 struct device *dev = &pdev->dev; 533 int ret, i; 534 struct platform_device *llcc_edac; 535 const struct qcom_llcc_config *cfg; 536 const struct llcc_slice_config *llcc_cfg; 537 u32 sz; 538 u32 version; 539 540 drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); 541 if (!drv_data) { 542 ret = -ENOMEM; 543 goto err; 544 } 545 546 drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base"); 547 if (IS_ERR(drv_data->regmap)) { 548 ret = PTR_ERR(drv_data->regmap); 549 goto err; 550 } 551 552 drv_data->bcast_regmap = 553 qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); 554 if (IS_ERR(drv_data->bcast_regmap)) { 555 ret = PTR_ERR(drv_data->bcast_regmap); 556 goto err; 557 } 558 559 /* Extract major version of the IP */ 560 ret = regmap_read(drv_data->bcast_regmap, LLCC_COMMON_HW_INFO, &version); 561 if (ret) 562 goto err; 563 564 drv_data->major_version = FIELD_GET(LLCC_MAJOR_VERSION_MASK, version); 565 566 ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0, 567 &num_banks); 568 if (ret) 569 goto err; 570 571 num_banks &= LLCC_LB_CNT_MASK; 572 num_banks >>= LLCC_LB_CNT_SHIFT; 573 drv_data->num_banks = num_banks; 574 575 cfg = of_device_get_match_data(&pdev->dev); 576 llcc_cfg = cfg->sct_data; 577 sz = cfg->size; 578 579 for (i = 0; i < sz; i++) 580 if (llcc_cfg[i].slice_id > drv_data->max_slices) 581 drv_data->max_slices = llcc_cfg[i].slice_id; 582 583 drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), 584 GFP_KERNEL); 585 if (!drv_data->offsets) { 586 ret = -ENOMEM; 587 goto err; 588 } 589 590 for (i = 0; i < num_banks; i++) 591 drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; 592 593 drv_data->bitmap = devm_kcalloc(dev, 594 BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long), 595 GFP_KERNEL); 596 if (!drv_data->bitmap) { 597 ret = -ENOMEM; 598 goto err; 599 } 600 601 drv_data->cfg = llcc_cfg; 602 drv_data->cfg_size = sz; 603 mutex_init(&drv_data->lock); 604 platform_set_drvdata(pdev, drv_data); 605 606 ret = qcom_llcc_cfg_program(pdev, cfg); 607 if (ret) 608 goto err; 609 610 drv_data->ecc_irq = platform_get_irq(pdev, 0); 611 if (drv_data->ecc_irq >= 0) { 612 llcc_edac = platform_device_register_data(&pdev->dev, 613 "qcom_llcc_edac", -1, drv_data, 614 sizeof(*drv_data)); 615 if (IS_ERR(llcc_edac)) 616 dev_err(dev, "Failed to register llcc edac driver\n"); 617 } 618 619 return 0; 620 err: 621 drv_data = ERR_PTR(-ENODEV); 622 return ret; 623 } 624 625 static const struct of_device_id qcom_llcc_of_match[] = { 626 { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, 627 { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg }, 628 { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, 629 { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, 630 { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, 631 { } 632 }; 633 634 static struct platform_driver qcom_llcc_driver = { 635 .driver = { 636 .name = "qcom-llcc", 637 .of_match_table = qcom_llcc_of_match, 638 }, 639 .probe = qcom_llcc_probe, 640 .remove = qcom_llcc_remove, 641 }; 642 module_platform_driver(qcom_llcc_driver); 643 644 MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller"); 645 MODULE_LICENSE("GPL v2"); 646