1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bitmap.h> 9 #include <linux/bitops.h> 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/regmap.h> 18 #include <linux/sizes.h> 19 #include <linux/slab.h> 20 #include <linux/soc/qcom/llcc-qcom.h> 21 22 #define ACTIVATE BIT(0) 23 #define DEACTIVATE BIT(1) 24 #define ACT_CTRL_OPCODE_ACTIVATE BIT(0) 25 #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1) 26 #define ACT_CTRL_ACT_TRIG BIT(0) 27 #define ACT_CTRL_OPCODE_SHIFT 0x01 28 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02 29 #define ATTR1_FIXED_SIZE_SHIFT 0x03 30 #define ATTR1_PRIORITY_SHIFT 0x04 31 #define ATTR1_MAX_CAP_SHIFT 0x10 32 #define ATTR0_RES_WAYS_MASK GENMASK(11, 0) 33 #define ATTR0_BONUS_WAYS_MASK GENMASK(27, 16) 34 #define ATTR0_BONUS_WAYS_SHIFT 0x10 35 #define LLCC_STATUS_READ_DELAY 100 36 37 #define CACHE_LINE_SIZE_SHIFT 6 38 39 #define LLCC_COMMON_HW_INFO 0x00030000 40 #define LLCC_MAJOR_VERSION_MASK GENMASK(31, 24) 41 42 #define LLCC_COMMON_STATUS0 0x0003000c 43 #define LLCC_LB_CNT_MASK GENMASK(31, 28) 44 #define LLCC_LB_CNT_SHIFT 28 45 46 #define MAX_CAP_TO_BYTES(n) (n * SZ_1K) 47 #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K) 48 #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K) 49 #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) 50 #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) 51 52 #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 53 #define LLCC_TRP_PCB_ACT 0x21f04 54 #define LLCC_TRP_WRSC_EN 0x21f20 55 56 #define BANK_OFFSET_STRIDE 0x80000 57 58 /** 59 * struct llcc_slice_config - Data associated with the llcc slice 60 * @usecase_id: Unique id for the client's use case 61 * @slice_id: llcc slice id for each client 62 * @max_cap: The maximum capacity of the cache slice provided in KB 63 * @priority: Priority of the client used to select victim line for replacement 64 * @fixed_size: Boolean indicating if the slice has a fixed capacity 65 * @bonus_ways: Bonus ways are additional ways to be used for any slice, 66 * if client ends up using more than reserved cache ways. Bonus 67 * ways are allocated only if they are not reserved for some 68 * other client. 69 * @res_ways: Reserved ways for the cache slice, the reserved ways cannot 70 * be used by any other client than the one its assigned to. 71 * @cache_mode: Each slice operates as a cache, this controls the mode of the 72 * slice: normal or TCM(Tightly Coupled Memory) 73 * @probe_target_ways: Determines what ways to probe for access hit. When 74 * configured to 1 only bonus and reserved ways are probed. 75 * When configured to 0 all ways in llcc are probed. 76 * @dis_cap_alloc: Disable capacity based allocation for a client 77 * @retain_on_pc: If this bit is set and client has maintained active vote 78 * then the ways assigned to this client are not flushed on power 79 * collapse. 80 * @activate_on_init: Activate the slice immediately after it is programmed 81 * @write_scid_en: Bit enables write cache support for a given scid. 82 */ 83 struct llcc_slice_config { 84 u32 usecase_id; 85 u32 slice_id; 86 u32 max_cap; 87 u32 priority; 88 bool fixed_size; 89 u32 bonus_ways; 90 u32 res_ways; 91 u32 cache_mode; 92 u32 probe_target_ways; 93 bool dis_cap_alloc; 94 bool retain_on_pc; 95 bool activate_on_init; 96 bool write_scid_en; 97 }; 98 99 struct qcom_llcc_config { 100 const struct llcc_slice_config *sct_data; 101 int size; 102 bool need_llcc_cfg; 103 }; 104 105 static const struct llcc_slice_config sc7180_data[] = { 106 { LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 }, 107 { LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 108 { LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 109 { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 110 }; 111 112 static const struct llcc_slice_config sc7280_data[] = { 113 { LLCC_CPUSS, 1, 768, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 1, 0}, 114 { LLCC_MDMHPGRW, 7, 512, 2, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 115 { LLCC_CMPT, 10, 768, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 116 { LLCC_GPUHTW, 11, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 117 { LLCC_GPU, 12, 512, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 118 { LLCC_MMUHWT, 13, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 0, 1, 0}, 119 { LLCC_MDMPNG, 21, 768, 0, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 120 { LLCC_WLHW, 24, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 121 { LLCC_MODPE, 29, 64, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, 122 }; 123 124 static const struct llcc_slice_config sdm845_data[] = { 125 { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 }, 126 { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 127 { LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 128 { LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 }, 129 { LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 130 { LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 131 { LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 }, 132 { LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 133 { LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 134 { LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 }, 135 { LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 }, 136 { LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 }, 137 { LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 138 { LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 139 { LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 140 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 }, 141 { LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 }, 142 { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 143 }; 144 145 static const struct llcc_slice_config sm6350_data[] = { 146 { LLCC_CPUSS, 1, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1 }, 147 { LLCC_MDM, 8, 512, 2, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 148 { LLCC_GPUHTW, 11, 256, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 149 { LLCC_GPU, 12, 512, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 150 { LLCC_MDMPNG, 21, 768, 0, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 151 { LLCC_NPU, 23, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 152 { LLCC_MODPE, 29, 64, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, 153 }; 154 155 static const struct llcc_slice_config sm8150_data[] = { 156 { LLCC_CPUSS, 1, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1 }, 157 { LLCC_VIDSC0, 2, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 158 { LLCC_VIDSC1, 3, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 159 { LLCC_AUDIO, 6, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 160 { LLCC_MDMHPGRW, 7, 3072, 1, 0, 0xFF, 0xF00, 0, 0, 0, 1, 0 }, 161 { LLCC_MDM, 8, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 162 { LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 163 { LLCC_CMPT, 10, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 164 { LLCC_GPUHTW , 11, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 165 { LLCC_GPU, 12, 2560, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 166 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1 }, 167 { LLCC_CMPTDMA, 15, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 168 { LLCC_DISP, 16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 169 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 170 { LLCC_MDMHPFX, 21, 1024, 0, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 171 { LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 172 { LLCC_NPU, 23, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 173 { LLCC_WLHW, 24, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, 174 { LLCC_MODPE, 29, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, 175 { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 }, 176 { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 }, 177 }; 178 179 static const struct llcc_slice_config sm8250_data[] = { 180 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, 181 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 182 { LLCC_AUDIO, 6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 183 { LLCC_CMPT, 10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, 184 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 185 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, 186 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 187 { LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 188 { LLCC_DISP, 16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 189 { LLCC_VIDFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 190 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 191 { LLCC_NPU, 23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 192 { LLCC_WLHW, 24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 193 { LLCC_CVP, 28, 256, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, 194 { LLCC_APTCM, 30, 128, 3, 0, 0x0, 0x3, 1, 0, 0, 1, 0, 0 }, 195 { LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, 196 }; 197 198 static const struct qcom_llcc_config sc7180_cfg = { 199 .sct_data = sc7180_data, 200 .size = ARRAY_SIZE(sc7180_data), 201 .need_llcc_cfg = true, 202 }; 203 204 static const struct qcom_llcc_config sc7280_cfg = { 205 .sct_data = sc7280_data, 206 .size = ARRAY_SIZE(sc7280_data), 207 .need_llcc_cfg = true, 208 }; 209 210 static const struct qcom_llcc_config sdm845_cfg = { 211 .sct_data = sdm845_data, 212 .size = ARRAY_SIZE(sdm845_data), 213 .need_llcc_cfg = false, 214 }; 215 216 static const struct qcom_llcc_config sm6350_cfg = { 217 .sct_data = sm6350_data, 218 .size = ARRAY_SIZE(sm6350_data), 219 }; 220 221 static const struct qcom_llcc_config sm8150_cfg = { 222 .sct_data = sm8150_data, 223 .size = ARRAY_SIZE(sm8150_data), 224 }; 225 226 static const struct qcom_llcc_config sm8250_cfg = { 227 .sct_data = sm8250_data, 228 .size = ARRAY_SIZE(sm8250_data), 229 }; 230 231 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; 232 233 /** 234 * llcc_slice_getd - get llcc slice descriptor 235 * @uid: usecase_id for the client 236 * 237 * A pointer to llcc slice descriptor will be returned on success and 238 * and error pointer is returned on failure 239 */ 240 struct llcc_slice_desc *llcc_slice_getd(u32 uid) 241 { 242 const struct llcc_slice_config *cfg; 243 struct llcc_slice_desc *desc; 244 u32 sz, count; 245 246 if (IS_ERR(drv_data)) 247 return ERR_CAST(drv_data); 248 249 cfg = drv_data->cfg; 250 sz = drv_data->cfg_size; 251 252 for (count = 0; cfg && count < sz; count++, cfg++) 253 if (cfg->usecase_id == uid) 254 break; 255 256 if (count == sz || !cfg) 257 return ERR_PTR(-ENODEV); 258 259 desc = kzalloc(sizeof(*desc), GFP_KERNEL); 260 if (!desc) 261 return ERR_PTR(-ENOMEM); 262 263 desc->slice_id = cfg->slice_id; 264 desc->slice_size = cfg->max_cap; 265 266 return desc; 267 } 268 EXPORT_SYMBOL_GPL(llcc_slice_getd); 269 270 /** 271 * llcc_slice_putd - llcc slice descritpor 272 * @desc: Pointer to llcc slice descriptor 273 */ 274 void llcc_slice_putd(struct llcc_slice_desc *desc) 275 { 276 if (!IS_ERR_OR_NULL(desc)) 277 kfree(desc); 278 } 279 EXPORT_SYMBOL_GPL(llcc_slice_putd); 280 281 static int llcc_update_act_ctrl(u32 sid, 282 u32 act_ctrl_reg_val, u32 status) 283 { 284 u32 act_ctrl_reg; 285 u32 status_reg; 286 u32 slice_status; 287 int ret; 288 289 if (IS_ERR(drv_data)) 290 return PTR_ERR(drv_data); 291 292 act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid); 293 status_reg = LLCC_TRP_STATUSn(sid); 294 295 /* Set the ACTIVE trigger */ 296 act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG; 297 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 298 act_ctrl_reg_val); 299 if (ret) 300 return ret; 301 302 /* Clear the ACTIVE trigger */ 303 act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG; 304 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 305 act_ctrl_reg_val); 306 if (ret) 307 return ret; 308 309 ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg, 310 slice_status, !(slice_status & status), 311 0, LLCC_STATUS_READ_DELAY); 312 return ret; 313 } 314 315 /** 316 * llcc_slice_activate - Activate the llcc slice 317 * @desc: Pointer to llcc slice descriptor 318 * 319 * A value of zero will be returned on success and a negative errno will 320 * be returned in error cases 321 */ 322 int llcc_slice_activate(struct llcc_slice_desc *desc) 323 { 324 int ret; 325 u32 act_ctrl_val; 326 327 if (IS_ERR(drv_data)) 328 return PTR_ERR(drv_data); 329 330 if (IS_ERR_OR_NULL(desc)) 331 return -EINVAL; 332 333 mutex_lock(&drv_data->lock); 334 if (test_bit(desc->slice_id, drv_data->bitmap)) { 335 mutex_unlock(&drv_data->lock); 336 return 0; 337 } 338 339 act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT; 340 341 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 342 DEACTIVATE); 343 if (ret) { 344 mutex_unlock(&drv_data->lock); 345 return ret; 346 } 347 348 __set_bit(desc->slice_id, drv_data->bitmap); 349 mutex_unlock(&drv_data->lock); 350 351 return ret; 352 } 353 EXPORT_SYMBOL_GPL(llcc_slice_activate); 354 355 /** 356 * llcc_slice_deactivate - Deactivate the llcc slice 357 * @desc: Pointer to llcc slice descriptor 358 * 359 * A value of zero will be returned on success and a negative errno will 360 * be returned in error cases 361 */ 362 int llcc_slice_deactivate(struct llcc_slice_desc *desc) 363 { 364 u32 act_ctrl_val; 365 int ret; 366 367 if (IS_ERR(drv_data)) 368 return PTR_ERR(drv_data); 369 370 if (IS_ERR_OR_NULL(desc)) 371 return -EINVAL; 372 373 mutex_lock(&drv_data->lock); 374 if (!test_bit(desc->slice_id, drv_data->bitmap)) { 375 mutex_unlock(&drv_data->lock); 376 return 0; 377 } 378 act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT; 379 380 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 381 ACTIVATE); 382 if (ret) { 383 mutex_unlock(&drv_data->lock); 384 return ret; 385 } 386 387 __clear_bit(desc->slice_id, drv_data->bitmap); 388 mutex_unlock(&drv_data->lock); 389 390 return ret; 391 } 392 EXPORT_SYMBOL_GPL(llcc_slice_deactivate); 393 394 /** 395 * llcc_get_slice_id - return the slice id 396 * @desc: Pointer to llcc slice descriptor 397 */ 398 int llcc_get_slice_id(struct llcc_slice_desc *desc) 399 { 400 if (IS_ERR_OR_NULL(desc)) 401 return -EINVAL; 402 403 return desc->slice_id; 404 } 405 EXPORT_SYMBOL_GPL(llcc_get_slice_id); 406 407 /** 408 * llcc_get_slice_size - return the slice id 409 * @desc: Pointer to llcc slice descriptor 410 */ 411 size_t llcc_get_slice_size(struct llcc_slice_desc *desc) 412 { 413 if (IS_ERR_OR_NULL(desc)) 414 return 0; 415 416 return desc->slice_size; 417 } 418 EXPORT_SYMBOL_GPL(llcc_get_slice_size); 419 420 static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, 421 const struct qcom_llcc_config *cfg) 422 { 423 int ret; 424 u32 attr1_cfg; 425 u32 attr0_cfg; 426 u32 attr1_val; 427 u32 attr0_val; 428 u32 max_cap_cacheline; 429 struct llcc_slice_desc desc; 430 431 attr1_val = config->cache_mode; 432 attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT; 433 attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT; 434 attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT; 435 436 max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap); 437 438 /* 439 * LLCC instances can vary for each target. 440 * The SW writes to broadcast register which gets propagated 441 * to each llcc instance (llcc0,.. llccN). 442 * Since the size of the memory is divided equally amongst the 443 * llcc instances, we need to configure the max cap accordingly. 444 */ 445 max_cap_cacheline = max_cap_cacheline / drv_data->num_banks; 446 max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT; 447 attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; 448 449 attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id); 450 451 ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val); 452 if (ret) 453 return ret; 454 455 attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK; 456 attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT; 457 458 attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id); 459 460 ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val); 461 if (ret) 462 return ret; 463 464 if (cfg->need_llcc_cfg) { 465 u32 disable_cap_alloc, retain_pc; 466 467 disable_cap_alloc = config->dis_cap_alloc << config->slice_id; 468 ret = regmap_write(drv_data->bcast_regmap, 469 LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc); 470 if (ret) 471 return ret; 472 473 retain_pc = config->retain_on_pc << config->slice_id; 474 ret = regmap_write(drv_data->bcast_regmap, 475 LLCC_TRP_PCB_ACT, retain_pc); 476 if (ret) 477 return ret; 478 } 479 480 if (drv_data->major_version == 2) { 481 u32 wren; 482 483 wren = config->write_scid_en << config->slice_id; 484 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN, 485 BIT(config->slice_id), wren); 486 if (ret) 487 return ret; 488 } 489 490 if (config->activate_on_init) { 491 desc.slice_id = config->slice_id; 492 ret = llcc_slice_activate(&desc); 493 } 494 495 return ret; 496 } 497 498 static int qcom_llcc_cfg_program(struct platform_device *pdev, 499 const struct qcom_llcc_config *cfg) 500 { 501 int i; 502 u32 sz; 503 int ret = 0; 504 const struct llcc_slice_config *llcc_table; 505 506 sz = drv_data->cfg_size; 507 llcc_table = drv_data->cfg; 508 509 for (i = 0; i < sz; i++) { 510 ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg); 511 if (ret) 512 return ret; 513 } 514 515 return ret; 516 } 517 518 static int qcom_llcc_remove(struct platform_device *pdev) 519 { 520 /* Set the global pointer to a error code to avoid referencing it */ 521 drv_data = ERR_PTR(-ENODEV); 522 return 0; 523 } 524 525 static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, 526 const char *name) 527 { 528 void __iomem *base; 529 struct regmap_config llcc_regmap_config = { 530 .reg_bits = 32, 531 .reg_stride = 4, 532 .val_bits = 32, 533 .fast_io = true, 534 }; 535 536 base = devm_platform_ioremap_resource_byname(pdev, name); 537 if (IS_ERR(base)) 538 return ERR_CAST(base); 539 540 llcc_regmap_config.name = name; 541 return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config); 542 } 543 544 static int qcom_llcc_probe(struct platform_device *pdev) 545 { 546 u32 num_banks; 547 struct device *dev = &pdev->dev; 548 int ret, i; 549 struct platform_device *llcc_edac; 550 const struct qcom_llcc_config *cfg; 551 const struct llcc_slice_config *llcc_cfg; 552 u32 sz; 553 u32 version; 554 555 drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); 556 if (!drv_data) { 557 ret = -ENOMEM; 558 goto err; 559 } 560 561 drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base"); 562 if (IS_ERR(drv_data->regmap)) { 563 ret = PTR_ERR(drv_data->regmap); 564 goto err; 565 } 566 567 drv_data->bcast_regmap = 568 qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); 569 if (IS_ERR(drv_data->bcast_regmap)) { 570 ret = PTR_ERR(drv_data->bcast_regmap); 571 goto err; 572 } 573 574 /* Extract major version of the IP */ 575 ret = regmap_read(drv_data->bcast_regmap, LLCC_COMMON_HW_INFO, &version); 576 if (ret) 577 goto err; 578 579 drv_data->major_version = FIELD_GET(LLCC_MAJOR_VERSION_MASK, version); 580 581 ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0, 582 &num_banks); 583 if (ret) 584 goto err; 585 586 num_banks &= LLCC_LB_CNT_MASK; 587 num_banks >>= LLCC_LB_CNT_SHIFT; 588 drv_data->num_banks = num_banks; 589 590 cfg = of_device_get_match_data(&pdev->dev); 591 llcc_cfg = cfg->sct_data; 592 sz = cfg->size; 593 594 for (i = 0; i < sz; i++) 595 if (llcc_cfg[i].slice_id > drv_data->max_slices) 596 drv_data->max_slices = llcc_cfg[i].slice_id; 597 598 drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), 599 GFP_KERNEL); 600 if (!drv_data->offsets) { 601 ret = -ENOMEM; 602 goto err; 603 } 604 605 for (i = 0; i < num_banks; i++) 606 drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; 607 608 drv_data->bitmap = devm_kcalloc(dev, 609 BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long), 610 GFP_KERNEL); 611 if (!drv_data->bitmap) { 612 ret = -ENOMEM; 613 goto err; 614 } 615 616 drv_data->cfg = llcc_cfg; 617 drv_data->cfg_size = sz; 618 mutex_init(&drv_data->lock); 619 platform_set_drvdata(pdev, drv_data); 620 621 ret = qcom_llcc_cfg_program(pdev, cfg); 622 if (ret) 623 goto err; 624 625 drv_data->ecc_irq = platform_get_irq(pdev, 0); 626 if (drv_data->ecc_irq >= 0) { 627 llcc_edac = platform_device_register_data(&pdev->dev, 628 "qcom_llcc_edac", -1, drv_data, 629 sizeof(*drv_data)); 630 if (IS_ERR(llcc_edac)) 631 dev_err(dev, "Failed to register llcc edac driver\n"); 632 } 633 634 return 0; 635 err: 636 drv_data = ERR_PTR(-ENODEV); 637 return ret; 638 } 639 640 static const struct of_device_id qcom_llcc_of_match[] = { 641 { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, 642 { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg }, 643 { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, 644 { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg }, 645 { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, 646 { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, 647 { } 648 }; 649 650 static struct platform_driver qcom_llcc_driver = { 651 .driver = { 652 .name = "qcom-llcc", 653 .of_match_table = qcom_llcc_of_match, 654 }, 655 .probe = qcom_llcc_probe, 656 .remove = qcom_llcc_remove, 657 }; 658 module_platform_driver(qcom_llcc_driver); 659 660 MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller"); 661 MODULE_LICENSE("GPL v2"); 662