1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 *
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/bitmap.h>
9 #include <linux/bitops.h>
10 #include <linux/device.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/mutex.h>
15 #include <linux/of.h>
16 #include <linux/regmap.h>
17 #include <linux/sizes.h>
18 #include <linux/slab.h>
19 #include <linux/soc/qcom/llcc-qcom.h>
20
21 #define ACTIVATE BIT(0)
22 #define DEACTIVATE BIT(1)
23 #define ACT_CLEAR BIT(0)
24 #define ACT_COMPLETE BIT(4)
25 #define ACT_CTRL_OPCODE_ACTIVATE BIT(0)
26 #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1)
27 #define ACT_CTRL_ACT_TRIG BIT(0)
28 #define ACT_CTRL_OPCODE_SHIFT 0x01
29 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02
30 #define ATTR1_FIXED_SIZE_SHIFT 0x03
31 #define ATTR1_PRIORITY_SHIFT 0x04
32 #define ATTR1_MAX_CAP_SHIFT 0x10
33 #define ATTR0_RES_WAYS_MASK GENMASK(15, 0)
34 #define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16)
35 #define ATTR0_BONUS_WAYS_SHIFT 0x10
36 #define LLCC_STATUS_READ_DELAY 100
37
38 #define CACHE_LINE_SIZE_SHIFT 6
39
40 #define LLCC_LB_CNT_MASK GENMASK(31, 28)
41 #define LLCC_LB_CNT_SHIFT 28
42
43 #define MAX_CAP_TO_BYTES(n) (n * SZ_1K)
44 #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K)
45 #define LLCC_TRP_ACT_CLEARn(n) (8 + n * SZ_4K)
46 #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K)
47 #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n)
48 #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n)
49 #define LLCC_TRP_ATTR2_CFGn(n) (0x21100 + SZ_4 * n)
50
51 #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00
52 #define LLCC_TRP_PCB_ACT 0x21f04
53 #define LLCC_TRP_ALGO_CFG1 0x21f0c
54 #define LLCC_TRP_ALGO_CFG2 0x21f10
55 #define LLCC_TRP_ALGO_CFG3 0x21f14
56 #define LLCC_TRP_ALGO_CFG4 0x21f18
57 #define LLCC_TRP_ALGO_CFG5 0x21f1c
58 #define LLCC_TRP_WRSC_EN 0x21f20
59 #define LLCC_TRP_ALGO_CFG6 0x21f24
60 #define LLCC_TRP_ALGO_CFG7 0x21f28
61 #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c
62 #define LLCC_TRP_ALGO_CFG8 0x21f30
63
64 #define LLCC_VERSION_2_0_0_0 0x02000000
65 #define LLCC_VERSION_2_1_0_0 0x02010000
66 #define LLCC_VERSION_4_1_0_0 0x04010000
67
68 /**
69 * struct llcc_slice_config - Data associated with the llcc slice
70 * @usecase_id: Unique id for the client's use case
71 * @slice_id: llcc slice id for each client
72 * @max_cap: The maximum capacity of the cache slice provided in KB
73 * @priority: Priority of the client used to select victim line for replacement
74 * @fixed_size: Boolean indicating if the slice has a fixed capacity
75 * @bonus_ways: Bonus ways are additional ways to be used for any slice,
76 * if client ends up using more than reserved cache ways. Bonus
77 * ways are allocated only if they are not reserved for some
78 * other client.
79 * @res_ways: Reserved ways for the cache slice, the reserved ways cannot
80 * be used by any other client than the one its assigned to.
81 * @cache_mode: Each slice operates as a cache, this controls the mode of the
82 * slice: normal or TCM(Tightly Coupled Memory)
83 * @probe_target_ways: Determines what ways to probe for access hit. When
84 * configured to 1 only bonus and reserved ways are probed.
85 * When configured to 0 all ways in llcc are probed.
86 * @dis_cap_alloc: Disable capacity based allocation for a client
87 * @retain_on_pc: If this bit is set and client has maintained active vote
88 * then the ways assigned to this client are not flushed on power
89 * collapse.
90 * @activate_on_init: Activate the slice immediately after it is programmed
91 * @write_scid_en: Bit enables write cache support for a given scid.
92 * @write_scid_cacheable_en: Enables write cache cacheable support for a
93 * given scid (not supported on v2 or older hardware).
94 */
95 struct llcc_slice_config {
96 u32 usecase_id;
97 u32 slice_id;
98 u32 max_cap;
99 u32 priority;
100 bool fixed_size;
101 u32 bonus_ways;
102 u32 res_ways;
103 u32 cache_mode;
104 u32 probe_target_ways;
105 bool dis_cap_alloc;
106 bool retain_on_pc;
107 bool activate_on_init;
108 bool write_scid_en;
109 bool write_scid_cacheable_en;
110 bool stale_en;
111 bool stale_cap_en;
112 bool mru_uncap_en;
113 bool mru_rollover;
114 bool alloc_oneway_en;
115 bool ovcap_en;
116 bool ovcap_prio;
117 bool vict_prio;
118 };
119
120 struct qcom_llcc_config {
121 const struct llcc_slice_config *sct_data;
122 const u32 *reg_offset;
123 const struct llcc_edac_reg_offset *edac_reg_offset;
124 int size;
125 bool need_llcc_cfg;
126 bool no_edac;
127 };
128
129 enum llcc_reg_offset {
130 LLCC_COMMON_HW_INFO,
131 LLCC_COMMON_STATUS0,
132 };
133
134 static const struct llcc_slice_config sc7180_data[] = {
135 { LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 },
136 { LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
137 { LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
138 { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
139 };
140
141 static const struct llcc_slice_config sc7280_data[] = {
142 { LLCC_CPUSS, 1, 768, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 1, 0},
143 { LLCC_MDMHPGRW, 7, 512, 2, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
144 { LLCC_CMPT, 10, 768, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
145 { LLCC_GPUHTW, 11, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
146 { LLCC_GPU, 12, 512, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
147 { LLCC_MMUHWT, 13, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 0, 1, 0},
148 { LLCC_MDMPNG, 21, 768, 0, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
149 { LLCC_WLHW, 24, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
150 { LLCC_MODPE, 29, 64, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
151 };
152
153 static const struct llcc_slice_config sc8180x_data[] = {
154 { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1 },
155 { LLCC_VIDSC0, 2, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
156 { LLCC_VIDSC1, 3, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
157 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
158 { LLCC_MDMHPGRW, 7, 3072, 1, 1, 0x3ff, 0xc00, 0, 0, 0, 1, 0 },
159 { LLCC_MDM, 8, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
160 { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
161 { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
162 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
163 { LLCC_GPU, 12, 5120, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
164 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1 },
165 { LLCC_CMPTDMA, 15, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
166 { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
167 { LLCC_VIDFW, 17, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
168 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
169 { LLCC_MDMPNG, 21, 1024, 0, 1, 0xc, 0x0, 0, 0, 0, 1, 0 },
170 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
171 { LLCC_NPU, 23, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
172 { LLCC_WLHW, 24, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 },
173 { LLCC_MODPE, 29, 512, 1, 1, 0xc, 0x0, 0, 0, 0, 1, 0 },
174 { LLCC_APTCM, 30, 512, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 },
175 { LLCC_WRCACHE, 31, 128, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0 },
176 };
177
178 static const struct llcc_slice_config sc8280xp_data[] = {
179 { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 },
180 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
181 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
182 { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
183 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
184 { LLCC_GPU, 12, 4096, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 },
185 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
186 { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
187 { LLCC_AUDHW, 22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
188 { LLCC_DRE, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
189 { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
190 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 },
191 { LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
192 { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
193 { LLCC_CPUSS1, 3, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
194 { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
195 };
196
197 static const struct llcc_slice_config sdm845_data[] = {
198 { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 },
199 { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
200 { LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
201 { LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 },
202 { LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
203 { LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
204 { LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 },
205 { LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
206 { LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
207 { LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 },
208 { LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 },
209 { LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 },
210 { LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
211 { LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
212 { LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
213 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 },
214 { LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 },
215 { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 },
216 };
217
218 static const struct llcc_slice_config sm6350_data[] = {
219 { LLCC_CPUSS, 1, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1 },
220 { LLCC_MDM, 8, 512, 2, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
221 { LLCC_GPUHTW, 11, 256, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
222 { LLCC_GPU, 12, 512, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
223 { LLCC_MDMPNG, 21, 768, 0, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
224 { LLCC_NPU, 23, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
225 { LLCC_MODPE, 29, 64, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 },
226 };
227
228 static const struct llcc_slice_config sm7150_data[] = {
229 { LLCC_CPUSS, 1, 512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 1 },
230 { LLCC_MDM, 8, 128, 2, 0, 0xF, 0x0, 0, 0, 0, 1, 0 },
231 { LLCC_GPUHTW, 11, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 },
232 { LLCC_GPU, 12, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 },
233 { LLCC_NPU, 23, 512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 0 },
234 };
235
236 static const struct llcc_slice_config sm8150_data[] = {
237 { LLCC_CPUSS, 1, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1 },
238 { LLCC_VIDSC0, 2, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
239 { LLCC_VIDSC1, 3, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
240 { LLCC_AUDIO, 6, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
241 { LLCC_MDMHPGRW, 7, 3072, 1, 0, 0xFF, 0xF00, 0, 0, 0, 1, 0 },
242 { LLCC_MDM, 8, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
243 { LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
244 { LLCC_CMPT, 10, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
245 { LLCC_GPUHTW , 11, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
246 { LLCC_GPU, 12, 2560, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
247 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1 },
248 { LLCC_CMPTDMA, 15, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
249 { LLCC_DISP, 16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
250 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
251 { LLCC_MDMHPFX, 21, 1024, 0, 1, 0xF, 0x0, 0, 0, 0, 1, 0 },
252 { LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
253 { LLCC_NPU, 23, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
254 { LLCC_WLHW, 24, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 },
255 { LLCC_MODPE, 29, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 },
256 { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 },
257 { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 },
258 };
259
260 static const struct llcc_slice_config sm8250_data[] = {
261 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 },
262 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
263 { LLCC_AUDIO, 6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
264 { LLCC_CMPT, 10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
265 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
266 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 },
267 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
268 { LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
269 { LLCC_DISP, 16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
270 { LLCC_VIDFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
271 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
272 { LLCC_NPU, 23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
273 { LLCC_WLHW, 24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
274 { LLCC_CVP, 28, 256, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
275 { LLCC_APTCM, 30, 128, 3, 0, 0x0, 0x3, 1, 0, 0, 1, 0, 0 },
276 { LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
277 };
278
279 static const struct llcc_slice_config sm8350_data[] = {
280 { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 1 },
281 { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
282 { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
283 { LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
284 { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
285 { LLCC_CMPT, 10, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
286 { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
287 { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 },
288 { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
289 { LLCC_DISP, 16, 3072, 2, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
290 { LLCC_MDMPNG, 21, 1024, 0, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 },
291 { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
292 { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
293 { LLCC_MODPE, 29, 256, 1, 1, 0xf, 0x0, 0, 0, 0, 0, 1, 0 },
294 { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 0, 1, 0 },
295 { LLCC_WRCACHE, 31, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
296 { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
297 { LLCC_CPUSS1, 3, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
298 { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },
299 };
300
301 static const struct llcc_slice_config sm8450_data[] = {
302 {LLCC_CPUSS, 1, 3072, 1, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 },
303 {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
304 {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 },
305 {LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
306 {LLCC_MODHW, 9, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
307 {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
308 {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
309 {LLCC_GPU, 12, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 1, 0 },
310 {LLCC_MMUHWT, 13, 768, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 },
311 {LLCC_DISP, 16, 4096, 2, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
312 {LLCC_MDMPNG, 21, 1024, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 },
313 {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 },
314 {LLCC_CVP, 28, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
315 {LLCC_MODPE, 29, 64, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 },
316 {LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xF0, 1, 0, 0, 1, 0, 0, 0 },
317 {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 },
318 {LLCC_CVPFW, 17, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
319 {LLCC_CPUSS1, 3, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
320 {LLCC_CAMEXP0, 4, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
321 {LLCC_CPUMTE, 23, 256, 1, 1, 0x0FFF, 0x0, 0, 0, 0, 0, 1, 0, 0 },
322 {LLCC_CPUHWT, 5, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 },
323 {LLCC_CAMEXP1, 27, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
324 {LLCC_AENPU, 8, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 },
325 };
326
327 static const struct llcc_slice_config sm8550_data[] = {
328 {LLCC_CPUSS, 1, 5120, 1, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
329 {LLCC_VIDSC0, 2, 512, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
330 {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
331 {LLCC_MDMHPGRW, 25, 1024, 4, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
332 {LLCC_MODHW, 26, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
333 {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
334 {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
335 {LLCC_GPU, 9, 3096, 1, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, },
336 {LLCC_MMUHWT, 18, 768, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
337 {LLCC_DISP, 16, 6144, 1, 1, 0xFFFFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
338 {LLCC_MDMPNG, 27, 1024, 0, 1, 0xF00000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
339 {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
340 {LLCC_CVP, 8, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
341 {LLCC_MODPE, 29, 64, 1, 1, 0xF00000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, },
342 {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
343 {LLCC_CAMEXP0, 4, 256, 4, 1, 0xF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
344 {LLCC_CPUHWT, 5, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
345 {LLCC_CAMEXP1, 7, 3200, 3, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
346 {LLCC_CMPTHCP, 17, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
347 {LLCC_LCPDARE, 30, 128, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, },
348 {LLCC_AENPU, 3, 3072, 1, 1, 0xFE01FF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
349 {LLCC_ISLAND1, 12, 1792, 7, 1, 0xFE00, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
350 {LLCC_ISLAND4, 15, 256, 7, 1, 0x10000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
351 {LLCC_CAMEXP2, 19, 3200, 3, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
352 {LLCC_CAMEXP3, 20, 3200, 2, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
353 {LLCC_CAMEXP4, 21, 3200, 2, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
354 {LLCC_DISP_WB, 23, 1024, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
355 {LLCC_DISP_1, 24, 6144, 1, 1, 0xFFFFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
356 {LLCC_VIDVSP, 28, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
357 };
358
359 static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = {
360 .trp_ecc_error_status0 = 0x20344,
361 .trp_ecc_error_status1 = 0x20348,
362 .trp_ecc_sb_err_syn0 = 0x2304c,
363 .trp_ecc_db_err_syn0 = 0x20370,
364 .trp_ecc_error_cntr_clear = 0x20440,
365 .trp_interrupt_0_status = 0x20480,
366 .trp_interrupt_0_clear = 0x20484,
367 .trp_interrupt_0_enable = 0x20488,
368
369 /* LLCC Common registers */
370 .cmn_status0 = 0x3000c,
371 .cmn_interrupt_0_enable = 0x3001c,
372 .cmn_interrupt_2_enable = 0x3003c,
373
374 /* LLCC DRP registers */
375 .drp_ecc_error_cfg = 0x40000,
376 .drp_ecc_error_cntr_clear = 0x40004,
377 .drp_interrupt_status = 0x41000,
378 .drp_interrupt_clear = 0x41008,
379 .drp_interrupt_enable = 0x4100c,
380 .drp_ecc_error_status0 = 0x42044,
381 .drp_ecc_error_status1 = 0x42048,
382 .drp_ecc_sb_err_syn0 = 0x4204c,
383 .drp_ecc_db_err_syn0 = 0x42070,
384 };
385
386 static const struct llcc_edac_reg_offset llcc_v2_1_edac_reg_offset = {
387 .trp_ecc_error_status0 = 0x20344,
388 .trp_ecc_error_status1 = 0x20348,
389 .trp_ecc_sb_err_syn0 = 0x2034c,
390 .trp_ecc_db_err_syn0 = 0x20370,
391 .trp_ecc_error_cntr_clear = 0x20440,
392 .trp_interrupt_0_status = 0x20480,
393 .trp_interrupt_0_clear = 0x20484,
394 .trp_interrupt_0_enable = 0x20488,
395
396 /* LLCC Common registers */
397 .cmn_status0 = 0x3400c,
398 .cmn_interrupt_0_enable = 0x3401c,
399 .cmn_interrupt_2_enable = 0x3403c,
400
401 /* LLCC DRP registers */
402 .drp_ecc_error_cfg = 0x50000,
403 .drp_ecc_error_cntr_clear = 0x50004,
404 .drp_interrupt_status = 0x50020,
405 .drp_interrupt_clear = 0x50028,
406 .drp_interrupt_enable = 0x5002c,
407 .drp_ecc_error_status0 = 0x520f4,
408 .drp_ecc_error_status1 = 0x520f8,
409 .drp_ecc_sb_err_syn0 = 0x520fc,
410 .drp_ecc_db_err_syn0 = 0x52120,
411 };
412
413 /* LLCC register offset starting from v1.0.0 */
414 static const u32 llcc_v1_reg_offset[] = {
415 [LLCC_COMMON_HW_INFO] = 0x00030000,
416 [LLCC_COMMON_STATUS0] = 0x0003000c,
417 };
418
419 /* LLCC register offset starting from v2.0.1 */
420 static const u32 llcc_v2_1_reg_offset[] = {
421 [LLCC_COMMON_HW_INFO] = 0x00034000,
422 [LLCC_COMMON_STATUS0] = 0x0003400c,
423 };
424
425 static const struct qcom_llcc_config sc7180_cfg = {
426 .sct_data = sc7180_data,
427 .size = ARRAY_SIZE(sc7180_data),
428 .need_llcc_cfg = true,
429 .reg_offset = llcc_v1_reg_offset,
430 .edac_reg_offset = &llcc_v1_edac_reg_offset,
431 };
432
433 static const struct qcom_llcc_config sc7280_cfg = {
434 .sct_data = sc7280_data,
435 .size = ARRAY_SIZE(sc7280_data),
436 .need_llcc_cfg = true,
437 .reg_offset = llcc_v1_reg_offset,
438 .edac_reg_offset = &llcc_v1_edac_reg_offset,
439 };
440
441 static const struct qcom_llcc_config sc8180x_cfg = {
442 .sct_data = sc8180x_data,
443 .size = ARRAY_SIZE(sc8180x_data),
444 .need_llcc_cfg = true,
445 .reg_offset = llcc_v1_reg_offset,
446 .edac_reg_offset = &llcc_v1_edac_reg_offset,
447 };
448
449 static const struct qcom_llcc_config sc8280xp_cfg = {
450 .sct_data = sc8280xp_data,
451 .size = ARRAY_SIZE(sc8280xp_data),
452 .need_llcc_cfg = true,
453 .reg_offset = llcc_v1_reg_offset,
454 .edac_reg_offset = &llcc_v1_edac_reg_offset,
455 };
456
457 static const struct qcom_llcc_config sdm845_cfg = {
458 .sct_data = sdm845_data,
459 .size = ARRAY_SIZE(sdm845_data),
460 .need_llcc_cfg = false,
461 .reg_offset = llcc_v1_reg_offset,
462 .edac_reg_offset = &llcc_v1_edac_reg_offset,
463 .no_edac = true,
464 };
465
466 static const struct qcom_llcc_config sm6350_cfg = {
467 .sct_data = sm6350_data,
468 .size = ARRAY_SIZE(sm6350_data),
469 .need_llcc_cfg = true,
470 .reg_offset = llcc_v1_reg_offset,
471 .edac_reg_offset = &llcc_v1_edac_reg_offset,
472 };
473
474 static const struct qcom_llcc_config sm7150_cfg = {
475 .sct_data = sm7150_data,
476 .size = ARRAY_SIZE(sm7150_data),
477 .need_llcc_cfg = true,
478 .reg_offset = llcc_v1_reg_offset,
479 .edac_reg_offset = &llcc_v1_edac_reg_offset,
480 };
481
482 static const struct qcom_llcc_config sm8150_cfg = {
483 .sct_data = sm8150_data,
484 .size = ARRAY_SIZE(sm8150_data),
485 .need_llcc_cfg = true,
486 .reg_offset = llcc_v1_reg_offset,
487 .edac_reg_offset = &llcc_v1_edac_reg_offset,
488 };
489
490 static const struct qcom_llcc_config sm8250_cfg = {
491 .sct_data = sm8250_data,
492 .size = ARRAY_SIZE(sm8250_data),
493 .need_llcc_cfg = true,
494 .reg_offset = llcc_v1_reg_offset,
495 .edac_reg_offset = &llcc_v1_edac_reg_offset,
496 };
497
498 static const struct qcom_llcc_config sm8350_cfg = {
499 .sct_data = sm8350_data,
500 .size = ARRAY_SIZE(sm8350_data),
501 .need_llcc_cfg = true,
502 .reg_offset = llcc_v1_reg_offset,
503 .edac_reg_offset = &llcc_v1_edac_reg_offset,
504 };
505
506 static const struct qcom_llcc_config sm8450_cfg = {
507 .sct_data = sm8450_data,
508 .size = ARRAY_SIZE(sm8450_data),
509 .need_llcc_cfg = true,
510 .reg_offset = llcc_v2_1_reg_offset,
511 .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
512 };
513
514 static const struct qcom_llcc_config sm8550_cfg = {
515 .sct_data = sm8550_data,
516 .size = ARRAY_SIZE(sm8550_data),
517 .need_llcc_cfg = true,
518 .reg_offset = llcc_v2_1_reg_offset,
519 .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
520 };
521
522 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
523
524 /**
525 * llcc_slice_getd - get llcc slice descriptor
526 * @uid: usecase_id for the client
527 *
528 * A pointer to llcc slice descriptor will be returned on success
529 * and error pointer is returned on failure
530 */
llcc_slice_getd(u32 uid)531 struct llcc_slice_desc *llcc_slice_getd(u32 uid)
532 {
533 const struct llcc_slice_config *cfg;
534 struct llcc_slice_desc *desc;
535 u32 sz, count;
536
537 if (IS_ERR(drv_data))
538 return ERR_CAST(drv_data);
539
540 cfg = drv_data->cfg;
541 sz = drv_data->cfg_size;
542
543 for (count = 0; cfg && count < sz; count++, cfg++)
544 if (cfg->usecase_id == uid)
545 break;
546
547 if (count == sz || !cfg)
548 return ERR_PTR(-ENODEV);
549
550 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
551 if (!desc)
552 return ERR_PTR(-ENOMEM);
553
554 desc->slice_id = cfg->slice_id;
555 desc->slice_size = cfg->max_cap;
556
557 return desc;
558 }
559 EXPORT_SYMBOL_GPL(llcc_slice_getd);
560
561 /**
562 * llcc_slice_putd - llcc slice descritpor
563 * @desc: Pointer to llcc slice descriptor
564 */
llcc_slice_putd(struct llcc_slice_desc * desc)565 void llcc_slice_putd(struct llcc_slice_desc *desc)
566 {
567 if (!IS_ERR_OR_NULL(desc))
568 kfree(desc);
569 }
570 EXPORT_SYMBOL_GPL(llcc_slice_putd);
571
llcc_update_act_ctrl(u32 sid,u32 act_ctrl_reg_val,u32 status)572 static int llcc_update_act_ctrl(u32 sid,
573 u32 act_ctrl_reg_val, u32 status)
574 {
575 u32 act_ctrl_reg;
576 u32 act_clear_reg;
577 u32 status_reg;
578 u32 slice_status;
579 int ret;
580
581 if (IS_ERR(drv_data))
582 return PTR_ERR(drv_data);
583
584 act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid);
585 act_clear_reg = LLCC_TRP_ACT_CLEARn(sid);
586 status_reg = LLCC_TRP_STATUSn(sid);
587
588 /* Set the ACTIVE trigger */
589 act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG;
590 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
591 act_ctrl_reg_val);
592 if (ret)
593 return ret;
594
595 /* Clear the ACTIVE trigger */
596 act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG;
597 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
598 act_ctrl_reg_val);
599 if (ret)
600 return ret;
601
602 if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
603 ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
604 slice_status, (slice_status & ACT_COMPLETE),
605 0, LLCC_STATUS_READ_DELAY);
606 if (ret)
607 return ret;
608 }
609
610 ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
611 slice_status, !(slice_status & status),
612 0, LLCC_STATUS_READ_DELAY);
613 if (ret)
614 return ret;
615
616 if (drv_data->version >= LLCC_VERSION_4_1_0_0)
617 ret = regmap_write(drv_data->bcast_regmap, act_clear_reg,
618 ACT_CLEAR);
619
620 return ret;
621 }
622
623 /**
624 * llcc_slice_activate - Activate the llcc slice
625 * @desc: Pointer to llcc slice descriptor
626 *
627 * A value of zero will be returned on success and a negative errno will
628 * be returned in error cases
629 */
llcc_slice_activate(struct llcc_slice_desc * desc)630 int llcc_slice_activate(struct llcc_slice_desc *desc)
631 {
632 int ret;
633 u32 act_ctrl_val;
634
635 if (IS_ERR(drv_data))
636 return PTR_ERR(drv_data);
637
638 if (IS_ERR_OR_NULL(desc))
639 return -EINVAL;
640
641 mutex_lock(&drv_data->lock);
642 if (test_bit(desc->slice_id, drv_data->bitmap)) {
643 mutex_unlock(&drv_data->lock);
644 return 0;
645 }
646
647 act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT;
648
649 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
650 DEACTIVATE);
651 if (ret) {
652 mutex_unlock(&drv_data->lock);
653 return ret;
654 }
655
656 __set_bit(desc->slice_id, drv_data->bitmap);
657 mutex_unlock(&drv_data->lock);
658
659 return ret;
660 }
661 EXPORT_SYMBOL_GPL(llcc_slice_activate);
662
663 /**
664 * llcc_slice_deactivate - Deactivate the llcc slice
665 * @desc: Pointer to llcc slice descriptor
666 *
667 * A value of zero will be returned on success and a negative errno will
668 * be returned in error cases
669 */
llcc_slice_deactivate(struct llcc_slice_desc * desc)670 int llcc_slice_deactivate(struct llcc_slice_desc *desc)
671 {
672 u32 act_ctrl_val;
673 int ret;
674
675 if (IS_ERR(drv_data))
676 return PTR_ERR(drv_data);
677
678 if (IS_ERR_OR_NULL(desc))
679 return -EINVAL;
680
681 mutex_lock(&drv_data->lock);
682 if (!test_bit(desc->slice_id, drv_data->bitmap)) {
683 mutex_unlock(&drv_data->lock);
684 return 0;
685 }
686 act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT;
687
688 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
689 ACTIVATE);
690 if (ret) {
691 mutex_unlock(&drv_data->lock);
692 return ret;
693 }
694
695 __clear_bit(desc->slice_id, drv_data->bitmap);
696 mutex_unlock(&drv_data->lock);
697
698 return ret;
699 }
700 EXPORT_SYMBOL_GPL(llcc_slice_deactivate);
701
702 /**
703 * llcc_get_slice_id - return the slice id
704 * @desc: Pointer to llcc slice descriptor
705 */
llcc_get_slice_id(struct llcc_slice_desc * desc)706 int llcc_get_slice_id(struct llcc_slice_desc *desc)
707 {
708 if (IS_ERR_OR_NULL(desc))
709 return -EINVAL;
710
711 return desc->slice_id;
712 }
713 EXPORT_SYMBOL_GPL(llcc_get_slice_id);
714
715 /**
716 * llcc_get_slice_size - return the slice id
717 * @desc: Pointer to llcc slice descriptor
718 */
llcc_get_slice_size(struct llcc_slice_desc * desc)719 size_t llcc_get_slice_size(struct llcc_slice_desc *desc)
720 {
721 if (IS_ERR_OR_NULL(desc))
722 return 0;
723
724 return desc->slice_size;
725 }
726 EXPORT_SYMBOL_GPL(llcc_get_slice_size);
727
_qcom_llcc_cfg_program(const struct llcc_slice_config * config,const struct qcom_llcc_config * cfg)728 static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
729 const struct qcom_llcc_config *cfg)
730 {
731 int ret;
732 u32 attr2_cfg;
733 u32 attr1_cfg;
734 u32 attr0_cfg;
735 u32 attr2_val;
736 u32 attr1_val;
737 u32 attr0_val;
738 u32 max_cap_cacheline;
739 struct llcc_slice_desc desc;
740
741 attr1_val = config->cache_mode;
742 attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT;
743 attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT;
744 attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT;
745
746 max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap);
747
748 /*
749 * LLCC instances can vary for each target.
750 * The SW writes to broadcast register which gets propagated
751 * to each llcc instance (llcc0,.. llccN).
752 * Since the size of the memory is divided equally amongst the
753 * llcc instances, we need to configure the max cap accordingly.
754 */
755 max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
756 max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
757 attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
758
759 attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id);
760
761 ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val);
762 if (ret)
763 return ret;
764
765 if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
766 attr2_cfg = LLCC_TRP_ATTR2_CFGn(config->slice_id);
767 attr0_val = config->res_ways;
768 attr2_val = config->bonus_ways;
769 } else {
770 attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK;
771 attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
772 }
773
774 attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id);
775
776 ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val);
777 if (ret)
778 return ret;
779
780 if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
781 ret = regmap_write(drv_data->bcast_regmap, attr2_cfg, attr2_val);
782 if (ret)
783 return ret;
784 }
785
786 if (cfg->need_llcc_cfg) {
787 u32 disable_cap_alloc, retain_pc;
788
789 disable_cap_alloc = config->dis_cap_alloc << config->slice_id;
790 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_SCID_DIS_CAP_ALLOC,
791 BIT(config->slice_id), disable_cap_alloc);
792 if (ret)
793 return ret;
794
795 if (drv_data->version < LLCC_VERSION_4_1_0_0) {
796 retain_pc = config->retain_on_pc << config->slice_id;
797 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_PCB_ACT,
798 BIT(config->slice_id), retain_pc);
799 if (ret)
800 return ret;
801 }
802 }
803
804 if (drv_data->version >= LLCC_VERSION_2_0_0_0) {
805 u32 wren;
806
807 wren = config->write_scid_en << config->slice_id;
808 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN,
809 BIT(config->slice_id), wren);
810 if (ret)
811 return ret;
812 }
813
814 if (drv_data->version >= LLCC_VERSION_2_1_0_0) {
815 u32 wr_cache_en;
816
817 wr_cache_en = config->write_scid_cacheable_en << config->slice_id;
818 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_CACHEABLE_EN,
819 BIT(config->slice_id), wr_cache_en);
820 if (ret)
821 return ret;
822 }
823
824 if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
825 u32 stale_en;
826 u32 stale_cap_en;
827 u32 mru_uncap_en;
828 u32 mru_rollover;
829 u32 alloc_oneway_en;
830 u32 ovcap_en;
831 u32 ovcap_prio;
832 u32 vict_prio;
833
834 stale_en = config->stale_en << config->slice_id;
835 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG1,
836 BIT(config->slice_id), stale_en);
837 if (ret)
838 return ret;
839
840 stale_cap_en = config->stale_cap_en << config->slice_id;
841 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG2,
842 BIT(config->slice_id), stale_cap_en);
843 if (ret)
844 return ret;
845
846 mru_uncap_en = config->mru_uncap_en << config->slice_id;
847 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG3,
848 BIT(config->slice_id), mru_uncap_en);
849 if (ret)
850 return ret;
851
852 mru_rollover = config->mru_rollover << config->slice_id;
853 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG4,
854 BIT(config->slice_id), mru_rollover);
855 if (ret)
856 return ret;
857
858 alloc_oneway_en = config->alloc_oneway_en << config->slice_id;
859 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG5,
860 BIT(config->slice_id), alloc_oneway_en);
861 if (ret)
862 return ret;
863
864 ovcap_en = config->ovcap_en << config->slice_id;
865 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG6,
866 BIT(config->slice_id), ovcap_en);
867 if (ret)
868 return ret;
869
870 ovcap_prio = config->ovcap_prio << config->slice_id;
871 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG7,
872 BIT(config->slice_id), ovcap_prio);
873 if (ret)
874 return ret;
875
876 vict_prio = config->vict_prio << config->slice_id;
877 ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG8,
878 BIT(config->slice_id), vict_prio);
879 if (ret)
880 return ret;
881 }
882
883 if (config->activate_on_init) {
884 desc.slice_id = config->slice_id;
885 ret = llcc_slice_activate(&desc);
886 }
887
888 return ret;
889 }
890
qcom_llcc_cfg_program(struct platform_device * pdev,const struct qcom_llcc_config * cfg)891 static int qcom_llcc_cfg_program(struct platform_device *pdev,
892 const struct qcom_llcc_config *cfg)
893 {
894 int i;
895 u32 sz;
896 int ret = 0;
897 const struct llcc_slice_config *llcc_table;
898
899 sz = drv_data->cfg_size;
900 llcc_table = drv_data->cfg;
901
902 for (i = 0; i < sz; i++) {
903 ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg);
904 if (ret)
905 return ret;
906 }
907
908 return ret;
909 }
910
qcom_llcc_remove(struct platform_device * pdev)911 static int qcom_llcc_remove(struct platform_device *pdev)
912 {
913 /* Set the global pointer to a error code to avoid referencing it */
914 drv_data = ERR_PTR(-ENODEV);
915 return 0;
916 }
917
qcom_llcc_init_mmio(struct platform_device * pdev,u8 index,const char * name)918 static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, u8 index,
919 const char *name)
920 {
921 void __iomem *base;
922 struct regmap_config llcc_regmap_config = {
923 .reg_bits = 32,
924 .reg_stride = 4,
925 .val_bits = 32,
926 .fast_io = true,
927 };
928
929 base = devm_platform_ioremap_resource(pdev, index);
930 if (IS_ERR(base))
931 return ERR_CAST(base);
932
933 llcc_regmap_config.name = name;
934 return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config);
935 }
936
qcom_llcc_probe(struct platform_device * pdev)937 static int qcom_llcc_probe(struct platform_device *pdev)
938 {
939 u32 num_banks;
940 struct device *dev = &pdev->dev;
941 int ret, i;
942 struct platform_device *llcc_edac;
943 const struct qcom_llcc_config *cfg;
944 const struct llcc_slice_config *llcc_cfg;
945 u32 sz;
946 u32 version;
947 struct regmap *regmap;
948
949 if (!IS_ERR(drv_data))
950 return -EBUSY;
951
952 drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
953 if (!drv_data) {
954 ret = -ENOMEM;
955 goto err;
956 }
957
958 /* Initialize the first LLCC bank regmap */
959 regmap = qcom_llcc_init_mmio(pdev, 0, "llcc0_base");
960 if (IS_ERR(regmap)) {
961 ret = PTR_ERR(regmap);
962 goto err;
963 }
964
965 cfg = of_device_get_match_data(&pdev->dev);
966
967 ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks);
968 if (ret)
969 goto err;
970
971 num_banks &= LLCC_LB_CNT_MASK;
972 num_banks >>= LLCC_LB_CNT_SHIFT;
973 drv_data->num_banks = num_banks;
974
975 drv_data->regmaps = devm_kcalloc(dev, num_banks, sizeof(*drv_data->regmaps), GFP_KERNEL);
976 if (!drv_data->regmaps) {
977 ret = -ENOMEM;
978 goto err;
979 }
980
981 drv_data->regmaps[0] = regmap;
982
983 /* Initialize rest of LLCC bank regmaps */
984 for (i = 1; i < num_banks; i++) {
985 char *base = kasprintf(GFP_KERNEL, "llcc%d_base", i);
986
987 drv_data->regmaps[i] = qcom_llcc_init_mmio(pdev, i, base);
988 if (IS_ERR(drv_data->regmaps[i])) {
989 ret = PTR_ERR(drv_data->regmaps[i]);
990 kfree(base);
991 goto err;
992 }
993
994 kfree(base);
995 }
996
997 drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base");
998 if (IS_ERR(drv_data->bcast_regmap)) {
999 ret = PTR_ERR(drv_data->bcast_regmap);
1000 goto err;
1001 }
1002
1003 /* Extract version of the IP */
1004 ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO],
1005 &version);
1006 if (ret)
1007 goto err;
1008
1009 drv_data->version = version;
1010
1011 llcc_cfg = cfg->sct_data;
1012 sz = cfg->size;
1013
1014 for (i = 0; i < sz; i++)
1015 if (llcc_cfg[i].slice_id > drv_data->max_slices)
1016 drv_data->max_slices = llcc_cfg[i].slice_id;
1017
1018 drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices,
1019 GFP_KERNEL);
1020 if (!drv_data->bitmap) {
1021 ret = -ENOMEM;
1022 goto err;
1023 }
1024
1025 drv_data->cfg = llcc_cfg;
1026 drv_data->cfg_size = sz;
1027 drv_data->edac_reg_offset = cfg->edac_reg_offset;
1028 mutex_init(&drv_data->lock);
1029 platform_set_drvdata(pdev, drv_data);
1030
1031 ret = qcom_llcc_cfg_program(pdev, cfg);
1032 if (ret)
1033 goto err;
1034
1035 drv_data->ecc_irq = platform_get_irq_optional(pdev, 0);
1036
1037 /*
1038 * On some platforms, the access to EDAC registers will be locked by
1039 * the bootloader. So probing the EDAC driver will result in a crash.
1040 * Hence, disable the creation of EDAC platform device for the
1041 * problematic platforms.
1042 */
1043 if (!cfg->no_edac) {
1044 llcc_edac = platform_device_register_data(&pdev->dev,
1045 "qcom_llcc_edac", -1, drv_data,
1046 sizeof(*drv_data));
1047 if (IS_ERR(llcc_edac))
1048 dev_err(dev, "Failed to register llcc edac driver\n");
1049 }
1050
1051 return 0;
1052 err:
1053 drv_data = ERR_PTR(-ENODEV);
1054 return ret;
1055 }
1056
1057 static const struct of_device_id qcom_llcc_of_match[] = {
1058 { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
1059 { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg },
1060 { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg },
1061 { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg },
1062 { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
1063 { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg },
1064 { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfg },
1065 { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },
1066 { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg },
1067 { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg },
1068 { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg },
1069 { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfg },
1070 { }
1071 };
1072 MODULE_DEVICE_TABLE(of, qcom_llcc_of_match);
1073
1074 static struct platform_driver qcom_llcc_driver = {
1075 .driver = {
1076 .name = "qcom-llcc",
1077 .of_match_table = qcom_llcc_of_match,
1078 },
1079 .probe = qcom_llcc_probe,
1080 .remove = qcom_llcc_remove,
1081 };
1082 module_platform_driver(qcom_llcc_driver);
1083
1084 MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller");
1085 MODULE_LICENSE("GPL v2");
1086