1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/bits.h> 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/cpu.h> 11 #include <linux/cpuidle.h> 12 #include <linux/debugfs.h> 13 #include <linux/device.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/kernel.h> 17 #include <linux/kthread.h> 18 #include <linux/module.h> 19 #include <linux/mutex.h> 20 #include <linux/nvmem-consumer.h> 21 #include <linux/of_address.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_platform.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_domain.h> 26 #include <linux/pm_opp.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/reset.h> 30 #include <linux/seq_file.h> 31 #include <linux/slab.h> 32 #include <linux/spinlock.h> 33 #include <linux/thermal.h> 34 35 /* svs bank 1-line software id */ 36 #define SVSB_CPU_LITTLE BIT(0) 37 #define SVSB_CPU_BIG BIT(1) 38 #define SVSB_CCI BIT(2) 39 #define SVSB_GPU BIT(3) 40 41 /* svs bank 2-line type */ 42 #define SVSB_LOW BIT(8) 43 #define SVSB_HIGH BIT(9) 44 45 /* svs bank mode support */ 46 #define SVSB_MODE_ALL_DISABLE 0 47 #define SVSB_MODE_INIT01 BIT(1) 48 #define SVSB_MODE_INIT02 BIT(2) 49 #define SVSB_MODE_MON BIT(3) 50 51 /* svs bank volt flags */ 52 #define SVSB_INIT01_PD_REQ BIT(0) 53 #define SVSB_INIT01_VOLT_IGNORE BIT(1) 54 #define SVSB_INIT01_VOLT_INC_ONLY BIT(2) 55 #define SVSB_MON_VOLT_IGNORE BIT(16) 56 #define SVSB_REMOVE_DVTFIXED_VOLT BIT(24) 57 58 /* svs bank register fields and common configuration */ 59 #define SVSB_PTPCONFIG_DETMAX GENMASK(15, 0) 60 #define SVSB_DET_MAX FIELD_PREP(SVSB_PTPCONFIG_DETMAX, 0xffff) 61 #define SVSB_DET_WINDOW 0xa28 62 63 /* DESCHAR */ 64 #define SVSB_DESCHAR_FLD_MDES GENMASK(7, 0) 65 #define SVSB_DESCHAR_FLD_BDES GENMASK(15, 8) 66 67 /* TEMPCHAR */ 68 #define SVSB_TEMPCHAR_FLD_DVT_FIXED GENMASK(7, 0) 69 #define SVSB_TEMPCHAR_FLD_MTDES GENMASK(15, 8) 70 #define SVSB_TEMPCHAR_FLD_VCO GENMASK(23, 16) 71 72 /* DETCHAR */ 73 #define SVSB_DETCHAR_FLD_DCMDET GENMASK(7, 0) 74 #define SVSB_DETCHAR_FLD_DCBDET GENMASK(15, 8) 75 76 /* SVSEN (PTPEN) */ 77 #define SVSB_PTPEN_INIT01 BIT(0) 78 #define SVSB_PTPEN_MON BIT(1) 79 #define SVSB_PTPEN_INIT02 (SVSB_PTPEN_INIT01 | BIT(2)) 80 #define SVSB_PTPEN_OFF 0x0 81 82 /* FREQPCTS */ 83 #define SVSB_FREQPCTS_FLD_PCT0_4 GENMASK(7, 0) 84 #define SVSB_FREQPCTS_FLD_PCT1_5 GENMASK(15, 8) 85 #define SVSB_FREQPCTS_FLD_PCT2_6 GENMASK(23, 16) 86 #define SVSB_FREQPCTS_FLD_PCT3_7 GENMASK(31, 24) 87 88 /* INTSTS */ 89 #define SVSB_INTSTS_VAL_CLEAN 0x00ffffff 90 #define SVSB_INTSTS_F0_COMPLETE BIT(0) 91 #define SVSB_INTSTS_FLD_MONVOP GENMASK(23, 16) 92 #define SVSB_RUNCONFIG_DEFAULT 0x80000000 93 94 /* LIMITVALS */ 95 #define SVSB_LIMITVALS_FLD_DTLO GENMASK(7, 0) 96 #define SVSB_LIMITVALS_FLD_DTHI GENMASK(15, 8) 97 #define SVSB_LIMITVALS_FLD_VMIN GENMASK(23, 16) 98 #define SVSB_LIMITVALS_FLD_VMAX GENMASK(31, 24) 99 #define SVSB_VAL_DTHI 0x1 100 #define SVSB_VAL_DTLO 0xfe 101 102 /* INTEN */ 103 #define SVSB_INTEN_F0EN BIT(0) 104 #define SVSB_INTEN_DACK0UPEN BIT(8) 105 #define SVSB_INTEN_DC0EN BIT(9) 106 #define SVSB_INTEN_DC1EN BIT(10) 107 #define SVSB_INTEN_DACK0LOEN BIT(11) 108 #define SVSB_INTEN_INITPROD_OVF_EN BIT(12) 109 #define SVSB_INTEN_INITSUM_OVF_EN BIT(14) 110 #define SVSB_INTEN_MONVOPEN GENMASK(23, 16) 111 #define SVSB_INTEN_INIT0x (SVSB_INTEN_F0EN | SVSB_INTEN_DACK0UPEN | \ 112 SVSB_INTEN_DC0EN | SVSB_INTEN_DC1EN | \ 113 SVSB_INTEN_DACK0LOEN | \ 114 SVSB_INTEN_INITPROD_OVF_EN | \ 115 SVSB_INTEN_INITSUM_OVF_EN) 116 117 /* TSCALCS */ 118 #define SVSB_TSCALCS_FLD_MTS GENMASK(11, 0) 119 #define SVSB_TSCALCS_FLD_BTS GENMASK(23, 12) 120 121 /* INIT2VALS */ 122 #define SVSB_INIT2VALS_FLD_DCVOFFSETIN GENMASK(15, 0) 123 #define SVSB_INIT2VALS_FLD_AGEVOFFSETIN GENMASK(31, 16) 124 125 /* VOPS */ 126 #define SVSB_VOPS_FLD_VOP0_4 GENMASK(7, 0) 127 #define SVSB_VOPS_FLD_VOP1_5 GENMASK(15, 8) 128 #define SVSB_VOPS_FLD_VOP2_6 GENMASK(23, 16) 129 #define SVSB_VOPS_FLD_VOP3_7 GENMASK(31, 24) 130 131 /* svs bank related setting */ 132 #define BITS8 8 133 #define MAX_OPP_ENTRIES 16 134 #define REG_BYTES 4 135 #define SVSB_DC_SIGNED_BIT BIT(15) 136 #define SVSB_DET_CLK_EN BIT(31) 137 #define SVSB_TEMP_LOWER_BOUND 0xb2 138 #define SVSB_TEMP_UPPER_BOUND 0x64 139 140 static DEFINE_SPINLOCK(svs_lock); 141 142 #ifdef CONFIG_DEBUG_FS 143 #define debug_fops_ro(name) \ 144 static int svs_##name##_debug_open(struct inode *inode, \ 145 struct file *filp) \ 146 { \ 147 return single_open(filp, svs_##name##_debug_show, \ 148 inode->i_private); \ 149 } \ 150 static const struct file_operations svs_##name##_debug_fops = { \ 151 .owner = THIS_MODULE, \ 152 .open = svs_##name##_debug_open, \ 153 .read = seq_read, \ 154 .llseek = seq_lseek, \ 155 .release = single_release, \ 156 } 157 158 #define debug_fops_rw(name) \ 159 static int svs_##name##_debug_open(struct inode *inode, \ 160 struct file *filp) \ 161 { \ 162 return single_open(filp, svs_##name##_debug_show, \ 163 inode->i_private); \ 164 } \ 165 static const struct file_operations svs_##name##_debug_fops = { \ 166 .owner = THIS_MODULE, \ 167 .open = svs_##name##_debug_open, \ 168 .read = seq_read, \ 169 .write = svs_##name##_debug_write, \ 170 .llseek = seq_lseek, \ 171 .release = single_release, \ 172 } 173 174 #define svs_dentry_data(name) {__stringify(name), &svs_##name##_debug_fops} 175 #endif 176 177 /** 178 * enum svsb_phase - svs bank phase enumeration 179 * @SVSB_PHASE_ERROR: svs bank encounters unexpected condition 180 * @SVSB_PHASE_INIT01: svs bank basic init for data calibration 181 * @SVSB_PHASE_INIT02: svs bank can provide voltages to opp table 182 * @SVSB_PHASE_MON: svs bank can provide voltages with thermal effect 183 * @SVSB_PHASE_MAX: total number of svs bank phase (debug purpose) 184 * 185 * Each svs bank has its own independent phase and we enable each svs bank by 186 * running their phase orderly. However, when svs bank encounters unexpected 187 * condition, it will fire an irq (PHASE_ERROR) to inform svs software. 188 * 189 * svs bank general phase-enabled order: 190 * SVSB_PHASE_INIT01 -> SVSB_PHASE_INIT02 -> SVSB_PHASE_MON 191 */ 192 enum svsb_phase { 193 SVSB_PHASE_ERROR = 0, 194 SVSB_PHASE_INIT01, 195 SVSB_PHASE_INIT02, 196 SVSB_PHASE_MON, 197 SVSB_PHASE_MAX, 198 }; 199 200 enum svs_reg_index { 201 DESCHAR = 0, 202 TEMPCHAR, 203 DETCHAR, 204 AGECHAR, 205 DCCONFIG, 206 AGECONFIG, 207 FREQPCT30, 208 FREQPCT74, 209 LIMITVALS, 210 VBOOT, 211 DETWINDOW, 212 CONFIG, 213 TSCALCS, 214 RUNCONFIG, 215 SVSEN, 216 INIT2VALS, 217 DCVALUES, 218 AGEVALUES, 219 VOP30, 220 VOP74, 221 TEMP, 222 INTSTS, 223 INTSTSRAW, 224 INTEN, 225 CHKINT, 226 CHKSHIFT, 227 STATUS, 228 VDESIGN30, 229 VDESIGN74, 230 DVT30, 231 DVT74, 232 AGECOUNT, 233 SMSTATE0, 234 SMSTATE1, 235 CTL0, 236 DESDETSEC, 237 TEMPAGESEC, 238 CTRLSPARE0, 239 CTRLSPARE1, 240 CTRLSPARE2, 241 CTRLSPARE3, 242 CORESEL, 243 THERMINTST, 244 INTST, 245 THSTAGE0ST, 246 THSTAGE1ST, 247 THSTAGE2ST, 248 THAHBST0, 249 THAHBST1, 250 SPARE0, 251 SPARE1, 252 SPARE2, 253 SPARE3, 254 THSLPEVEB, 255 SVS_REG_MAX, 256 }; 257 258 static const u32 svs_regs_v2[] = { 259 [DESCHAR] = 0xc00, 260 [TEMPCHAR] = 0xc04, 261 [DETCHAR] = 0xc08, 262 [AGECHAR] = 0xc0c, 263 [DCCONFIG] = 0xc10, 264 [AGECONFIG] = 0xc14, 265 [FREQPCT30] = 0xc18, 266 [FREQPCT74] = 0xc1c, 267 [LIMITVALS] = 0xc20, 268 [VBOOT] = 0xc24, 269 [DETWINDOW] = 0xc28, 270 [CONFIG] = 0xc2c, 271 [TSCALCS] = 0xc30, 272 [RUNCONFIG] = 0xc34, 273 [SVSEN] = 0xc38, 274 [INIT2VALS] = 0xc3c, 275 [DCVALUES] = 0xc40, 276 [AGEVALUES] = 0xc44, 277 [VOP30] = 0xc48, 278 [VOP74] = 0xc4c, 279 [TEMP] = 0xc50, 280 [INTSTS] = 0xc54, 281 [INTSTSRAW] = 0xc58, 282 [INTEN] = 0xc5c, 283 [CHKINT] = 0xc60, 284 [CHKSHIFT] = 0xc64, 285 [STATUS] = 0xc68, 286 [VDESIGN30] = 0xc6c, 287 [VDESIGN74] = 0xc70, 288 [DVT30] = 0xc74, 289 [DVT74] = 0xc78, 290 [AGECOUNT] = 0xc7c, 291 [SMSTATE0] = 0xc80, 292 [SMSTATE1] = 0xc84, 293 [CTL0] = 0xc88, 294 [DESDETSEC] = 0xce0, 295 [TEMPAGESEC] = 0xce4, 296 [CTRLSPARE0] = 0xcf0, 297 [CTRLSPARE1] = 0xcf4, 298 [CTRLSPARE2] = 0xcf8, 299 [CTRLSPARE3] = 0xcfc, 300 [CORESEL] = 0xf00, 301 [THERMINTST] = 0xf04, 302 [INTST] = 0xf08, 303 [THSTAGE0ST] = 0xf0c, 304 [THSTAGE1ST] = 0xf10, 305 [THSTAGE2ST] = 0xf14, 306 [THAHBST0] = 0xf18, 307 [THAHBST1] = 0xf1c, 308 [SPARE0] = 0xf20, 309 [SPARE1] = 0xf24, 310 [SPARE2] = 0xf28, 311 [SPARE3] = 0xf2c, 312 [THSLPEVEB] = 0xf30, 313 }; 314 315 /** 316 * struct svs_platform - svs platform control 317 * @base: svs platform register base 318 * @dev: svs platform device 319 * @main_clk: main clock for svs bank 320 * @pbank: svs bank pointer needing to be protected by spin_lock section 321 * @banks: svs banks that svs platform supports 322 * @rst: svs platform reset control 323 * @efuse_max: total number of svs efuse 324 * @tefuse_max: total number of thermal efuse 325 * @regs: svs platform registers map 326 * @bank_max: total number of svs banks 327 * @efuse: svs efuse data received from NVMEM framework 328 * @tefuse: thermal efuse data received from NVMEM framework 329 */ 330 struct svs_platform { 331 void __iomem *base; 332 struct device *dev; 333 struct clk *main_clk; 334 struct svs_bank *pbank; 335 struct svs_bank *banks; 336 struct reset_control *rst; 337 size_t efuse_max; 338 size_t tefuse_max; 339 const u32 *regs; 340 u32 bank_max; 341 u32 *efuse; 342 u32 *tefuse; 343 }; 344 345 struct svs_platform_data { 346 char *name; 347 struct svs_bank *banks; 348 bool (*efuse_parsing)(struct svs_platform *svsp); 349 int (*probe)(struct svs_platform *svsp); 350 const u32 *regs; 351 u32 bank_max; 352 }; 353 354 /** 355 * struct svs_bank - svs bank representation 356 * @dev: bank device 357 * @opp_dev: device for opp table/buck control 358 * @init_completion: the timeout completion for bank init 359 * @buck: regulator used by opp_dev 360 * @tzd: thermal zone device for getting temperature 361 * @lock: mutex lock to protect voltage update process 362 * @set_freq_pct: function pointer to set bank frequency percent table 363 * @get_volts: function pointer to get bank voltages 364 * @name: bank name 365 * @buck_name: regulator name 366 * @tzone_name: thermal zone name 367 * @phase: bank current phase 368 * @volt_od: bank voltage overdrive 369 * @reg_data: bank register data in different phase for debug purpose 370 * @pm_runtime_enabled_count: bank pm runtime enabled count 371 * @mode_support: bank mode support. 372 * @freq_base: reference frequency for bank init 373 * @turn_freq_base: refenrece frequency for 2-line turn point 374 * @vboot: voltage request for bank init01 only 375 * @opp_dfreq: default opp frequency table 376 * @opp_dvolt: default opp voltage table 377 * @freq_pct: frequency percent table for bank init 378 * @volt: bank voltage table 379 * @volt_step: bank voltage step 380 * @volt_base: bank voltage base 381 * @volt_flags: bank voltage flags 382 * @vmax: bank voltage maximum 383 * @vmin: bank voltage minimum 384 * @age_config: bank age configuration 385 * @age_voffset_in: bank age voltage offset 386 * @dc_config: bank dc configuration 387 * @dc_voffset_in: bank dc voltage offset 388 * @dvt_fixed: bank dvt fixed value 389 * @vco: bank VCO value 390 * @chk_shift: bank chicken shift 391 * @core_sel: bank selection 392 * @opp_count: bank opp count 393 * @int_st: bank interrupt identification 394 * @sw_id: bank software identification 395 * @cpu_id: cpu core id for SVS CPU bank use only 396 * @ctl0: TS-x selection 397 * @temp: bank temperature 398 * @tzone_htemp: thermal zone high temperature threshold 399 * @tzone_htemp_voffset: thermal zone high temperature voltage offset 400 * @tzone_ltemp: thermal zone low temperature threshold 401 * @tzone_ltemp_voffset: thermal zone low temperature voltage offset 402 * @bts: svs efuse data 403 * @mts: svs efuse data 404 * @bdes: svs efuse data 405 * @mdes: svs efuse data 406 * @mtdes: svs efuse data 407 * @dcbdet: svs efuse data 408 * @dcmdet: svs efuse data 409 * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank 410 * @type: bank type to represent it is 2-line (high/low) bank or 1-line bank 411 * 412 * Svs bank will generate suitalbe voltages by below general math equation 413 * and provide these voltages to opp voltage table. 414 * 415 * opp_volt[i] = (volt[i] * volt_step) + volt_base; 416 */ 417 struct svs_bank { 418 struct device *dev; 419 struct device *opp_dev; 420 struct completion init_completion; 421 struct regulator *buck; 422 struct thermal_zone_device *tzd; 423 struct mutex lock; /* lock to protect voltage update process */ 424 void (*set_freq_pct)(struct svs_platform *svsp); 425 void (*get_volts)(struct svs_platform *svsp); 426 char *name; 427 char *buck_name; 428 char *tzone_name; 429 enum svsb_phase phase; 430 s32 volt_od; 431 u32 reg_data[SVSB_PHASE_MAX][SVS_REG_MAX]; 432 u32 pm_runtime_enabled_count; 433 u32 mode_support; 434 u32 freq_base; 435 u32 turn_freq_base; 436 u32 vboot; 437 u32 opp_dfreq[MAX_OPP_ENTRIES]; 438 u32 opp_dvolt[MAX_OPP_ENTRIES]; 439 u32 freq_pct[MAX_OPP_ENTRIES]; 440 u32 volt[MAX_OPP_ENTRIES]; 441 u32 volt_step; 442 u32 volt_base; 443 u32 volt_flags; 444 u32 vmax; 445 u32 vmin; 446 u32 age_config; 447 u32 age_voffset_in; 448 u32 dc_config; 449 u32 dc_voffset_in; 450 u32 dvt_fixed; 451 u32 vco; 452 u32 chk_shift; 453 u32 core_sel; 454 u32 opp_count; 455 u32 int_st; 456 u32 sw_id; 457 u32 cpu_id; 458 u32 ctl0; 459 u32 temp; 460 u32 tzone_htemp; 461 u32 tzone_htemp_voffset; 462 u32 tzone_ltemp; 463 u32 tzone_ltemp_voffset; 464 u32 bts; 465 u32 mts; 466 u32 bdes; 467 u32 mdes; 468 u32 mtdes; 469 u32 dcbdet; 470 u32 dcmdet; 471 u32 turn_pt; 472 u32 type; 473 }; 474 475 static u32 percent(u32 numerator, u32 denominator) 476 { 477 /* If not divide 1000, "numerator * 100" will have data overflow. */ 478 numerator /= 1000; 479 denominator /= 1000; 480 481 return DIV_ROUND_UP(numerator * 100, denominator); 482 } 483 484 static u32 svs_readl_relaxed(struct svs_platform *svsp, enum svs_reg_index rg_i) 485 { 486 return readl_relaxed(svsp->base + svsp->regs[rg_i]); 487 } 488 489 static void svs_writel_relaxed(struct svs_platform *svsp, u32 val, 490 enum svs_reg_index rg_i) 491 { 492 writel_relaxed(val, svsp->base + svsp->regs[rg_i]); 493 } 494 495 static void svs_switch_bank(struct svs_platform *svsp) 496 { 497 struct svs_bank *svsb = svsp->pbank; 498 499 svs_writel_relaxed(svsp, svsb->core_sel, CORESEL); 500 } 501 502 static u32 svs_bank_volt_to_opp_volt(u32 svsb_volt, u32 svsb_volt_step, 503 u32 svsb_volt_base) 504 { 505 return (svsb_volt * svsb_volt_step) + svsb_volt_base; 506 } 507 508 static u32 svs_opp_volt_to_bank_volt(u32 opp_u_volt, u32 svsb_volt_step, 509 u32 svsb_volt_base) 510 { 511 return (opp_u_volt - svsb_volt_base) / svsb_volt_step; 512 } 513 514 static int svs_sync_bank_volts_from_opp(struct svs_bank *svsb) 515 { 516 struct dev_pm_opp *opp; 517 u32 i, opp_u_volt; 518 519 for (i = 0; i < svsb->opp_count; i++) { 520 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, 521 svsb->opp_dfreq[i], 522 true); 523 if (IS_ERR(opp)) { 524 dev_err(svsb->dev, "cannot find freq = %u (%ld)\n", 525 svsb->opp_dfreq[i], PTR_ERR(opp)); 526 return PTR_ERR(opp); 527 } 528 529 opp_u_volt = dev_pm_opp_get_voltage(opp); 530 svsb->volt[i] = svs_opp_volt_to_bank_volt(opp_u_volt, 531 svsb->volt_step, 532 svsb->volt_base); 533 dev_pm_opp_put(opp); 534 } 535 536 return 0; 537 } 538 539 static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) 540 { 541 int ret = -EPERM, tzone_temp = 0; 542 u32 i, svsb_volt, opp_volt, temp_voffset = 0, opp_start, opp_stop; 543 544 mutex_lock(&svsb->lock); 545 546 /* 547 * 2-line bank updates its corresponding opp volts. 548 * 1-line bank updates all opp volts. 549 */ 550 if (svsb->type == SVSB_HIGH) { 551 opp_start = 0; 552 opp_stop = svsb->turn_pt; 553 } else if (svsb->type == SVSB_LOW) { 554 opp_start = svsb->turn_pt; 555 opp_stop = svsb->opp_count; 556 } else { 557 opp_start = 0; 558 opp_stop = svsb->opp_count; 559 } 560 561 /* Get thermal effect */ 562 if (!IS_ERR_OR_NULL(svsb->tzd)) { 563 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); 564 if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND && 565 svsb->temp < SVSB_TEMP_LOWER_BOUND)) { 566 dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n", 567 svsb->tzone_name, ret, svsb->temp); 568 svsb->phase = SVSB_PHASE_ERROR; 569 } 570 571 if (tzone_temp >= svsb->tzone_htemp) 572 temp_voffset += svsb->tzone_htemp_voffset; 573 else if (tzone_temp <= svsb->tzone_ltemp) 574 temp_voffset += svsb->tzone_ltemp_voffset; 575 576 /* 2-line bank update all opp volts when running mon mode */ 577 if (svsb->phase == SVSB_PHASE_MON && (svsb->type == SVSB_HIGH || 578 svsb->type == SVSB_LOW)) { 579 opp_start = 0; 580 opp_stop = svsb->opp_count; 581 } 582 } 583 584 /* vmin <= svsb_volt (opp_volt) <= default opp voltage */ 585 for (i = opp_start; i < opp_stop; i++) { 586 switch (svsb->phase) { 587 case SVSB_PHASE_ERROR: 588 opp_volt = svsb->opp_dvolt[i]; 589 break; 590 case SVSB_PHASE_INIT01: 591 /* do nothing */ 592 goto unlock_mutex; 593 case SVSB_PHASE_INIT02: 594 case SVSB_PHASE_MON: 595 svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin); 596 opp_volt = svs_bank_volt_to_opp_volt(svsb_volt, 597 svsb->volt_step, 598 svsb->volt_base); 599 break; 600 default: 601 dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase); 602 ret = -EINVAL; 603 goto unlock_mutex; 604 } 605 606 opp_volt = min(opp_volt, svsb->opp_dvolt[i]); 607 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev, 608 svsb->opp_dfreq[i], 609 opp_volt, opp_volt, 610 svsb->opp_dvolt[i]); 611 if (ret) { 612 dev_err(svsb->dev, "set %uuV fail: %d\n", 613 opp_volt, ret); 614 goto unlock_mutex; 615 } 616 } 617 618 unlock_mutex: 619 mutex_unlock(&svsb->lock); 620 621 return ret; 622 } 623 624 static void svs_bank_disable_and_restore_default_volts(struct svs_platform *svsp, 625 struct svs_bank *svsb) 626 { 627 unsigned long flags; 628 629 if (svsb->mode_support == SVSB_MODE_ALL_DISABLE) 630 return; 631 632 spin_lock_irqsave(&svs_lock, flags); 633 svsp->pbank = svsb; 634 svs_switch_bank(svsp); 635 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); 636 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); 637 spin_unlock_irqrestore(&svs_lock, flags); 638 639 svsb->phase = SVSB_PHASE_ERROR; 640 svs_adjust_pm_opp_volts(svsb); 641 } 642 643 #ifdef CONFIG_DEBUG_FS 644 static int svs_dump_debug_show(struct seq_file *m, void *p) 645 { 646 struct svs_platform *svsp = (struct svs_platform *)m->private; 647 struct svs_bank *svsb; 648 unsigned long svs_reg_addr; 649 u32 idx, i, j, bank_id; 650 651 for (i = 0; i < svsp->efuse_max; i++) 652 if (svsp->efuse && svsp->efuse[i]) 653 seq_printf(m, "M_HW_RES%d = 0x%08x\n", 654 i, svsp->efuse[i]); 655 656 for (i = 0; i < svsp->tefuse_max; i++) 657 if (svsp->tefuse) 658 seq_printf(m, "THERMAL_EFUSE%d = 0x%08x\n", 659 i, svsp->tefuse[i]); 660 661 for (bank_id = 0, idx = 0; idx < svsp->bank_max; idx++, bank_id++) { 662 svsb = &svsp->banks[idx]; 663 664 for (i = SVSB_PHASE_INIT01; i <= SVSB_PHASE_MON; i++) { 665 seq_printf(m, "Bank_number = %u\n", bank_id); 666 667 if (i == SVSB_PHASE_INIT01 || i == SVSB_PHASE_INIT02) 668 seq_printf(m, "mode = init%d\n", i); 669 else if (i == SVSB_PHASE_MON) 670 seq_puts(m, "mode = mon\n"); 671 else 672 seq_puts(m, "mode = error\n"); 673 674 for (j = DESCHAR; j < SVS_REG_MAX; j++) { 675 svs_reg_addr = (unsigned long)(svsp->base + 676 svsp->regs[j]); 677 seq_printf(m, "0x%08lx = 0x%08x\n", 678 svs_reg_addr, svsb->reg_data[i][j]); 679 } 680 } 681 } 682 683 return 0; 684 } 685 686 debug_fops_ro(dump); 687 688 static int svs_enable_debug_show(struct seq_file *m, void *v) 689 { 690 struct svs_bank *svsb = (struct svs_bank *)m->private; 691 692 switch (svsb->phase) { 693 case SVSB_PHASE_ERROR: 694 seq_puts(m, "disabled\n"); 695 break; 696 case SVSB_PHASE_INIT01: 697 seq_puts(m, "init1\n"); 698 break; 699 case SVSB_PHASE_INIT02: 700 seq_puts(m, "init2\n"); 701 break; 702 case SVSB_PHASE_MON: 703 seq_puts(m, "mon mode\n"); 704 break; 705 default: 706 seq_puts(m, "unknown\n"); 707 break; 708 } 709 710 return 0; 711 } 712 713 static ssize_t svs_enable_debug_write(struct file *filp, 714 const char __user *buffer, 715 size_t count, loff_t *pos) 716 { 717 struct svs_bank *svsb = file_inode(filp)->i_private; 718 struct svs_platform *svsp = dev_get_drvdata(svsb->dev); 719 int enabled, ret; 720 char *buf = NULL; 721 722 if (count >= PAGE_SIZE) 723 return -EINVAL; 724 725 buf = (char *)memdup_user_nul(buffer, count); 726 if (IS_ERR(buf)) 727 return PTR_ERR(buf); 728 729 ret = kstrtoint(buf, 10, &enabled); 730 if (ret) 731 return ret; 732 733 if (!enabled) { 734 svs_bank_disable_and_restore_default_volts(svsp, svsb); 735 svsb->mode_support = SVSB_MODE_ALL_DISABLE; 736 } 737 738 kfree(buf); 739 740 return count; 741 } 742 743 debug_fops_rw(enable); 744 745 static int svs_status_debug_show(struct seq_file *m, void *v) 746 { 747 struct svs_bank *svsb = (struct svs_bank *)m->private; 748 struct dev_pm_opp *opp; 749 int tzone_temp = 0, ret; 750 u32 i; 751 752 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); 753 if (ret) 754 seq_printf(m, "%s: temperature ignore, turn_pt = %u\n", 755 svsb->name, svsb->turn_pt); 756 else 757 seq_printf(m, "%s: temperature = %d, turn_pt = %u\n", 758 svsb->name, tzone_temp, svsb->turn_pt); 759 760 for (i = 0; i < svsb->opp_count; i++) { 761 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, 762 svsb->opp_dfreq[i], true); 763 if (IS_ERR(opp)) { 764 seq_printf(m, "%s: cannot find freq = %u (%ld)\n", 765 svsb->name, svsb->opp_dfreq[i], 766 PTR_ERR(opp)); 767 return PTR_ERR(opp); 768 } 769 770 seq_printf(m, "opp_freq[%02u]: %u, opp_volt[%02u]: %lu, ", 771 i, svsb->opp_dfreq[i], i, 772 dev_pm_opp_get_voltage(opp)); 773 seq_printf(m, "svsb_volt[%02u]: 0x%x, freq_pct[%02u]: %u\n", 774 i, svsb->volt[i], i, svsb->freq_pct[i]); 775 dev_pm_opp_put(opp); 776 } 777 778 return 0; 779 } 780 781 debug_fops_ro(status); 782 783 static int svs_create_debug_cmds(struct svs_platform *svsp) 784 { 785 struct svs_bank *svsb; 786 struct dentry *svs_dir, *svsb_dir, *file_entry; 787 const char *d = "/sys/kernel/debug/svs"; 788 u32 i, idx; 789 790 struct svs_dentry { 791 const char *name; 792 const struct file_operations *fops; 793 }; 794 795 struct svs_dentry svs_entries[] = { 796 svs_dentry_data(dump), 797 }; 798 799 struct svs_dentry svsb_entries[] = { 800 svs_dentry_data(enable), 801 svs_dentry_data(status), 802 }; 803 804 svs_dir = debugfs_create_dir("svs", NULL); 805 if (IS_ERR(svs_dir)) { 806 dev_err(svsp->dev, "cannot create %s: %ld\n", 807 d, PTR_ERR(svs_dir)); 808 return PTR_ERR(svs_dir); 809 } 810 811 for (i = 0; i < ARRAY_SIZE(svs_entries); i++) { 812 file_entry = debugfs_create_file(svs_entries[i].name, 0664, 813 svs_dir, svsp, 814 svs_entries[i].fops); 815 if (IS_ERR(file_entry)) { 816 dev_err(svsp->dev, "cannot create %s/%s: %ld\n", 817 d, svs_entries[i].name, PTR_ERR(file_entry)); 818 return PTR_ERR(file_entry); 819 } 820 } 821 822 for (idx = 0; idx < svsp->bank_max; idx++) { 823 svsb = &svsp->banks[idx]; 824 825 if (svsb->mode_support == SVSB_MODE_ALL_DISABLE) 826 continue; 827 828 svsb_dir = debugfs_create_dir(svsb->name, svs_dir); 829 if (IS_ERR(svsb_dir)) { 830 dev_err(svsp->dev, "cannot create %s/%s: %ld\n", 831 d, svsb->name, PTR_ERR(svsb_dir)); 832 return PTR_ERR(svsb_dir); 833 } 834 835 for (i = 0; i < ARRAY_SIZE(svsb_entries); i++) { 836 file_entry = debugfs_create_file(svsb_entries[i].name, 837 0664, svsb_dir, svsb, 838 svsb_entries[i].fops); 839 if (IS_ERR(file_entry)) { 840 dev_err(svsp->dev, "no %s/%s/%s?: %ld\n", 841 d, svsb->name, svsb_entries[i].name, 842 PTR_ERR(file_entry)); 843 return PTR_ERR(file_entry); 844 } 845 } 846 } 847 848 return 0; 849 } 850 #endif /* CONFIG_DEBUG_FS */ 851 852 static u32 interpolate(u32 f0, u32 f1, u32 v0, u32 v1, u32 fx) 853 { 854 u32 vx; 855 856 if (v0 == v1 || f0 == f1) 857 return v0; 858 859 /* *100 to have decimal fraction factor */ 860 vx = (v0 * 100) - ((((v0 - v1) * 100) / (f0 - f1)) * (f0 - fx)); 861 862 return DIV_ROUND_UP(vx, 100); 863 } 864 865 static void svs_get_bank_volts_v3(struct svs_platform *svsp) 866 { 867 struct svs_bank *svsb = svsp->pbank; 868 u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt; 869 u32 b_sft, shift_byte = 0, opp_start = 0, opp_stop = 0; 870 u32 middle_index = (svsb->opp_count / 2); 871 872 if (svsb->phase == SVSB_PHASE_MON && 873 svsb->volt_flags & SVSB_MON_VOLT_IGNORE) 874 return; 875 876 vop74 = svs_readl_relaxed(svsp, VOP74); 877 vop30 = svs_readl_relaxed(svsp, VOP30); 878 879 /* Target is to set svsb->volt[] by algorithm */ 880 if (turn_pt < middle_index) { 881 if (svsb->type == SVSB_HIGH) { 882 /* volt[0] ~ volt[turn_pt - 1] */ 883 for (i = 0; i < turn_pt; i++) { 884 b_sft = BITS8 * (shift_byte % REG_BYTES); 885 vop = (shift_byte < REG_BYTES) ? &vop30 : 886 &vop74; 887 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); 888 shift_byte++; 889 } 890 } else if (svsb->type == SVSB_LOW) { 891 /* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */ 892 j = svsb->opp_count - 7; 893 svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); 894 shift_byte++; 895 for (i = j; i < svsb->opp_count; i++) { 896 b_sft = BITS8 * (shift_byte % REG_BYTES); 897 vop = (shift_byte < REG_BYTES) ? &vop30 : 898 &vop74; 899 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); 900 shift_byte++; 901 } 902 903 /* volt[turn_pt + 1] ~ volt[j - 1] by interpolate */ 904 for (i = turn_pt + 1; i < j; i++) 905 svsb->volt[i] = interpolate(svsb->freq_pct[turn_pt], 906 svsb->freq_pct[j], 907 svsb->volt[turn_pt], 908 svsb->volt[j], 909 svsb->freq_pct[i]); 910 } 911 } else { 912 if (svsb->type == SVSB_HIGH) { 913 /* volt[0] + volt[j] ~ volt[turn_pt - 1] */ 914 j = turn_pt - 7; 915 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); 916 shift_byte++; 917 for (i = j; i < turn_pt; i++) { 918 b_sft = BITS8 * (shift_byte % REG_BYTES); 919 vop = (shift_byte < REG_BYTES) ? &vop30 : 920 &vop74; 921 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); 922 shift_byte++; 923 } 924 925 /* volt[1] ~ volt[j - 1] by interpolate */ 926 for (i = 1; i < j; i++) 927 svsb->volt[i] = interpolate(svsb->freq_pct[0], 928 svsb->freq_pct[j], 929 svsb->volt[0], 930 svsb->volt[j], 931 svsb->freq_pct[i]); 932 } else if (svsb->type == SVSB_LOW) { 933 /* volt[turn_pt] ~ volt[opp_count - 1] */ 934 for (i = turn_pt; i < svsb->opp_count; i++) { 935 b_sft = BITS8 * (shift_byte % REG_BYTES); 936 vop = (shift_byte < REG_BYTES) ? &vop30 : 937 &vop74; 938 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); 939 shift_byte++; 940 } 941 } 942 } 943 944 if (svsb->type == SVSB_HIGH) { 945 opp_start = 0; 946 opp_stop = svsb->turn_pt; 947 } else if (svsb->type == SVSB_LOW) { 948 opp_start = svsb->turn_pt; 949 opp_stop = svsb->opp_count; 950 } 951 952 for (i = opp_start; i < opp_stop; i++) 953 if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT) 954 svsb->volt[i] -= svsb->dvt_fixed; 955 } 956 957 static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) 958 { 959 struct svs_bank *svsb = svsp->pbank; 960 u32 i, j, *freq_pct, freq_pct74 = 0, freq_pct30 = 0; 961 u32 b_sft, shift_byte = 0, turn_pt; 962 u32 middle_index = (svsb->opp_count / 2); 963 964 for (i = 0; i < svsb->opp_count; i++) { 965 if (svsb->opp_dfreq[i] <= svsb->turn_freq_base) { 966 svsb->turn_pt = i; 967 break; 968 } 969 } 970 971 turn_pt = svsb->turn_pt; 972 973 /* Target is to fill out freq_pct74 / freq_pct30 by algorithm */ 974 if (turn_pt < middle_index) { 975 if (svsb->type == SVSB_HIGH) { 976 /* 977 * If we don't handle this situation, 978 * SVSB_HIGH's FREQPCT74 / FREQPCT30 would keep "0" 979 * and this leads SVSB_LOW to work abnormally. 980 */ 981 if (turn_pt == 0) 982 freq_pct30 = svsb->freq_pct[0]; 983 984 /* freq_pct[0] ~ freq_pct[turn_pt - 1] */ 985 for (i = 0; i < turn_pt; i++) { 986 b_sft = BITS8 * (shift_byte % REG_BYTES); 987 freq_pct = (shift_byte < REG_BYTES) ? 988 &freq_pct30 : &freq_pct74; 989 *freq_pct |= (svsb->freq_pct[i] << b_sft); 990 shift_byte++; 991 } 992 } else if (svsb->type == SVSB_LOW) { 993 /* 994 * freq_pct[turn_pt] + 995 * freq_pct[opp_count - 7] ~ freq_pct[opp_count -1] 996 */ 997 freq_pct30 = svsb->freq_pct[turn_pt]; 998 shift_byte++; 999 j = svsb->opp_count - 7; 1000 for (i = j; i < svsb->opp_count; i++) { 1001 b_sft = BITS8 * (shift_byte % REG_BYTES); 1002 freq_pct = (shift_byte < REG_BYTES) ? 1003 &freq_pct30 : &freq_pct74; 1004 *freq_pct |= (svsb->freq_pct[i] << b_sft); 1005 shift_byte++; 1006 } 1007 } 1008 } else { 1009 if (svsb->type == SVSB_HIGH) { 1010 /* 1011 * freq_pct[0] + 1012 * freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1] 1013 */ 1014 freq_pct30 = svsb->freq_pct[0]; 1015 shift_byte++; 1016 j = turn_pt - 7; 1017 for (i = j; i < turn_pt; i++) { 1018 b_sft = BITS8 * (shift_byte % REG_BYTES); 1019 freq_pct = (shift_byte < REG_BYTES) ? 1020 &freq_pct30 : &freq_pct74; 1021 *freq_pct |= (svsb->freq_pct[i] << b_sft); 1022 shift_byte++; 1023 } 1024 } else if (svsb->type == SVSB_LOW) { 1025 /* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */ 1026 for (i = turn_pt; i < svsb->opp_count; i++) { 1027 b_sft = BITS8 * (shift_byte % REG_BYTES); 1028 freq_pct = (shift_byte < REG_BYTES) ? 1029 &freq_pct30 : &freq_pct74; 1030 *freq_pct |= (svsb->freq_pct[i] << b_sft); 1031 shift_byte++; 1032 } 1033 } 1034 } 1035 1036 svs_writel_relaxed(svsp, freq_pct74, FREQPCT74); 1037 svs_writel_relaxed(svsp, freq_pct30, FREQPCT30); 1038 } 1039 1040 static void svs_get_bank_volts_v2(struct svs_platform *svsp) 1041 { 1042 struct svs_bank *svsb = svsp->pbank; 1043 u32 temp, i; 1044 1045 temp = svs_readl_relaxed(svsp, VOP74); 1046 svsb->volt[14] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp); 1047 svsb->volt[12] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp); 1048 svsb->volt[10] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp); 1049 svsb->volt[8] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp); 1050 1051 temp = svs_readl_relaxed(svsp, VOP30); 1052 svsb->volt[6] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp); 1053 svsb->volt[4] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp); 1054 svsb->volt[2] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp); 1055 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp); 1056 1057 for (i = 0; i <= 12; i += 2) 1058 svsb->volt[i + 1] = interpolate(svsb->freq_pct[i], 1059 svsb->freq_pct[i + 2], 1060 svsb->volt[i], 1061 svsb->volt[i + 2], 1062 svsb->freq_pct[i + 1]); 1063 1064 svsb->volt[15] = interpolate(svsb->freq_pct[12], 1065 svsb->freq_pct[14], 1066 svsb->volt[12], 1067 svsb->volt[14], 1068 svsb->freq_pct[15]); 1069 1070 for (i = 0; i < svsb->opp_count; i++) 1071 svsb->volt[i] += svsb->volt_od; 1072 } 1073 1074 static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp) 1075 { 1076 struct svs_bank *svsb = svsp->pbank; 1077 u32 freqpct74_val, freqpct30_val; 1078 1079 freqpct74_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[8]) | 1080 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[10]) | 1081 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[12]) | 1082 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[14]); 1083 1084 freqpct30_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[0]) | 1085 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[2]) | 1086 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[4]) | 1087 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[6]); 1088 1089 svs_writel_relaxed(svsp, freqpct74_val, FREQPCT74); 1090 svs_writel_relaxed(svsp, freqpct30_val, FREQPCT30); 1091 } 1092 1093 static void svs_set_bank_phase(struct svs_platform *svsp, 1094 enum svsb_phase target_phase) 1095 { 1096 struct svs_bank *svsb = svsp->pbank; 1097 u32 des_char, temp_char, det_char, limit_vals, init2vals, ts_calcs; 1098 1099 svs_switch_bank(svsp); 1100 1101 des_char = FIELD_PREP(SVSB_DESCHAR_FLD_BDES, svsb->bdes) | 1102 FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes); 1103 svs_writel_relaxed(svsp, des_char, DESCHAR); 1104 1105 temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, svsb->vco) | 1106 FIELD_PREP(SVSB_TEMPCHAR_FLD_MTDES, svsb->mtdes) | 1107 FIELD_PREP(SVSB_TEMPCHAR_FLD_DVT_FIXED, svsb->dvt_fixed); 1108 svs_writel_relaxed(svsp, temp_char, TEMPCHAR); 1109 1110 det_char = FIELD_PREP(SVSB_DETCHAR_FLD_DCBDET, svsb->dcbdet) | 1111 FIELD_PREP(SVSB_DETCHAR_FLD_DCMDET, svsb->dcmdet); 1112 svs_writel_relaxed(svsp, det_char, DETCHAR); 1113 1114 svs_writel_relaxed(svsp, svsb->dc_config, DCCONFIG); 1115 svs_writel_relaxed(svsp, svsb->age_config, AGECONFIG); 1116 svs_writel_relaxed(svsp, SVSB_RUNCONFIG_DEFAULT, RUNCONFIG); 1117 1118 svsb->set_freq_pct(svsp); 1119 1120 limit_vals = FIELD_PREP(SVSB_LIMITVALS_FLD_DTLO, SVSB_VAL_DTLO) | 1121 FIELD_PREP(SVSB_LIMITVALS_FLD_DTHI, SVSB_VAL_DTHI) | 1122 FIELD_PREP(SVSB_LIMITVALS_FLD_VMIN, svsb->vmin) | 1123 FIELD_PREP(SVSB_LIMITVALS_FLD_VMAX, svsb->vmax); 1124 svs_writel_relaxed(svsp, limit_vals, LIMITVALS); 1125 1126 svs_writel_relaxed(svsp, SVSB_DET_WINDOW, DETWINDOW); 1127 svs_writel_relaxed(svsp, SVSB_DET_MAX, CONFIG); 1128 svs_writel_relaxed(svsp, svsb->chk_shift, CHKSHIFT); 1129 svs_writel_relaxed(svsp, svsb->ctl0, CTL0); 1130 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); 1131 1132 switch (target_phase) { 1133 case SVSB_PHASE_INIT01: 1134 svs_writel_relaxed(svsp, svsb->vboot, VBOOT); 1135 svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN); 1136 svs_writel_relaxed(svsp, SVSB_PTPEN_INIT01, SVSEN); 1137 break; 1138 case SVSB_PHASE_INIT02: 1139 init2vals = FIELD_PREP(SVSB_INIT2VALS_FLD_AGEVOFFSETIN, svsb->age_voffset_in) | 1140 FIELD_PREP(SVSB_INIT2VALS_FLD_DCVOFFSETIN, svsb->dc_voffset_in); 1141 svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN); 1142 svs_writel_relaxed(svsp, init2vals, INIT2VALS); 1143 svs_writel_relaxed(svsp, SVSB_PTPEN_INIT02, SVSEN); 1144 break; 1145 case SVSB_PHASE_MON: 1146 ts_calcs = FIELD_PREP(SVSB_TSCALCS_FLD_BTS, svsb->bts) | 1147 FIELD_PREP(SVSB_TSCALCS_FLD_MTS, svsb->mts); 1148 svs_writel_relaxed(svsp, ts_calcs, TSCALCS); 1149 svs_writel_relaxed(svsp, SVSB_INTEN_MONVOPEN, INTEN); 1150 svs_writel_relaxed(svsp, SVSB_PTPEN_MON, SVSEN); 1151 break; 1152 default: 1153 dev_err(svsb->dev, "requested unknown target phase: %u\n", 1154 target_phase); 1155 break; 1156 } 1157 } 1158 1159 static inline void svs_save_bank_register_data(struct svs_platform *svsp, 1160 enum svsb_phase phase) 1161 { 1162 struct svs_bank *svsb = svsp->pbank; 1163 enum svs_reg_index rg_i; 1164 1165 for (rg_i = DESCHAR; rg_i < SVS_REG_MAX; rg_i++) 1166 svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i); 1167 } 1168 1169 static inline void svs_error_isr_handler(struct svs_platform *svsp) 1170 { 1171 struct svs_bank *svsb = svsp->pbank; 1172 1173 dev_err(svsb->dev, "%s: CORESEL = 0x%08x\n", 1174 __func__, svs_readl_relaxed(svsp, CORESEL)); 1175 dev_err(svsb->dev, "SVSEN = 0x%08x, INTSTS = 0x%08x\n", 1176 svs_readl_relaxed(svsp, SVSEN), 1177 svs_readl_relaxed(svsp, INTSTS)); 1178 dev_err(svsb->dev, "SMSTATE0 = 0x%08x, SMSTATE1 = 0x%08x\n", 1179 svs_readl_relaxed(svsp, SMSTATE0), 1180 svs_readl_relaxed(svsp, SMSTATE1)); 1181 dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP)); 1182 1183 svs_save_bank_register_data(svsp, SVSB_PHASE_ERROR); 1184 1185 svsb->phase = SVSB_PHASE_ERROR; 1186 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); 1187 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); 1188 } 1189 1190 static inline void svs_init01_isr_handler(struct svs_platform *svsp) 1191 { 1192 struct svs_bank *svsb = svsp->pbank; 1193 1194 dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n", 1195 __func__, svs_readl_relaxed(svsp, VDESIGN74), 1196 svs_readl_relaxed(svsp, VDESIGN30), 1197 svs_readl_relaxed(svsp, DCVALUES)); 1198 1199 svs_save_bank_register_data(svsp, SVSB_PHASE_INIT01); 1200 1201 svsb->phase = SVSB_PHASE_INIT01; 1202 svsb->dc_voffset_in = ~(svs_readl_relaxed(svsp, DCVALUES) & 1203 GENMASK(15, 0)) + 1; 1204 if (svsb->volt_flags & SVSB_INIT01_VOLT_IGNORE || 1205 (svsb->dc_voffset_in & SVSB_DC_SIGNED_BIT && 1206 svsb->volt_flags & SVSB_INIT01_VOLT_INC_ONLY)) 1207 svsb->dc_voffset_in = 0; 1208 1209 svsb->age_voffset_in = svs_readl_relaxed(svsp, AGEVALUES) & 1210 GENMASK(15, 0); 1211 1212 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); 1213 svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS); 1214 svsb->core_sel &= ~SVSB_DET_CLK_EN; 1215 } 1216 1217 static inline void svs_init02_isr_handler(struct svs_platform *svsp) 1218 { 1219 struct svs_bank *svsb = svsp->pbank; 1220 1221 dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n", 1222 __func__, svs_readl_relaxed(svsp, VOP74), 1223 svs_readl_relaxed(svsp, VOP30), 1224 svs_readl_relaxed(svsp, DCVALUES)); 1225 1226 svs_save_bank_register_data(svsp, SVSB_PHASE_INIT02); 1227 1228 svsb->phase = SVSB_PHASE_INIT02; 1229 svsb->get_volts(svsp); 1230 1231 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); 1232 svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS); 1233 } 1234 1235 static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp) 1236 { 1237 struct svs_bank *svsb = svsp->pbank; 1238 1239 svs_save_bank_register_data(svsp, SVSB_PHASE_MON); 1240 1241 svsb->phase = SVSB_PHASE_MON; 1242 svsb->get_volts(svsp); 1243 1244 svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0); 1245 svs_writel_relaxed(svsp, SVSB_INTSTS_FLD_MONVOP, INTSTS); 1246 } 1247 1248 static irqreturn_t svs_isr(int irq, void *data) 1249 { 1250 struct svs_platform *svsp = data; 1251 struct svs_bank *svsb = NULL; 1252 unsigned long flags; 1253 u32 idx, int_sts, svs_en; 1254 1255 for (idx = 0; idx < svsp->bank_max; idx++) { 1256 svsb = &svsp->banks[idx]; 1257 WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name); 1258 1259 spin_lock_irqsave(&svs_lock, flags); 1260 svsp->pbank = svsb; 1261 1262 /* Find out which svs bank fires interrupt */ 1263 if (svsb->int_st & svs_readl_relaxed(svsp, INTST)) { 1264 spin_unlock_irqrestore(&svs_lock, flags); 1265 continue; 1266 } 1267 1268 svs_switch_bank(svsp); 1269 int_sts = svs_readl_relaxed(svsp, INTSTS); 1270 svs_en = svs_readl_relaxed(svsp, SVSEN); 1271 1272 if (int_sts == SVSB_INTSTS_F0_COMPLETE && 1273 svs_en == SVSB_PTPEN_INIT01) 1274 svs_init01_isr_handler(svsp); 1275 else if (int_sts == SVSB_INTSTS_F0_COMPLETE && 1276 svs_en == SVSB_PTPEN_INIT02) 1277 svs_init02_isr_handler(svsp); 1278 else if (int_sts & SVSB_INTSTS_FLD_MONVOP) 1279 svs_mon_mode_isr_handler(svsp); 1280 else 1281 svs_error_isr_handler(svsp); 1282 1283 spin_unlock_irqrestore(&svs_lock, flags); 1284 break; 1285 } 1286 1287 svs_adjust_pm_opp_volts(svsb); 1288 1289 if (svsb->phase == SVSB_PHASE_INIT01 || 1290 svsb->phase == SVSB_PHASE_INIT02) 1291 complete(&svsb->init_completion); 1292 1293 return IRQ_HANDLED; 1294 } 1295 1296 static int svs_init01(struct svs_platform *svsp) 1297 { 1298 struct svs_bank *svsb; 1299 unsigned long flags, time_left; 1300 bool search_done; 1301 int ret = 0, r; 1302 u32 opp_freq, opp_vboot, buck_volt, idx, i; 1303 1304 /* Keep CPUs' core power on for svs_init01 initialization */ 1305 cpuidle_pause_and_lock(); 1306 1307 /* Svs bank init01 preparation - power enable */ 1308 for (idx = 0; idx < svsp->bank_max; idx++) { 1309 svsb = &svsp->banks[idx]; 1310 1311 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1312 continue; 1313 1314 ret = regulator_enable(svsb->buck); 1315 if (ret) { 1316 dev_err(svsb->dev, "%s enable fail: %d\n", 1317 svsb->buck_name, ret); 1318 goto svs_init01_resume_cpuidle; 1319 } 1320 1321 /* Some buck doesn't support mode change. Show fail msg only */ 1322 ret = regulator_set_mode(svsb->buck, REGULATOR_MODE_FAST); 1323 if (ret) 1324 dev_notice(svsb->dev, "set fast mode fail: %d\n", ret); 1325 1326 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) { 1327 if (!pm_runtime_enabled(svsb->opp_dev)) { 1328 pm_runtime_enable(svsb->opp_dev); 1329 svsb->pm_runtime_enabled_count++; 1330 } 1331 1332 ret = pm_runtime_resume_and_get(svsb->opp_dev); 1333 if (ret < 0) { 1334 dev_err(svsb->dev, "mtcmos on fail: %d\n", ret); 1335 goto svs_init01_resume_cpuidle; 1336 } 1337 } 1338 } 1339 1340 /* 1341 * Svs bank init01 preparation - vboot voltage adjustment 1342 * Sometimes two svs banks use the same buck. Therefore, 1343 * we have to set each svs bank to target voltage(vboot) first. 1344 */ 1345 for (idx = 0; idx < svsp->bank_max; idx++) { 1346 svsb = &svsp->banks[idx]; 1347 1348 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1349 continue; 1350 1351 /* 1352 * Find the fastest freq that can be run at vboot and 1353 * fix to that freq until svs_init01 is done. 1354 */ 1355 search_done = false; 1356 opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, 1357 svsb->volt_step, 1358 svsb->volt_base); 1359 1360 for (i = 0; i < svsb->opp_count; i++) { 1361 opp_freq = svsb->opp_dfreq[i]; 1362 if (!search_done && svsb->opp_dvolt[i] <= opp_vboot) { 1363 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev, 1364 opp_freq, 1365 opp_vboot, 1366 opp_vboot, 1367 opp_vboot); 1368 if (ret) { 1369 dev_err(svsb->dev, 1370 "set opp %uuV vboot fail: %d\n", 1371 opp_vboot, ret); 1372 goto svs_init01_finish; 1373 } 1374 1375 search_done = true; 1376 } else { 1377 ret = dev_pm_opp_disable(svsb->opp_dev, 1378 svsb->opp_dfreq[i]); 1379 if (ret) { 1380 dev_err(svsb->dev, 1381 "opp %uHz disable fail: %d\n", 1382 svsb->opp_dfreq[i], ret); 1383 goto svs_init01_finish; 1384 } 1385 } 1386 } 1387 } 1388 1389 /* Svs bank init01 begins */ 1390 for (idx = 0; idx < svsp->bank_max; idx++) { 1391 svsb = &svsp->banks[idx]; 1392 1393 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1394 continue; 1395 1396 opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, 1397 svsb->volt_step, 1398 svsb->volt_base); 1399 1400 buck_volt = regulator_get_voltage(svsb->buck); 1401 if (buck_volt != opp_vboot) { 1402 dev_err(svsb->dev, 1403 "buck voltage: %uuV, expected vboot: %uuV\n", 1404 buck_volt, opp_vboot); 1405 ret = -EPERM; 1406 goto svs_init01_finish; 1407 } 1408 1409 spin_lock_irqsave(&svs_lock, flags); 1410 svsp->pbank = svsb; 1411 svs_set_bank_phase(svsp, SVSB_PHASE_INIT01); 1412 spin_unlock_irqrestore(&svs_lock, flags); 1413 1414 time_left = wait_for_completion_timeout(&svsb->init_completion, 1415 msecs_to_jiffies(5000)); 1416 if (!time_left) { 1417 dev_err(svsb->dev, "init01 completion timeout\n"); 1418 ret = -EBUSY; 1419 goto svs_init01_finish; 1420 } 1421 } 1422 1423 svs_init01_finish: 1424 for (idx = 0; idx < svsp->bank_max; idx++) { 1425 svsb = &svsp->banks[idx]; 1426 1427 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1428 continue; 1429 1430 for (i = 0; i < svsb->opp_count; i++) { 1431 r = dev_pm_opp_enable(svsb->opp_dev, 1432 svsb->opp_dfreq[i]); 1433 if (r) 1434 dev_err(svsb->dev, "opp %uHz enable fail: %d\n", 1435 svsb->opp_dfreq[i], r); 1436 } 1437 1438 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) { 1439 r = pm_runtime_put_sync(svsb->opp_dev); 1440 if (r) 1441 dev_err(svsb->dev, "mtcmos off fail: %d\n", r); 1442 1443 if (svsb->pm_runtime_enabled_count > 0) { 1444 pm_runtime_disable(svsb->opp_dev); 1445 svsb->pm_runtime_enabled_count--; 1446 } 1447 } 1448 1449 r = regulator_set_mode(svsb->buck, REGULATOR_MODE_NORMAL); 1450 if (r) 1451 dev_notice(svsb->dev, "set normal mode fail: %d\n", r); 1452 1453 r = regulator_disable(svsb->buck); 1454 if (r) 1455 dev_err(svsb->dev, "%s disable fail: %d\n", 1456 svsb->buck_name, r); 1457 } 1458 1459 svs_init01_resume_cpuidle: 1460 cpuidle_resume_and_unlock(); 1461 1462 return ret; 1463 } 1464 1465 static int svs_init02(struct svs_platform *svsp) 1466 { 1467 struct svs_bank *svsb; 1468 unsigned long flags, time_left; 1469 int ret; 1470 u32 idx; 1471 1472 for (idx = 0; idx < svsp->bank_max; idx++) { 1473 svsb = &svsp->banks[idx]; 1474 1475 if (!(svsb->mode_support & SVSB_MODE_INIT02)) 1476 continue; 1477 1478 reinit_completion(&svsb->init_completion); 1479 spin_lock_irqsave(&svs_lock, flags); 1480 svsp->pbank = svsb; 1481 svs_set_bank_phase(svsp, SVSB_PHASE_INIT02); 1482 spin_unlock_irqrestore(&svs_lock, flags); 1483 1484 time_left = wait_for_completion_timeout(&svsb->init_completion, 1485 msecs_to_jiffies(5000)); 1486 if (!time_left) { 1487 dev_err(svsb->dev, "init02 completion timeout\n"); 1488 ret = -EBUSY; 1489 goto out_of_init02; 1490 } 1491 } 1492 1493 /* 1494 * 2-line high/low bank update its corresponding opp voltages only. 1495 * Therefore, we sync voltages from opp for high/low bank voltages 1496 * consistency. 1497 */ 1498 for (idx = 0; idx < svsp->bank_max; idx++) { 1499 svsb = &svsp->banks[idx]; 1500 1501 if (!(svsb->mode_support & SVSB_MODE_INIT02)) 1502 continue; 1503 1504 if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) { 1505 if (svs_sync_bank_volts_from_opp(svsb)) { 1506 dev_err(svsb->dev, "sync volt fail\n"); 1507 ret = -EPERM; 1508 goto out_of_init02; 1509 } 1510 } 1511 } 1512 1513 return 0; 1514 1515 out_of_init02: 1516 for (idx = 0; idx < svsp->bank_max; idx++) { 1517 svsb = &svsp->banks[idx]; 1518 svs_bank_disable_and_restore_default_volts(svsp, svsb); 1519 } 1520 1521 return ret; 1522 } 1523 1524 static void svs_mon_mode(struct svs_platform *svsp) 1525 { 1526 struct svs_bank *svsb; 1527 unsigned long flags; 1528 u32 idx; 1529 1530 for (idx = 0; idx < svsp->bank_max; idx++) { 1531 svsb = &svsp->banks[idx]; 1532 1533 if (!(svsb->mode_support & SVSB_MODE_MON)) 1534 continue; 1535 1536 spin_lock_irqsave(&svs_lock, flags); 1537 svsp->pbank = svsb; 1538 svs_set_bank_phase(svsp, SVSB_PHASE_MON); 1539 spin_unlock_irqrestore(&svs_lock, flags); 1540 } 1541 } 1542 1543 static int svs_start(struct svs_platform *svsp) 1544 { 1545 int ret; 1546 1547 ret = svs_init01(svsp); 1548 if (ret) 1549 return ret; 1550 1551 ret = svs_init02(svsp); 1552 if (ret) 1553 return ret; 1554 1555 svs_mon_mode(svsp); 1556 1557 return 0; 1558 } 1559 1560 static int svs_suspend(struct device *dev) 1561 { 1562 struct svs_platform *svsp = dev_get_drvdata(dev); 1563 struct svs_bank *svsb; 1564 int ret; 1565 u32 idx; 1566 1567 for (idx = 0; idx < svsp->bank_max; idx++) { 1568 svsb = &svsp->banks[idx]; 1569 svs_bank_disable_and_restore_default_volts(svsp, svsb); 1570 } 1571 1572 ret = reset_control_assert(svsp->rst); 1573 if (ret) { 1574 dev_err(svsp->dev, "cannot assert reset %d\n", ret); 1575 return ret; 1576 } 1577 1578 clk_disable_unprepare(svsp->main_clk); 1579 1580 return 0; 1581 } 1582 1583 static int svs_resume(struct device *dev) 1584 { 1585 struct svs_platform *svsp = dev_get_drvdata(dev); 1586 int ret; 1587 1588 ret = clk_prepare_enable(svsp->main_clk); 1589 if (ret) { 1590 dev_err(svsp->dev, "cannot enable main_clk, disable svs\n"); 1591 return ret; 1592 } 1593 1594 ret = reset_control_deassert(svsp->rst); 1595 if (ret) { 1596 dev_err(svsp->dev, "cannot deassert reset %d\n", ret); 1597 goto out_of_resume; 1598 } 1599 1600 ret = svs_init02(svsp); 1601 if (ret) 1602 goto svs_resume_reset_assert; 1603 1604 svs_mon_mode(svsp); 1605 1606 return 0; 1607 1608 svs_resume_reset_assert: 1609 dev_err(svsp->dev, "assert reset: %d\n", 1610 reset_control_assert(svsp->rst)); 1611 1612 out_of_resume: 1613 clk_disable_unprepare(svsp->main_clk); 1614 return ret; 1615 } 1616 1617 static int svs_bank_resource_setup(struct svs_platform *svsp) 1618 { 1619 struct svs_bank *svsb; 1620 struct dev_pm_opp *opp; 1621 unsigned long freq; 1622 int count, ret; 1623 u32 idx, i; 1624 1625 dev_set_drvdata(svsp->dev, svsp); 1626 1627 for (idx = 0; idx < svsp->bank_max; idx++) { 1628 svsb = &svsp->banks[idx]; 1629 1630 switch (svsb->sw_id) { 1631 case SVSB_CPU_LITTLE: 1632 svsb->name = "SVSB_CPU_LITTLE"; 1633 break; 1634 case SVSB_CPU_BIG: 1635 svsb->name = "SVSB_CPU_BIG"; 1636 break; 1637 case SVSB_CCI: 1638 svsb->name = "SVSB_CCI"; 1639 break; 1640 case SVSB_GPU: 1641 if (svsb->type == SVSB_HIGH) 1642 svsb->name = "SVSB_GPU_HIGH"; 1643 else if (svsb->type == SVSB_LOW) 1644 svsb->name = "SVSB_GPU_LOW"; 1645 else 1646 svsb->name = "SVSB_GPU"; 1647 break; 1648 default: 1649 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 1650 return -EINVAL; 1651 } 1652 1653 svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev), 1654 GFP_KERNEL); 1655 if (!svsb->dev) 1656 return -ENOMEM; 1657 1658 ret = dev_set_name(svsb->dev, "%s", svsb->name); 1659 if (ret) 1660 return ret; 1661 1662 dev_set_drvdata(svsb->dev, svsp); 1663 1664 ret = devm_pm_opp_of_add_table(svsb->opp_dev); 1665 if (ret) { 1666 dev_err(svsb->dev, "add opp table fail: %d\n", ret); 1667 return ret; 1668 } 1669 1670 mutex_init(&svsb->lock); 1671 init_completion(&svsb->init_completion); 1672 1673 if (svsb->mode_support & SVSB_MODE_INIT01) { 1674 svsb->buck = devm_regulator_get_optional(svsb->opp_dev, 1675 svsb->buck_name); 1676 if (IS_ERR(svsb->buck)) { 1677 dev_err(svsb->dev, "cannot get \"%s-supply\"\n", 1678 svsb->buck_name); 1679 return PTR_ERR(svsb->buck); 1680 } 1681 } 1682 1683 if (!IS_ERR_OR_NULL(svsb->tzone_name)) { 1684 svsb->tzd = thermal_zone_get_zone_by_name(svsb->tzone_name); 1685 if (IS_ERR(svsb->tzd)) { 1686 dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n", 1687 svsb->tzone_name); 1688 return PTR_ERR(svsb->tzd); 1689 } 1690 } 1691 1692 count = dev_pm_opp_get_opp_count(svsb->opp_dev); 1693 if (svsb->opp_count != count) { 1694 dev_err(svsb->dev, 1695 "opp_count not \"%u\" but get \"%d\"?\n", 1696 svsb->opp_count, count); 1697 return count; 1698 } 1699 1700 for (i = 0, freq = U32_MAX; i < svsb->opp_count; i++, freq--) { 1701 opp = dev_pm_opp_find_freq_floor(svsb->opp_dev, &freq); 1702 if (IS_ERR(opp)) { 1703 dev_err(svsb->dev, "cannot find freq = %ld\n", 1704 PTR_ERR(opp)); 1705 return PTR_ERR(opp); 1706 } 1707 1708 svsb->opp_dfreq[i] = freq; 1709 svsb->opp_dvolt[i] = dev_pm_opp_get_voltage(opp); 1710 svsb->freq_pct[i] = percent(svsb->opp_dfreq[i], 1711 svsb->freq_base); 1712 dev_pm_opp_put(opp); 1713 } 1714 } 1715 1716 return 0; 1717 } 1718 1719 static int svs_get_efuse_data(struct svs_platform *svsp, 1720 const char *nvmem_cell_name, 1721 u32 **svsp_efuse, size_t *svsp_efuse_max) 1722 { 1723 struct nvmem_cell *cell; 1724 1725 cell = nvmem_cell_get(svsp->dev, nvmem_cell_name); 1726 if (IS_ERR(cell)) { 1727 dev_err(svsp->dev, "no \"%s\"? %ld\n", 1728 nvmem_cell_name, PTR_ERR(cell)); 1729 return PTR_ERR(cell); 1730 } 1731 1732 *svsp_efuse = nvmem_cell_read(cell, svsp_efuse_max); 1733 if (IS_ERR(*svsp_efuse)) { 1734 dev_err(svsp->dev, "cannot read \"%s\" efuse: %ld\n", 1735 nvmem_cell_name, PTR_ERR(*svsp_efuse)); 1736 nvmem_cell_put(cell); 1737 return PTR_ERR(*svsp_efuse); 1738 } 1739 1740 *svsp_efuse_max /= sizeof(u32); 1741 nvmem_cell_put(cell); 1742 1743 return 0; 1744 } 1745 1746 static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) 1747 { 1748 struct svs_bank *svsb; 1749 u32 idx, i, vmin, golden_temp; 1750 int ret; 1751 1752 for (i = 0; i < svsp->efuse_max; i++) 1753 if (svsp->efuse[i]) 1754 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", 1755 i, svsp->efuse[i]); 1756 1757 if (!svsp->efuse[9]) { 1758 dev_notice(svsp->dev, "svs_efuse[9] = 0x0?\n"); 1759 return false; 1760 } 1761 1762 /* Svs efuse parsing */ 1763 vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0); 1764 1765 for (idx = 0; idx < svsp->bank_max; idx++) { 1766 svsb = &svsp->banks[idx]; 1767 1768 if (vmin == 0x1) 1769 svsb->vmin = 0x1e; 1770 1771 if (svsb->type == SVSB_LOW) { 1772 svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); 1773 svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); 1774 svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); 1775 svsb->dcbdet = (svsp->efuse[17]) & GENMASK(7, 0); 1776 svsb->dcmdet = (svsp->efuse[17] >> 8) & GENMASK(7, 0); 1777 } else if (svsb->type == SVSB_HIGH) { 1778 svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); 1779 svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); 1780 svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); 1781 svsb->dcbdet = (svsp->efuse[17] >> 16) & GENMASK(7, 0); 1782 svsb->dcmdet = (svsp->efuse[17] >> 24) & GENMASK(7, 0); 1783 } 1784 1785 svsb->vmax += svsb->dvt_fixed; 1786 } 1787 1788 ret = svs_get_efuse_data(svsp, "t-calibration-data", 1789 &svsp->tefuse, &svsp->tefuse_max); 1790 if (ret) 1791 return false; 1792 1793 for (i = 0; i < svsp->tefuse_max; i++) 1794 if (svsp->tefuse[i] != 0) 1795 break; 1796 1797 if (i == svsp->tefuse_max) 1798 golden_temp = 50; /* All thermal efuse data are 0 */ 1799 else 1800 golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); 1801 1802 for (idx = 0; idx < svsp->bank_max; idx++) { 1803 svsb = &svsp->banks[idx]; 1804 svsb->mts = 500; 1805 svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; 1806 } 1807 1808 return true; 1809 } 1810 1811 static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) 1812 { 1813 struct svs_bank *svsb; 1814 int format[6], x_roomt[6], o_vtsmcu[5], o_vtsabb, tb_roomt = 0; 1815 int adc_ge_t, adc_oe_t, ge, oe, gain, degc_cali, adc_cali_en_t; 1816 int o_slope, o_slope_sign, ts_id; 1817 u32 idx, i, ft_pgm, mts, temp0, temp1, temp2; 1818 int ret; 1819 1820 for (i = 0; i < svsp->efuse_max; i++) 1821 if (svsp->efuse[i]) 1822 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", 1823 i, svsp->efuse[i]); 1824 1825 if (!svsp->efuse[2]) { 1826 dev_notice(svsp->dev, "svs_efuse[2] = 0x0?\n"); 1827 return false; 1828 } 1829 1830 /* Svs efuse parsing */ 1831 ft_pgm = (svsp->efuse[0] >> 4) & GENMASK(3, 0); 1832 1833 for (idx = 0; idx < svsp->bank_max; idx++) { 1834 svsb = &svsp->banks[idx]; 1835 1836 if (ft_pgm <= 1) 1837 svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; 1838 1839 switch (svsb->sw_id) { 1840 case SVSB_CPU_LITTLE: 1841 svsb->bdes = svsp->efuse[16] & GENMASK(7, 0); 1842 svsb->mdes = (svsp->efuse[16] >> 8) & GENMASK(7, 0); 1843 svsb->dcbdet = (svsp->efuse[16] >> 16) & GENMASK(7, 0); 1844 svsb->dcmdet = (svsp->efuse[16] >> 24) & GENMASK(7, 0); 1845 svsb->mtdes = (svsp->efuse[17] >> 16) & GENMASK(7, 0); 1846 1847 if (ft_pgm <= 3) 1848 svsb->volt_od += 10; 1849 else 1850 svsb->volt_od += 2; 1851 break; 1852 case SVSB_CPU_BIG: 1853 svsb->bdes = svsp->efuse[18] & GENMASK(7, 0); 1854 svsb->mdes = (svsp->efuse[18] >> 8) & GENMASK(7, 0); 1855 svsb->dcbdet = (svsp->efuse[18] >> 16) & GENMASK(7, 0); 1856 svsb->dcmdet = (svsp->efuse[18] >> 24) & GENMASK(7, 0); 1857 svsb->mtdes = svsp->efuse[17] & GENMASK(7, 0); 1858 1859 if (ft_pgm <= 3) 1860 svsb->volt_od += 15; 1861 else 1862 svsb->volt_od += 12; 1863 break; 1864 case SVSB_CCI: 1865 svsb->bdes = svsp->efuse[4] & GENMASK(7, 0); 1866 svsb->mdes = (svsp->efuse[4] >> 8) & GENMASK(7, 0); 1867 svsb->dcbdet = (svsp->efuse[4] >> 16) & GENMASK(7, 0); 1868 svsb->dcmdet = (svsp->efuse[4] >> 24) & GENMASK(7, 0); 1869 svsb->mtdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); 1870 1871 if (ft_pgm <= 3) 1872 svsb->volt_od += 10; 1873 else 1874 svsb->volt_od += 2; 1875 break; 1876 case SVSB_GPU: 1877 svsb->bdes = svsp->efuse[6] & GENMASK(7, 0); 1878 svsb->mdes = (svsp->efuse[6] >> 8) & GENMASK(7, 0); 1879 svsb->dcbdet = (svsp->efuse[6] >> 16) & GENMASK(7, 0); 1880 svsb->dcmdet = (svsp->efuse[6] >> 24) & GENMASK(7, 0); 1881 svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); 1882 1883 if (ft_pgm >= 2) { 1884 svsb->freq_base = 800000000; /* 800MHz */ 1885 svsb->dvt_fixed = 2; 1886 } 1887 break; 1888 default: 1889 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 1890 return false; 1891 } 1892 } 1893 1894 ret = svs_get_efuse_data(svsp, "t-calibration-data", 1895 &svsp->tefuse, &svsp->tefuse_max); 1896 if (ret) 1897 return false; 1898 1899 /* Thermal efuse parsing */ 1900 adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0); 1901 adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0); 1902 1903 o_vtsmcu[0] = (svsp->tefuse[0] >> 17) & GENMASK(8, 0); 1904 o_vtsmcu[1] = (svsp->tefuse[0] >> 8) & GENMASK(8, 0); 1905 o_vtsmcu[2] = svsp->tefuse[1] & GENMASK(8, 0); 1906 o_vtsmcu[3] = (svsp->tefuse[2] >> 23) & GENMASK(8, 0); 1907 o_vtsmcu[4] = (svsp->tefuse[2] >> 5) & GENMASK(8, 0); 1908 o_vtsabb = (svsp->tefuse[2] >> 14) & GENMASK(8, 0); 1909 1910 degc_cali = (svsp->tefuse[0] >> 1) & GENMASK(5, 0); 1911 adc_cali_en_t = svsp->tefuse[0] & BIT(0); 1912 o_slope_sign = (svsp->tefuse[0] >> 7) & BIT(0); 1913 1914 ts_id = (svsp->tefuse[1] >> 9) & BIT(0); 1915 if (!ts_id) { 1916 o_slope = 1534; 1917 } else { 1918 o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0); 1919 if (!o_slope_sign) 1920 o_slope = 1534 + o_slope * 10; 1921 else 1922 o_slope = 1534 - o_slope * 10; 1923 } 1924 1925 if (adc_cali_en_t == 0 || 1926 adc_ge_t < 265 || adc_ge_t > 758 || 1927 adc_oe_t < 265 || adc_oe_t > 758 || 1928 o_vtsmcu[0] < -8 || o_vtsmcu[0] > 484 || 1929 o_vtsmcu[1] < -8 || o_vtsmcu[1] > 484 || 1930 o_vtsmcu[2] < -8 || o_vtsmcu[2] > 484 || 1931 o_vtsmcu[3] < -8 || o_vtsmcu[3] > 484 || 1932 o_vtsmcu[4] < -8 || o_vtsmcu[4] > 484 || 1933 o_vtsabb < -8 || o_vtsabb > 484 || 1934 degc_cali < 1 || degc_cali > 63) { 1935 dev_err(svsp->dev, "bad thermal efuse, no mon mode\n"); 1936 goto remove_mt8183_svsb_mon_mode; 1937 } 1938 1939 ge = ((adc_ge_t - 512) * 10000) / 4096; 1940 oe = (adc_oe_t - 512); 1941 gain = (10000 + ge); 1942 1943 format[0] = (o_vtsmcu[0] + 3350 - oe); 1944 format[1] = (o_vtsmcu[1] + 3350 - oe); 1945 format[2] = (o_vtsmcu[2] + 3350 - oe); 1946 format[3] = (o_vtsmcu[3] + 3350 - oe); 1947 format[4] = (o_vtsmcu[4] + 3350 - oe); 1948 format[5] = (o_vtsabb + 3350 - oe); 1949 1950 for (i = 0; i < 6; i++) 1951 x_roomt[i] = (((format[i] * 10000) / 4096) * 10000) / gain; 1952 1953 temp0 = (10000 * 100000 / gain) * 15 / 18; 1954 mts = (temp0 * 10) / o_slope; 1955 1956 for (idx = 0; idx < svsp->bank_max; idx++) { 1957 svsb = &svsp->banks[idx]; 1958 svsb->mts = mts; 1959 1960 switch (svsb->sw_id) { 1961 case SVSB_CPU_LITTLE: 1962 tb_roomt = x_roomt[3]; 1963 break; 1964 case SVSB_CPU_BIG: 1965 tb_roomt = x_roomt[4]; 1966 break; 1967 case SVSB_CCI: 1968 tb_roomt = x_roomt[3]; 1969 break; 1970 case SVSB_GPU: 1971 tb_roomt = x_roomt[1]; 1972 break; 1973 default: 1974 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 1975 goto remove_mt8183_svsb_mon_mode; 1976 } 1977 1978 temp0 = (degc_cali * 10 / 2); 1979 temp1 = ((10000 * 100000 / 4096 / gain) * 1980 oe + tb_roomt * 10) * 15 / 18; 1981 temp2 = temp1 * 100 / o_slope; 1982 1983 svsb->bts = (temp0 + temp2 - 250) * 4 / 10; 1984 } 1985 1986 return true; 1987 1988 remove_mt8183_svsb_mon_mode: 1989 for (idx = 0; idx < svsp->bank_max; idx++) { 1990 svsb = &svsp->banks[idx]; 1991 svsb->mode_support &= ~SVSB_MODE_MON; 1992 } 1993 1994 return true; 1995 } 1996 1997 static struct device *svs_get_subsys_device(struct svs_platform *svsp, 1998 const char *node_name) 1999 { 2000 struct platform_device *pdev; 2001 struct device_node *np; 2002 2003 np = of_find_node_by_name(NULL, node_name); 2004 if (!np) { 2005 dev_err(svsp->dev, "cannot find %s node\n", node_name); 2006 return ERR_PTR(-ENODEV); 2007 } 2008 2009 pdev = of_find_device_by_node(np); 2010 if (!pdev) { 2011 of_node_put(np); 2012 dev_err(svsp->dev, "cannot find pdev by %s\n", node_name); 2013 return ERR_PTR(-ENXIO); 2014 } 2015 2016 of_node_put(np); 2017 2018 return &pdev->dev; 2019 } 2020 2021 static struct device *svs_add_device_link(struct svs_platform *svsp, 2022 const char *node_name) 2023 { 2024 struct device *dev; 2025 struct device_link *sup_link; 2026 2027 dev = svs_get_subsys_device(svsp, node_name); 2028 if (IS_ERR(dev)) 2029 return dev; 2030 2031 sup_link = device_link_add(svsp->dev, dev, 2032 DL_FLAG_AUTOREMOVE_CONSUMER); 2033 if (!sup_link) { 2034 dev_err(svsp->dev, "sup_link is NULL\n"); 2035 return ERR_PTR(-EINVAL); 2036 } 2037 2038 if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND) 2039 return ERR_PTR(-EPROBE_DEFER); 2040 2041 return dev; 2042 } 2043 2044 static int svs_mt8192_platform_probe(struct svs_platform *svsp) 2045 { 2046 struct device *dev; 2047 struct svs_bank *svsb; 2048 u32 idx; 2049 2050 svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst"); 2051 if (IS_ERR(svsp->rst)) 2052 return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), 2053 "cannot get svs reset control\n"); 2054 2055 dev = svs_add_device_link(svsp, "lvts"); 2056 if (IS_ERR(dev)) 2057 return dev_err_probe(svsp->dev, PTR_ERR(dev), 2058 "failed to get lvts device\n"); 2059 2060 for (idx = 0; idx < svsp->bank_max; idx++) { 2061 svsb = &svsp->banks[idx]; 2062 2063 if (svsb->type == SVSB_HIGH) 2064 svsb->opp_dev = svs_add_device_link(svsp, "gpu"); 2065 else if (svsb->type == SVSB_LOW) 2066 svsb->opp_dev = svs_get_subsys_device(svsp, "gpu"); 2067 2068 if (IS_ERR(svsb->opp_dev)) 2069 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), 2070 "failed to get OPP device for bank %d\n", 2071 idx); 2072 } 2073 2074 return 0; 2075 } 2076 2077 static int svs_mt8183_platform_probe(struct svs_platform *svsp) 2078 { 2079 struct device *dev; 2080 struct svs_bank *svsb; 2081 u32 idx; 2082 2083 dev = svs_add_device_link(svsp, "thermal"); 2084 if (IS_ERR(dev)) 2085 return dev_err_probe(svsp->dev, PTR_ERR(dev), 2086 "failed to get thermal device\n"); 2087 2088 for (idx = 0; idx < svsp->bank_max; idx++) { 2089 svsb = &svsp->banks[idx]; 2090 2091 switch (svsb->sw_id) { 2092 case SVSB_CPU_LITTLE: 2093 case SVSB_CPU_BIG: 2094 svsb->opp_dev = get_cpu_device(svsb->cpu_id); 2095 break; 2096 case SVSB_CCI: 2097 svsb->opp_dev = svs_add_device_link(svsp, "cci"); 2098 break; 2099 case SVSB_GPU: 2100 svsb->opp_dev = svs_add_device_link(svsp, "gpu"); 2101 break; 2102 default: 2103 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 2104 return -EINVAL; 2105 } 2106 2107 if (IS_ERR(svsb->opp_dev)) 2108 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), 2109 "failed to get OPP device for bank %d\n", 2110 idx); 2111 } 2112 2113 return 0; 2114 } 2115 2116 static struct svs_bank svs_mt8192_banks[] = { 2117 { 2118 .sw_id = SVSB_GPU, 2119 .type = SVSB_LOW, 2120 .set_freq_pct = svs_set_bank_freq_pct_v3, 2121 .get_volts = svs_get_bank_volts_v3, 2122 .tzone_name = "gpu1", 2123 .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, 2124 .mode_support = SVSB_MODE_INIT02, 2125 .opp_count = MAX_OPP_ENTRIES, 2126 .freq_base = 688000000, 2127 .turn_freq_base = 688000000, 2128 .volt_step = 6250, 2129 .volt_base = 400000, 2130 .vmax = 0x60, 2131 .vmin = 0x1a, 2132 .age_config = 0x555555, 2133 .dc_config = 0x1, 2134 .dvt_fixed = 0x1, 2135 .vco = 0x18, 2136 .chk_shift = 0x87, 2137 .core_sel = 0x0fff0100, 2138 .int_st = BIT(0), 2139 .ctl0 = 0x00540003, 2140 .tzone_htemp = 85000, 2141 .tzone_htemp_voffset = 0, 2142 .tzone_ltemp = 25000, 2143 .tzone_ltemp_voffset = 7, 2144 }, 2145 { 2146 .sw_id = SVSB_GPU, 2147 .type = SVSB_HIGH, 2148 .set_freq_pct = svs_set_bank_freq_pct_v3, 2149 .get_volts = svs_get_bank_volts_v3, 2150 .tzone_name = "gpu1", 2151 .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | 2152 SVSB_MON_VOLT_IGNORE, 2153 .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, 2154 .opp_count = MAX_OPP_ENTRIES, 2155 .freq_base = 902000000, 2156 .turn_freq_base = 688000000, 2157 .volt_step = 6250, 2158 .volt_base = 400000, 2159 .vmax = 0x60, 2160 .vmin = 0x1a, 2161 .age_config = 0x555555, 2162 .dc_config = 0x1, 2163 .dvt_fixed = 0x6, 2164 .vco = 0x18, 2165 .chk_shift = 0x87, 2166 .core_sel = 0x0fff0101, 2167 .int_st = BIT(1), 2168 .ctl0 = 0x00540003, 2169 .tzone_htemp = 85000, 2170 .tzone_htemp_voffset = 0, 2171 .tzone_ltemp = 25000, 2172 .tzone_ltemp_voffset = 7, 2173 }, 2174 }; 2175 2176 static struct svs_bank svs_mt8183_banks[] = { 2177 { 2178 .sw_id = SVSB_CPU_LITTLE, 2179 .set_freq_pct = svs_set_bank_freq_pct_v2, 2180 .get_volts = svs_get_bank_volts_v2, 2181 .cpu_id = 0, 2182 .buck_name = "proc", 2183 .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2184 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2185 .opp_count = MAX_OPP_ENTRIES, 2186 .freq_base = 1989000000, 2187 .vboot = 0x30, 2188 .volt_step = 6250, 2189 .volt_base = 500000, 2190 .vmax = 0x64, 2191 .vmin = 0x18, 2192 .age_config = 0x555555, 2193 .dc_config = 0x555555, 2194 .dvt_fixed = 0x7, 2195 .vco = 0x10, 2196 .chk_shift = 0x77, 2197 .core_sel = 0x8fff0000, 2198 .int_st = BIT(0), 2199 .ctl0 = 0x00010001, 2200 }, 2201 { 2202 .sw_id = SVSB_CPU_BIG, 2203 .set_freq_pct = svs_set_bank_freq_pct_v2, 2204 .get_volts = svs_get_bank_volts_v2, 2205 .cpu_id = 4, 2206 .buck_name = "proc", 2207 .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2208 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2209 .opp_count = MAX_OPP_ENTRIES, 2210 .freq_base = 1989000000, 2211 .vboot = 0x30, 2212 .volt_step = 6250, 2213 .volt_base = 500000, 2214 .vmax = 0x58, 2215 .vmin = 0x10, 2216 .age_config = 0x555555, 2217 .dc_config = 0x555555, 2218 .dvt_fixed = 0x7, 2219 .vco = 0x10, 2220 .chk_shift = 0x77, 2221 .core_sel = 0x8fff0001, 2222 .int_st = BIT(1), 2223 .ctl0 = 0x00000001, 2224 }, 2225 { 2226 .sw_id = SVSB_CCI, 2227 .set_freq_pct = svs_set_bank_freq_pct_v2, 2228 .get_volts = svs_get_bank_volts_v2, 2229 .buck_name = "proc", 2230 .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2231 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2232 .opp_count = MAX_OPP_ENTRIES, 2233 .freq_base = 1196000000, 2234 .vboot = 0x30, 2235 .volt_step = 6250, 2236 .volt_base = 500000, 2237 .vmax = 0x64, 2238 .vmin = 0x18, 2239 .age_config = 0x555555, 2240 .dc_config = 0x555555, 2241 .dvt_fixed = 0x7, 2242 .vco = 0x10, 2243 .chk_shift = 0x77, 2244 .core_sel = 0x8fff0002, 2245 .int_st = BIT(2), 2246 .ctl0 = 0x00100003, 2247 }, 2248 { 2249 .sw_id = SVSB_GPU, 2250 .set_freq_pct = svs_set_bank_freq_pct_v2, 2251 .get_volts = svs_get_bank_volts_v2, 2252 .buck_name = "mali", 2253 .tzone_name = "tzts2", 2254 .volt_flags = SVSB_INIT01_PD_REQ | 2255 SVSB_INIT01_VOLT_INC_ONLY, 2256 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02 | 2257 SVSB_MODE_MON, 2258 .opp_count = MAX_OPP_ENTRIES, 2259 .freq_base = 900000000, 2260 .vboot = 0x30, 2261 .volt_step = 6250, 2262 .volt_base = 500000, 2263 .vmax = 0x40, 2264 .vmin = 0x14, 2265 .age_config = 0x555555, 2266 .dc_config = 0x555555, 2267 .dvt_fixed = 0x3, 2268 .vco = 0x10, 2269 .chk_shift = 0x77, 2270 .core_sel = 0x8fff0003, 2271 .int_st = BIT(3), 2272 .ctl0 = 0x00050001, 2273 .tzone_htemp = 85000, 2274 .tzone_htemp_voffset = 0, 2275 .tzone_ltemp = 25000, 2276 .tzone_ltemp_voffset = 3, 2277 }, 2278 }; 2279 2280 static const struct svs_platform_data svs_mt8192_platform_data = { 2281 .name = "mt8192-svs", 2282 .banks = svs_mt8192_banks, 2283 .efuse_parsing = svs_mt8192_efuse_parsing, 2284 .probe = svs_mt8192_platform_probe, 2285 .regs = svs_regs_v2, 2286 .bank_max = ARRAY_SIZE(svs_mt8192_banks), 2287 }; 2288 2289 static const struct svs_platform_data svs_mt8183_platform_data = { 2290 .name = "mt8183-svs", 2291 .banks = svs_mt8183_banks, 2292 .efuse_parsing = svs_mt8183_efuse_parsing, 2293 .probe = svs_mt8183_platform_probe, 2294 .regs = svs_regs_v2, 2295 .bank_max = ARRAY_SIZE(svs_mt8183_banks), 2296 }; 2297 2298 static const struct of_device_id svs_of_match[] = { 2299 { 2300 .compatible = "mediatek,mt8192-svs", 2301 .data = &svs_mt8192_platform_data, 2302 }, { 2303 .compatible = "mediatek,mt8183-svs", 2304 .data = &svs_mt8183_platform_data, 2305 }, { 2306 /* Sentinel */ 2307 }, 2308 }; 2309 MODULE_DEVICE_TABLE(of, svs_of_match); 2310 2311 static int svs_probe(struct platform_device *pdev) 2312 { 2313 struct svs_platform *svsp; 2314 const struct svs_platform_data *svsp_data; 2315 int ret, svsp_irq; 2316 2317 svsp_data = of_device_get_match_data(&pdev->dev); 2318 2319 svsp = devm_kzalloc(&pdev->dev, sizeof(*svsp), GFP_KERNEL); 2320 if (!svsp) 2321 return -ENOMEM; 2322 2323 svsp->dev = &pdev->dev; 2324 svsp->banks = svsp_data->banks; 2325 svsp->regs = svsp_data->regs; 2326 svsp->bank_max = svsp_data->bank_max; 2327 2328 ret = svsp_data->probe(svsp); 2329 if (ret) 2330 return ret; 2331 2332 ret = svs_get_efuse_data(svsp, "svs-calibration-data", 2333 &svsp->efuse, &svsp->efuse_max); 2334 if (ret) { 2335 ret = -EPERM; 2336 goto svs_probe_free_efuse; 2337 } 2338 2339 if (!svsp_data->efuse_parsing(svsp)) { 2340 dev_err(svsp->dev, "efuse data parsing failed\n"); 2341 ret = -EPERM; 2342 goto svs_probe_free_tefuse; 2343 } 2344 2345 ret = svs_bank_resource_setup(svsp); 2346 if (ret) { 2347 dev_err(svsp->dev, "svs bank resource setup fail: %d\n", ret); 2348 goto svs_probe_free_tefuse; 2349 } 2350 2351 svsp_irq = platform_get_irq(pdev, 0); 2352 if (svsp_irq < 0) { 2353 ret = svsp_irq; 2354 goto svs_probe_free_tefuse; 2355 } 2356 2357 svsp->main_clk = devm_clk_get(svsp->dev, "main"); 2358 if (IS_ERR(svsp->main_clk)) { 2359 dev_err(svsp->dev, "failed to get clock: %ld\n", 2360 PTR_ERR(svsp->main_clk)); 2361 ret = PTR_ERR(svsp->main_clk); 2362 goto svs_probe_free_tefuse; 2363 } 2364 2365 ret = clk_prepare_enable(svsp->main_clk); 2366 if (ret) { 2367 dev_err(svsp->dev, "cannot enable main clk: %d\n", ret); 2368 goto svs_probe_free_tefuse; 2369 } 2370 2371 svsp->base = of_iomap(svsp->dev->of_node, 0); 2372 if (IS_ERR_OR_NULL(svsp->base)) { 2373 dev_err(svsp->dev, "cannot find svs register base\n"); 2374 ret = -EINVAL; 2375 goto svs_probe_clk_disable; 2376 } 2377 2378 ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr, 2379 IRQF_ONESHOT, svsp_data->name, svsp); 2380 if (ret) { 2381 dev_err(svsp->dev, "register irq(%d) failed: %d\n", 2382 svsp_irq, ret); 2383 goto svs_probe_iounmap; 2384 } 2385 2386 ret = svs_start(svsp); 2387 if (ret) { 2388 dev_err(svsp->dev, "svs start fail: %d\n", ret); 2389 goto svs_probe_iounmap; 2390 } 2391 2392 #ifdef CONFIG_DEBUG_FS 2393 ret = svs_create_debug_cmds(svsp); 2394 if (ret) { 2395 dev_err(svsp->dev, "svs create debug cmds fail: %d\n", ret); 2396 goto svs_probe_iounmap; 2397 } 2398 #endif 2399 2400 return 0; 2401 2402 svs_probe_iounmap: 2403 iounmap(svsp->base); 2404 2405 svs_probe_clk_disable: 2406 clk_disable_unprepare(svsp->main_clk); 2407 2408 svs_probe_free_tefuse: 2409 if (!IS_ERR_OR_NULL(svsp->tefuse)) 2410 kfree(svsp->tefuse); 2411 2412 svs_probe_free_efuse: 2413 if (!IS_ERR_OR_NULL(svsp->efuse)) 2414 kfree(svsp->efuse); 2415 2416 return ret; 2417 } 2418 2419 static DEFINE_SIMPLE_DEV_PM_OPS(svs_pm_ops, svs_suspend, svs_resume); 2420 2421 static struct platform_driver svs_driver = { 2422 .probe = svs_probe, 2423 .driver = { 2424 .name = "mtk-svs", 2425 .pm = &svs_pm_ops, 2426 .of_match_table = svs_of_match, 2427 }, 2428 }; 2429 2430 module_platform_driver(svs_driver); 2431 2432 MODULE_AUTHOR("Roger Lu <roger.lu@mediatek.com>"); 2433 MODULE_DESCRIPTION("MediaTek SVS driver"); 2434 MODULE_LICENSE("GPL"); 2435