1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/bits.h> 7 #include <linux/clk.h> 8 #include <linux/completion.h> 9 #include <linux/cpuidle.h> 10 #include <linux/debugfs.h> 11 #include <linux/device.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/kthread.h> 16 #include <linux/module.h> 17 #include <linux/mutex.h> 18 #include <linux/nvmem-consumer.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_domain.h> 24 #include <linux/pm_opp.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/thermal.h> 32 33 /* svs bank 1-line software id */ 34 #define SVSB_CPU_LITTLE BIT(0) 35 #define SVSB_CPU_BIG BIT(1) 36 #define SVSB_CCI BIT(2) 37 #define SVSB_GPU BIT(3) 38 39 /* svs bank 2-line type */ 40 #define SVSB_LOW BIT(8) 41 #define SVSB_HIGH BIT(9) 42 43 /* svs bank mode support */ 44 #define SVSB_MODE_ALL_DISABLE 0 45 #define SVSB_MODE_INIT01 BIT(1) 46 #define SVSB_MODE_INIT02 BIT(2) 47 #define SVSB_MODE_MON BIT(3) 48 49 /* svs bank volt flags */ 50 #define SVSB_INIT01_PD_REQ BIT(0) 51 #define SVSB_INIT01_VOLT_IGNORE BIT(1) 52 #define SVSB_INIT01_VOLT_INC_ONLY BIT(2) 53 #define SVSB_MON_VOLT_IGNORE BIT(16) 54 #define SVSB_REMOVE_DVTFIXED_VOLT BIT(24) 55 56 /* svs bank register common configuration */ 57 #define SVSB_DET_MAX 0xffff 58 #define SVSB_DET_WINDOW 0xa28 59 #define SVSB_DTHI 0x1 60 #define SVSB_DTLO 0xfe 61 #define SVSB_EN_INIT01 0x1 62 #define SVSB_EN_INIT02 0x5 63 #define SVSB_EN_MON 0x2 64 #define SVSB_EN_OFF 0x0 65 #define SVSB_INTEN_INIT0x 0x00005f01 66 #define SVSB_INTEN_MONVOPEN 0x00ff0000 67 #define SVSB_INTSTS_CLEAN 0x00ffffff 68 #define SVSB_INTSTS_COMPLETE 0x1 69 #define SVSB_INTSTS_MONVOP 0x00ff0000 70 #define SVSB_RUNCONFIG_DEFAULT 0x80000000 71 72 /* svs bank related setting */ 73 #define BITS8 8 74 #define MAX_OPP_ENTRIES 16 75 #define REG_BYTES 4 76 #define SVSB_DC_SIGNED_BIT BIT(15) 77 #define SVSB_DET_CLK_EN BIT(31) 78 #define SVSB_TEMP_LOWER_BOUND 0xb2 79 #define SVSB_TEMP_UPPER_BOUND 0x64 80 81 static DEFINE_SPINLOCK(svs_lock); 82 83 #define debug_fops_ro(name) \ 84 static int svs_##name##_debug_open(struct inode *inode, \ 85 struct file *filp) \ 86 { \ 87 return single_open(filp, svs_##name##_debug_show, \ 88 inode->i_private); \ 89 } \ 90 static const struct file_operations svs_##name##_debug_fops = { \ 91 .owner = THIS_MODULE, \ 92 .open = svs_##name##_debug_open, \ 93 .read = seq_read, \ 94 .llseek = seq_lseek, \ 95 .release = single_release, \ 96 } 97 98 #define debug_fops_rw(name) \ 99 static int svs_##name##_debug_open(struct inode *inode, \ 100 struct file *filp) \ 101 { \ 102 return single_open(filp, svs_##name##_debug_show, \ 103 inode->i_private); \ 104 } \ 105 static const struct file_operations svs_##name##_debug_fops = { \ 106 .owner = THIS_MODULE, \ 107 .open = svs_##name##_debug_open, \ 108 .read = seq_read, \ 109 .write = svs_##name##_debug_write, \ 110 .llseek = seq_lseek, \ 111 .release = single_release, \ 112 } 113 114 #define svs_dentry_data(name) {__stringify(name), &svs_##name##_debug_fops} 115 116 /** 117 * enum svsb_phase - svs bank phase enumeration 118 * @SVSB_PHASE_ERROR: svs bank encounters unexpected condition 119 * @SVSB_PHASE_INIT01: svs bank basic init for data calibration 120 * @SVSB_PHASE_INIT02: svs bank can provide voltages to opp table 121 * @SVSB_PHASE_MON: svs bank can provide voltages with thermal effect 122 * @SVSB_PHASE_MAX: total number of svs bank phase (debug purpose) 123 * 124 * Each svs bank has its own independent phase and we enable each svs bank by 125 * running their phase orderly. However, when svs bank encounters unexpected 126 * condition, it will fire an irq (PHASE_ERROR) to inform svs software. 127 * 128 * svs bank general phase-enabled order: 129 * SVSB_PHASE_INIT01 -> SVSB_PHASE_INIT02 -> SVSB_PHASE_MON 130 */ 131 enum svsb_phase { 132 SVSB_PHASE_ERROR = 0, 133 SVSB_PHASE_INIT01, 134 SVSB_PHASE_INIT02, 135 SVSB_PHASE_MON, 136 SVSB_PHASE_MAX, 137 }; 138 139 enum svs_reg_index { 140 DESCHAR = 0, 141 TEMPCHAR, 142 DETCHAR, 143 AGECHAR, 144 DCCONFIG, 145 AGECONFIG, 146 FREQPCT30, 147 FREQPCT74, 148 LIMITVALS, 149 VBOOT, 150 DETWINDOW, 151 CONFIG, 152 TSCALCS, 153 RUNCONFIG, 154 SVSEN, 155 INIT2VALS, 156 DCVALUES, 157 AGEVALUES, 158 VOP30, 159 VOP74, 160 TEMP, 161 INTSTS, 162 INTSTSRAW, 163 INTEN, 164 CHKINT, 165 CHKSHIFT, 166 STATUS, 167 VDESIGN30, 168 VDESIGN74, 169 DVT30, 170 DVT74, 171 AGECOUNT, 172 SMSTATE0, 173 SMSTATE1, 174 CTL0, 175 DESDETSEC, 176 TEMPAGESEC, 177 CTRLSPARE0, 178 CTRLSPARE1, 179 CTRLSPARE2, 180 CTRLSPARE3, 181 CORESEL, 182 THERMINTST, 183 INTST, 184 THSTAGE0ST, 185 THSTAGE1ST, 186 THSTAGE2ST, 187 THAHBST0, 188 THAHBST1, 189 SPARE0, 190 SPARE1, 191 SPARE2, 192 SPARE3, 193 THSLPEVEB, 194 SVS_REG_MAX, 195 }; 196 197 static const u32 svs_regs_v2[] = { 198 [DESCHAR] = 0xc00, 199 [TEMPCHAR] = 0xc04, 200 [DETCHAR] = 0xc08, 201 [AGECHAR] = 0xc0c, 202 [DCCONFIG] = 0xc10, 203 [AGECONFIG] = 0xc14, 204 [FREQPCT30] = 0xc18, 205 [FREQPCT74] = 0xc1c, 206 [LIMITVALS] = 0xc20, 207 [VBOOT] = 0xc24, 208 [DETWINDOW] = 0xc28, 209 [CONFIG] = 0xc2c, 210 [TSCALCS] = 0xc30, 211 [RUNCONFIG] = 0xc34, 212 [SVSEN] = 0xc38, 213 [INIT2VALS] = 0xc3c, 214 [DCVALUES] = 0xc40, 215 [AGEVALUES] = 0xc44, 216 [VOP30] = 0xc48, 217 [VOP74] = 0xc4c, 218 [TEMP] = 0xc50, 219 [INTSTS] = 0xc54, 220 [INTSTSRAW] = 0xc58, 221 [INTEN] = 0xc5c, 222 [CHKINT] = 0xc60, 223 [CHKSHIFT] = 0xc64, 224 [STATUS] = 0xc68, 225 [VDESIGN30] = 0xc6c, 226 [VDESIGN74] = 0xc70, 227 [DVT30] = 0xc74, 228 [DVT74] = 0xc78, 229 [AGECOUNT] = 0xc7c, 230 [SMSTATE0] = 0xc80, 231 [SMSTATE1] = 0xc84, 232 [CTL0] = 0xc88, 233 [DESDETSEC] = 0xce0, 234 [TEMPAGESEC] = 0xce4, 235 [CTRLSPARE0] = 0xcf0, 236 [CTRLSPARE1] = 0xcf4, 237 [CTRLSPARE2] = 0xcf8, 238 [CTRLSPARE3] = 0xcfc, 239 [CORESEL] = 0xf00, 240 [THERMINTST] = 0xf04, 241 [INTST] = 0xf08, 242 [THSTAGE0ST] = 0xf0c, 243 [THSTAGE1ST] = 0xf10, 244 [THSTAGE2ST] = 0xf14, 245 [THAHBST0] = 0xf18, 246 [THAHBST1] = 0xf1c, 247 [SPARE0] = 0xf20, 248 [SPARE1] = 0xf24, 249 [SPARE2] = 0xf28, 250 [SPARE3] = 0xf2c, 251 [THSLPEVEB] = 0xf30, 252 }; 253 254 /** 255 * struct svs_platform - svs platform control 256 * @name: svs platform name 257 * @base: svs platform register base 258 * @dev: svs platform device 259 * @main_clk: main clock for svs bank 260 * @pbank: svs bank pointer needing to be protected by spin_lock section 261 * @banks: svs banks that svs platform supports 262 * @rst: svs platform reset control 263 * @efuse_parsing: svs platform efuse parsing function pointer 264 * @probe: svs platform probe function pointer 265 * @irqflags: svs platform irq settings flags 266 * @efuse_max: total number of svs efuse 267 * @tefuse_max: total number of thermal efuse 268 * @regs: svs platform registers map 269 * @bank_max: total number of svs banks 270 * @efuse: svs efuse data received from NVMEM framework 271 * @tefuse: thermal efuse data received from NVMEM framework 272 */ 273 struct svs_platform { 274 char *name; 275 void __iomem *base; 276 struct device *dev; 277 struct clk *main_clk; 278 struct svs_bank *pbank; 279 struct svs_bank *banks; 280 struct reset_control *rst; 281 bool (*efuse_parsing)(struct svs_platform *svsp); 282 int (*probe)(struct svs_platform *svsp); 283 unsigned long irqflags; 284 size_t efuse_max; 285 size_t tefuse_max; 286 const u32 *regs; 287 u32 bank_max; 288 u32 *efuse; 289 u32 *tefuse; 290 }; 291 292 struct svs_platform_data { 293 char *name; 294 struct svs_bank *banks; 295 bool (*efuse_parsing)(struct svs_platform *svsp); 296 int (*probe)(struct svs_platform *svsp); 297 unsigned long irqflags; 298 const u32 *regs; 299 u32 bank_max; 300 }; 301 302 /** 303 * struct svs_bank - svs bank representation 304 * @dev: bank device 305 * @opp_dev: device for opp table/buck control 306 * @init_completion: the timeout completion for bank init 307 * @buck: regulator used by opp_dev 308 * @tzd: thermal zone device for getting temperature 309 * @lock: mutex lock to protect voltage update process 310 * @set_freq_pct: function pointer to set bank frequency percent table 311 * @get_volts: function pointer to get bank voltages 312 * @name: bank name 313 * @buck_name: regulator name 314 * @tzone_name: thermal zone name 315 * @phase: bank current phase 316 * @volt_od: bank voltage overdrive 317 * @reg_data: bank register data in different phase for debug purpose 318 * @pm_runtime_enabled_count: bank pm runtime enabled count 319 * @mode_support: bank mode support. 320 * @freq_base: reference frequency for bank init 321 * @turn_freq_base: refenrece frequency for 2-line turn point 322 * @vboot: voltage request for bank init01 only 323 * @opp_dfreq: default opp frequency table 324 * @opp_dvolt: default opp voltage table 325 * @freq_pct: frequency percent table for bank init 326 * @volt: bank voltage table 327 * @volt_step: bank voltage step 328 * @volt_base: bank voltage base 329 * @volt_flags: bank voltage flags 330 * @vmax: bank voltage maximum 331 * @vmin: bank voltage minimum 332 * @age_config: bank age configuration 333 * @age_voffset_in: bank age voltage offset 334 * @dc_config: bank dc configuration 335 * @dc_voffset_in: bank dc voltage offset 336 * @dvt_fixed: bank dvt fixed value 337 * @vco: bank VCO value 338 * @chk_shift: bank chicken shift 339 * @core_sel: bank selection 340 * @opp_count: bank opp count 341 * @int_st: bank interrupt identification 342 * @sw_id: bank software identification 343 * @cpu_id: cpu core id for SVS CPU bank use only 344 * @ctl0: TS-x selection 345 * @temp: bank temperature 346 * @tzone_htemp: thermal zone high temperature threshold 347 * @tzone_htemp_voffset: thermal zone high temperature voltage offset 348 * @tzone_ltemp: thermal zone low temperature threshold 349 * @tzone_ltemp_voffset: thermal zone low temperature voltage offset 350 * @bts: svs efuse data 351 * @mts: svs efuse data 352 * @bdes: svs efuse data 353 * @mdes: svs efuse data 354 * @mtdes: svs efuse data 355 * @dcbdet: svs efuse data 356 * @dcmdet: svs efuse data 357 * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank 358 * @type: bank type to represent it is 2-line (high/low) bank or 1-line bank 359 * 360 * Svs bank will generate suitalbe voltages by below general math equation 361 * and provide these voltages to opp voltage table. 362 * 363 * opp_volt[i] = (volt[i] * volt_step) + volt_base; 364 */ 365 struct svs_bank { 366 struct device *dev; 367 struct device *opp_dev; 368 struct completion init_completion; 369 struct regulator *buck; 370 struct thermal_zone_device *tzd; 371 struct mutex lock; /* lock to protect voltage update process */ 372 void (*set_freq_pct)(struct svs_platform *svsp); 373 void (*get_volts)(struct svs_platform *svsp); 374 char *name; 375 char *buck_name; 376 char *tzone_name; 377 enum svsb_phase phase; 378 s32 volt_od; 379 u32 reg_data[SVSB_PHASE_MAX][SVS_REG_MAX]; 380 u32 pm_runtime_enabled_count; 381 u32 mode_support; 382 u32 freq_base; 383 u32 turn_freq_base; 384 u32 vboot; 385 u32 opp_dfreq[MAX_OPP_ENTRIES]; 386 u32 opp_dvolt[MAX_OPP_ENTRIES]; 387 u32 freq_pct[MAX_OPP_ENTRIES]; 388 u32 volt[MAX_OPP_ENTRIES]; 389 u32 volt_step; 390 u32 volt_base; 391 u32 volt_flags; 392 u32 vmax; 393 u32 vmin; 394 u32 age_config; 395 u32 age_voffset_in; 396 u32 dc_config; 397 u32 dc_voffset_in; 398 u32 dvt_fixed; 399 u32 vco; 400 u32 chk_shift; 401 u32 core_sel; 402 u32 opp_count; 403 u32 int_st; 404 u32 sw_id; 405 u32 cpu_id; 406 u32 ctl0; 407 u32 temp; 408 u32 tzone_htemp; 409 u32 tzone_htemp_voffset; 410 u32 tzone_ltemp; 411 u32 tzone_ltemp_voffset; 412 u32 bts; 413 u32 mts; 414 u32 bdes; 415 u32 mdes; 416 u32 mtdes; 417 u32 dcbdet; 418 u32 dcmdet; 419 u32 turn_pt; 420 u32 type; 421 }; 422 423 static u32 percent(u32 numerator, u32 denominator) 424 { 425 /* If not divide 1000, "numerator * 100" will have data overflow. */ 426 numerator /= 1000; 427 denominator /= 1000; 428 429 return DIV_ROUND_UP(numerator * 100, denominator); 430 } 431 432 static u32 svs_readl_relaxed(struct svs_platform *svsp, enum svs_reg_index rg_i) 433 { 434 return readl_relaxed(svsp->base + svsp->regs[rg_i]); 435 } 436 437 static void svs_writel_relaxed(struct svs_platform *svsp, u32 val, 438 enum svs_reg_index rg_i) 439 { 440 writel_relaxed(val, svsp->base + svsp->regs[rg_i]); 441 } 442 443 static void svs_switch_bank(struct svs_platform *svsp) 444 { 445 struct svs_bank *svsb = svsp->pbank; 446 447 svs_writel_relaxed(svsp, svsb->core_sel, CORESEL); 448 } 449 450 static u32 svs_bank_volt_to_opp_volt(u32 svsb_volt, u32 svsb_volt_step, 451 u32 svsb_volt_base) 452 { 453 return (svsb_volt * svsb_volt_step) + svsb_volt_base; 454 } 455 456 static u32 svs_opp_volt_to_bank_volt(u32 opp_u_volt, u32 svsb_volt_step, 457 u32 svsb_volt_base) 458 { 459 return (opp_u_volt - svsb_volt_base) / svsb_volt_step; 460 } 461 462 static int svs_sync_bank_volts_from_opp(struct svs_bank *svsb) 463 { 464 struct dev_pm_opp *opp; 465 u32 i, opp_u_volt; 466 467 for (i = 0; i < svsb->opp_count; i++) { 468 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, 469 svsb->opp_dfreq[i], 470 true); 471 if (IS_ERR(opp)) { 472 dev_err(svsb->dev, "cannot find freq = %u (%ld)\n", 473 svsb->opp_dfreq[i], PTR_ERR(opp)); 474 return PTR_ERR(opp); 475 } 476 477 opp_u_volt = dev_pm_opp_get_voltage(opp); 478 svsb->volt[i] = svs_opp_volt_to_bank_volt(opp_u_volt, 479 svsb->volt_step, 480 svsb->volt_base); 481 dev_pm_opp_put(opp); 482 } 483 484 return 0; 485 } 486 487 static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) 488 { 489 int ret = -EPERM, tzone_temp = 0; 490 u32 i, svsb_volt, opp_volt, temp_voffset = 0, opp_start, opp_stop; 491 492 mutex_lock(&svsb->lock); 493 494 /* 495 * 2-line bank updates its corresponding opp volts. 496 * 1-line bank updates all opp volts. 497 */ 498 if (svsb->type == SVSB_HIGH) { 499 opp_start = 0; 500 opp_stop = svsb->turn_pt; 501 } else if (svsb->type == SVSB_LOW) { 502 opp_start = svsb->turn_pt; 503 opp_stop = svsb->opp_count; 504 } else { 505 opp_start = 0; 506 opp_stop = svsb->opp_count; 507 } 508 509 /* Get thermal effect */ 510 if (svsb->phase == SVSB_PHASE_MON) { 511 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); 512 if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND && 513 svsb->temp < SVSB_TEMP_LOWER_BOUND)) { 514 dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n", 515 svsb->tzone_name, ret, svsb->temp); 516 svsb->phase = SVSB_PHASE_ERROR; 517 } 518 519 if (tzone_temp >= svsb->tzone_htemp) 520 temp_voffset += svsb->tzone_htemp_voffset; 521 else if (tzone_temp <= svsb->tzone_ltemp) 522 temp_voffset += svsb->tzone_ltemp_voffset; 523 524 /* 2-line bank update all opp volts when running mon mode */ 525 if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) { 526 opp_start = 0; 527 opp_stop = svsb->opp_count; 528 } 529 } 530 531 /* vmin <= svsb_volt (opp_volt) <= default opp voltage */ 532 for (i = opp_start; i < opp_stop; i++) { 533 switch (svsb->phase) { 534 case SVSB_PHASE_ERROR: 535 opp_volt = svsb->opp_dvolt[i]; 536 break; 537 case SVSB_PHASE_INIT01: 538 /* do nothing */ 539 goto unlock_mutex; 540 case SVSB_PHASE_INIT02: 541 svsb_volt = max(svsb->volt[i], svsb->vmin); 542 opp_volt = svs_bank_volt_to_opp_volt(svsb_volt, 543 svsb->volt_step, 544 svsb->volt_base); 545 break; 546 case SVSB_PHASE_MON: 547 svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin); 548 opp_volt = svs_bank_volt_to_opp_volt(svsb_volt, 549 svsb->volt_step, 550 svsb->volt_base); 551 break; 552 default: 553 dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase); 554 ret = -EINVAL; 555 goto unlock_mutex; 556 } 557 558 opp_volt = min(opp_volt, svsb->opp_dvolt[i]); 559 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev, 560 svsb->opp_dfreq[i], 561 opp_volt, opp_volt, 562 svsb->opp_dvolt[i]); 563 if (ret) { 564 dev_err(svsb->dev, "set %uuV fail: %d\n", 565 opp_volt, ret); 566 goto unlock_mutex; 567 } 568 } 569 570 unlock_mutex: 571 mutex_unlock(&svsb->lock); 572 573 return ret; 574 } 575 576 static int svs_dump_debug_show(struct seq_file *m, void *p) 577 { 578 struct svs_platform *svsp = (struct svs_platform *)m->private; 579 struct svs_bank *svsb; 580 unsigned long svs_reg_addr; 581 u32 idx, i, j, bank_id; 582 583 for (i = 0; i < svsp->efuse_max; i++) 584 if (svsp->efuse && svsp->efuse[i]) 585 seq_printf(m, "M_HW_RES%d = 0x%08x\n", 586 i, svsp->efuse[i]); 587 588 for (i = 0; i < svsp->tefuse_max; i++) 589 if (svsp->tefuse) 590 seq_printf(m, "THERMAL_EFUSE%d = 0x%08x\n", 591 i, svsp->tefuse[i]); 592 593 for (bank_id = 0, idx = 0; idx < svsp->bank_max; idx++, bank_id++) { 594 svsb = &svsp->banks[idx]; 595 596 for (i = SVSB_PHASE_INIT01; i <= SVSB_PHASE_MON; i++) { 597 seq_printf(m, "Bank_number = %u\n", bank_id); 598 599 if (i == SVSB_PHASE_INIT01 || i == SVSB_PHASE_INIT02) 600 seq_printf(m, "mode = init%d\n", i); 601 else if (i == SVSB_PHASE_MON) 602 seq_puts(m, "mode = mon\n"); 603 else 604 seq_puts(m, "mode = error\n"); 605 606 for (j = DESCHAR; j < SVS_REG_MAX; j++) { 607 svs_reg_addr = (unsigned long)(svsp->base + 608 svsp->regs[j]); 609 seq_printf(m, "0x%08lx = 0x%08x\n", 610 svs_reg_addr, svsb->reg_data[i][j]); 611 } 612 } 613 } 614 615 return 0; 616 } 617 618 debug_fops_ro(dump); 619 620 static int svs_enable_debug_show(struct seq_file *m, void *v) 621 { 622 struct svs_bank *svsb = (struct svs_bank *)m->private; 623 624 switch (svsb->phase) { 625 case SVSB_PHASE_ERROR: 626 seq_puts(m, "disabled\n"); 627 break; 628 case SVSB_PHASE_INIT01: 629 seq_puts(m, "init1\n"); 630 break; 631 case SVSB_PHASE_INIT02: 632 seq_puts(m, "init2\n"); 633 break; 634 case SVSB_PHASE_MON: 635 seq_puts(m, "mon mode\n"); 636 break; 637 default: 638 seq_puts(m, "unknown\n"); 639 break; 640 } 641 642 return 0; 643 } 644 645 static ssize_t svs_enable_debug_write(struct file *filp, 646 const char __user *buffer, 647 size_t count, loff_t *pos) 648 { 649 struct svs_bank *svsb = file_inode(filp)->i_private; 650 struct svs_platform *svsp = dev_get_drvdata(svsb->dev); 651 unsigned long flags; 652 int enabled, ret; 653 char *buf = NULL; 654 655 if (count >= PAGE_SIZE) 656 return -EINVAL; 657 658 buf = (char *)memdup_user_nul(buffer, count); 659 if (IS_ERR(buf)) 660 return PTR_ERR(buf); 661 662 ret = kstrtoint(buf, 10, &enabled); 663 if (ret) 664 return ret; 665 666 if (!enabled) { 667 spin_lock_irqsave(&svs_lock, flags); 668 svsp->pbank = svsb; 669 svsb->mode_support = SVSB_MODE_ALL_DISABLE; 670 svs_switch_bank(svsp); 671 svs_writel_relaxed(svsp, SVSB_EN_OFF, SVSEN); 672 svs_writel_relaxed(svsp, SVSB_INTSTS_CLEAN, INTSTS); 673 spin_unlock_irqrestore(&svs_lock, flags); 674 675 svsb->phase = SVSB_PHASE_ERROR; 676 svs_adjust_pm_opp_volts(svsb); 677 } 678 679 kfree(buf); 680 681 return count; 682 } 683 684 debug_fops_rw(enable); 685 686 static int svs_status_debug_show(struct seq_file *m, void *v) 687 { 688 struct svs_bank *svsb = (struct svs_bank *)m->private; 689 struct dev_pm_opp *opp; 690 int tzone_temp = 0, ret; 691 u32 i; 692 693 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); 694 if (ret) 695 seq_printf(m, "%s: temperature ignore, turn_pt = %u\n", 696 svsb->name, svsb->turn_pt); 697 else 698 seq_printf(m, "%s: temperature = %d, turn_pt = %u\n", 699 svsb->name, tzone_temp, svsb->turn_pt); 700 701 for (i = 0; i < svsb->opp_count; i++) { 702 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, 703 svsb->opp_dfreq[i], true); 704 if (IS_ERR(opp)) { 705 seq_printf(m, "%s: cannot find freq = %u (%ld)\n", 706 svsb->name, svsb->opp_dfreq[i], 707 PTR_ERR(opp)); 708 return PTR_ERR(opp); 709 } 710 711 seq_printf(m, "opp_freq[%02u]: %u, opp_volt[%02u]: %lu, ", 712 i, svsb->opp_dfreq[i], i, 713 dev_pm_opp_get_voltage(opp)); 714 seq_printf(m, "svsb_volt[%02u]: 0x%x, freq_pct[%02u]: %u\n", 715 i, svsb->volt[i], i, svsb->freq_pct[i]); 716 dev_pm_opp_put(opp); 717 } 718 719 return 0; 720 } 721 722 debug_fops_ro(status); 723 724 static int svs_create_debug_cmds(struct svs_platform *svsp) 725 { 726 struct svs_bank *svsb; 727 struct dentry *svs_dir, *svsb_dir, *file_entry; 728 const char *d = "/sys/kernel/debug/svs"; 729 u32 i, idx; 730 731 struct svs_dentry { 732 const char *name; 733 const struct file_operations *fops; 734 }; 735 736 struct svs_dentry svs_entries[] = { 737 svs_dentry_data(dump), 738 }; 739 740 struct svs_dentry svsb_entries[] = { 741 svs_dentry_data(enable), 742 svs_dentry_data(status), 743 }; 744 745 svs_dir = debugfs_create_dir("svs", NULL); 746 if (IS_ERR(svs_dir)) { 747 dev_err(svsp->dev, "cannot create %s: %ld\n", 748 d, PTR_ERR(svs_dir)); 749 return PTR_ERR(svs_dir); 750 } 751 752 for (i = 0; i < ARRAY_SIZE(svs_entries); i++) { 753 file_entry = debugfs_create_file(svs_entries[i].name, 0664, 754 svs_dir, svsp, 755 svs_entries[i].fops); 756 if (IS_ERR(file_entry)) { 757 dev_err(svsp->dev, "cannot create %s/%s: %ld\n", 758 d, svs_entries[i].name, PTR_ERR(file_entry)); 759 return PTR_ERR(file_entry); 760 } 761 } 762 763 for (idx = 0; idx < svsp->bank_max; idx++) { 764 svsb = &svsp->banks[idx]; 765 766 if (svsb->mode_support == SVSB_MODE_ALL_DISABLE) 767 continue; 768 769 svsb_dir = debugfs_create_dir(svsb->name, svs_dir); 770 if (IS_ERR(svsb_dir)) { 771 dev_err(svsp->dev, "cannot create %s/%s: %ld\n", 772 d, svsb->name, PTR_ERR(svsb_dir)); 773 return PTR_ERR(svsb_dir); 774 } 775 776 for (i = 0; i < ARRAY_SIZE(svsb_entries); i++) { 777 file_entry = debugfs_create_file(svsb_entries[i].name, 778 0664, svsb_dir, svsb, 779 svsb_entries[i].fops); 780 if (IS_ERR(file_entry)) { 781 dev_err(svsp->dev, "no %s/%s/%s?: %ld\n", 782 d, svsb->name, svsb_entries[i].name, 783 PTR_ERR(file_entry)); 784 return PTR_ERR(file_entry); 785 } 786 } 787 } 788 789 return 0; 790 } 791 792 static u32 interpolate(u32 f0, u32 f1, u32 v0, u32 v1, u32 fx) 793 { 794 u32 vx; 795 796 if (v0 == v1 || f0 == f1) 797 return v0; 798 799 /* *100 to have decimal fraction factor */ 800 vx = (v0 * 100) - ((((v0 - v1) * 100) / (f0 - f1)) * (f0 - fx)); 801 802 return DIV_ROUND_UP(vx, 100); 803 } 804 805 static void svs_get_bank_volts_v3(struct svs_platform *svsp) 806 { 807 struct svs_bank *svsb = svsp->pbank; 808 u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt; 809 u32 b_sft, shift_byte = 0, opp_start = 0, opp_stop = 0; 810 u32 middle_index = (svsb->opp_count / 2); 811 812 if (svsb->phase == SVSB_PHASE_MON && 813 svsb->volt_flags & SVSB_MON_VOLT_IGNORE) 814 return; 815 816 vop74 = svs_readl_relaxed(svsp, VOP74); 817 vop30 = svs_readl_relaxed(svsp, VOP30); 818 819 /* Target is to set svsb->volt[] by algorithm */ 820 if (turn_pt < middle_index) { 821 if (svsb->type == SVSB_HIGH) { 822 /* volt[0] ~ volt[turn_pt - 1] */ 823 for (i = 0; i < turn_pt; i++) { 824 b_sft = BITS8 * (shift_byte % REG_BYTES); 825 vop = (shift_byte < REG_BYTES) ? &vop30 : 826 &vop74; 827 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); 828 shift_byte++; 829 } 830 } else if (svsb->type == SVSB_LOW) { 831 /* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */ 832 j = svsb->opp_count - 7; 833 svsb->volt[turn_pt] = vop30 & GENMASK(7, 0); 834 shift_byte++; 835 for (i = j; i < svsb->opp_count; i++) { 836 b_sft = BITS8 * (shift_byte % REG_BYTES); 837 vop = (shift_byte < REG_BYTES) ? &vop30 : 838 &vop74; 839 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); 840 shift_byte++; 841 } 842 843 /* volt[turn_pt + 1] ~ volt[j - 1] by interpolate */ 844 for (i = turn_pt + 1; i < j; i++) 845 svsb->volt[i] = interpolate(svsb->freq_pct[turn_pt], 846 svsb->freq_pct[j], 847 svsb->volt[turn_pt], 848 svsb->volt[j], 849 svsb->freq_pct[i]); 850 } 851 } else { 852 if (svsb->type == SVSB_HIGH) { 853 /* volt[0] + volt[j] ~ volt[turn_pt - 1] */ 854 j = turn_pt - 7; 855 svsb->volt[0] = vop30 & GENMASK(7, 0); 856 shift_byte++; 857 for (i = j; i < turn_pt; i++) { 858 b_sft = BITS8 * (shift_byte % REG_BYTES); 859 vop = (shift_byte < REG_BYTES) ? &vop30 : 860 &vop74; 861 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); 862 shift_byte++; 863 } 864 865 /* volt[1] ~ volt[j - 1] by interpolate */ 866 for (i = 1; i < j; i++) 867 svsb->volt[i] = interpolate(svsb->freq_pct[0], 868 svsb->freq_pct[j], 869 svsb->volt[0], 870 svsb->volt[j], 871 svsb->freq_pct[i]); 872 } else if (svsb->type == SVSB_LOW) { 873 /* volt[turn_pt] ~ volt[opp_count - 1] */ 874 for (i = turn_pt; i < svsb->opp_count; i++) { 875 b_sft = BITS8 * (shift_byte % REG_BYTES); 876 vop = (shift_byte < REG_BYTES) ? &vop30 : 877 &vop74; 878 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); 879 shift_byte++; 880 } 881 } 882 } 883 884 if (svsb->type == SVSB_HIGH) { 885 opp_start = 0; 886 opp_stop = svsb->turn_pt; 887 } else if (svsb->type == SVSB_LOW) { 888 opp_start = svsb->turn_pt; 889 opp_stop = svsb->opp_count; 890 } 891 892 for (i = opp_start; i < opp_stop; i++) 893 if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT) 894 svsb->volt[i] -= svsb->dvt_fixed; 895 } 896 897 static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) 898 { 899 struct svs_bank *svsb = svsp->pbank; 900 u32 i, j, *freq_pct, freq_pct74 = 0, freq_pct30 = 0; 901 u32 b_sft, shift_byte = 0, turn_pt; 902 u32 middle_index = (svsb->opp_count / 2); 903 904 for (i = 0; i < svsb->opp_count; i++) { 905 if (svsb->opp_dfreq[i] <= svsb->turn_freq_base) { 906 svsb->turn_pt = i; 907 break; 908 } 909 } 910 911 turn_pt = svsb->turn_pt; 912 913 /* Target is to fill out freq_pct74 / freq_pct30 by algorithm */ 914 if (turn_pt < middle_index) { 915 if (svsb->type == SVSB_HIGH) { 916 /* 917 * If we don't handle this situation, 918 * SVSB_HIGH's FREQPCT74 / FREQPCT30 would keep "0" 919 * and this leads SVSB_LOW to work abnormally. 920 */ 921 if (turn_pt == 0) 922 freq_pct30 = svsb->freq_pct[0]; 923 924 /* freq_pct[0] ~ freq_pct[turn_pt - 1] */ 925 for (i = 0; i < turn_pt; i++) { 926 b_sft = BITS8 * (shift_byte % REG_BYTES); 927 freq_pct = (shift_byte < REG_BYTES) ? 928 &freq_pct30 : &freq_pct74; 929 *freq_pct |= (svsb->freq_pct[i] << b_sft); 930 shift_byte++; 931 } 932 } else if (svsb->type == SVSB_LOW) { 933 /* 934 * freq_pct[turn_pt] + 935 * freq_pct[opp_count - 7] ~ freq_pct[opp_count -1] 936 */ 937 freq_pct30 = svsb->freq_pct[turn_pt]; 938 shift_byte++; 939 j = svsb->opp_count - 7; 940 for (i = j; i < svsb->opp_count; i++) { 941 b_sft = BITS8 * (shift_byte % REG_BYTES); 942 freq_pct = (shift_byte < REG_BYTES) ? 943 &freq_pct30 : &freq_pct74; 944 *freq_pct |= (svsb->freq_pct[i] << b_sft); 945 shift_byte++; 946 } 947 } 948 } else { 949 if (svsb->type == SVSB_HIGH) { 950 /* 951 * freq_pct[0] + 952 * freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1] 953 */ 954 freq_pct30 = svsb->freq_pct[0]; 955 shift_byte++; 956 j = turn_pt - 7; 957 for (i = j; i < turn_pt; i++) { 958 b_sft = BITS8 * (shift_byte % REG_BYTES); 959 freq_pct = (shift_byte < REG_BYTES) ? 960 &freq_pct30 : &freq_pct74; 961 *freq_pct |= (svsb->freq_pct[i] << b_sft); 962 shift_byte++; 963 } 964 } else if (svsb->type == SVSB_LOW) { 965 /* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */ 966 for (i = turn_pt; i < svsb->opp_count; i++) { 967 b_sft = BITS8 * (shift_byte % REG_BYTES); 968 freq_pct = (shift_byte < REG_BYTES) ? 969 &freq_pct30 : &freq_pct74; 970 *freq_pct |= (svsb->freq_pct[i] << b_sft); 971 shift_byte++; 972 } 973 } 974 } 975 976 svs_writel_relaxed(svsp, freq_pct74, FREQPCT74); 977 svs_writel_relaxed(svsp, freq_pct30, FREQPCT30); 978 } 979 980 static void svs_get_bank_volts_v2(struct svs_platform *svsp) 981 { 982 struct svs_bank *svsb = svsp->pbank; 983 u32 temp, i; 984 985 temp = svs_readl_relaxed(svsp, VOP74); 986 svsb->volt[14] = (temp >> 24) & GENMASK(7, 0); 987 svsb->volt[12] = (temp >> 16) & GENMASK(7, 0); 988 svsb->volt[10] = (temp >> 8) & GENMASK(7, 0); 989 svsb->volt[8] = (temp & GENMASK(7, 0)); 990 991 temp = svs_readl_relaxed(svsp, VOP30); 992 svsb->volt[6] = (temp >> 24) & GENMASK(7, 0); 993 svsb->volt[4] = (temp >> 16) & GENMASK(7, 0); 994 svsb->volt[2] = (temp >> 8) & GENMASK(7, 0); 995 svsb->volt[0] = (temp & GENMASK(7, 0)); 996 997 for (i = 0; i <= 12; i += 2) 998 svsb->volt[i + 1] = interpolate(svsb->freq_pct[i], 999 svsb->freq_pct[i + 2], 1000 svsb->volt[i], 1001 svsb->volt[i + 2], 1002 svsb->freq_pct[i + 1]); 1003 1004 svsb->volt[15] = interpolate(svsb->freq_pct[12], 1005 svsb->freq_pct[14], 1006 svsb->volt[12], 1007 svsb->volt[14], 1008 svsb->freq_pct[15]); 1009 1010 for (i = 0; i < svsb->opp_count; i++) 1011 svsb->volt[i] += svsb->volt_od; 1012 } 1013 1014 static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp) 1015 { 1016 struct svs_bank *svsb = svsp->pbank; 1017 1018 svs_writel_relaxed(svsp, 1019 (svsb->freq_pct[14] << 24) | 1020 (svsb->freq_pct[12] << 16) | 1021 (svsb->freq_pct[10] << 8) | 1022 svsb->freq_pct[8], 1023 FREQPCT74); 1024 1025 svs_writel_relaxed(svsp, 1026 (svsb->freq_pct[6] << 24) | 1027 (svsb->freq_pct[4] << 16) | 1028 (svsb->freq_pct[2] << 8) | 1029 svsb->freq_pct[0], 1030 FREQPCT30); 1031 } 1032 1033 static void svs_set_bank_phase(struct svs_platform *svsp, 1034 enum svsb_phase target_phase) 1035 { 1036 struct svs_bank *svsb = svsp->pbank; 1037 u32 des_char, temp_char, det_char, limit_vals, init2vals, ts_calcs; 1038 1039 svs_switch_bank(svsp); 1040 1041 des_char = (svsb->bdes << 8) | svsb->mdes; 1042 svs_writel_relaxed(svsp, des_char, DESCHAR); 1043 1044 temp_char = (svsb->vco << 16) | (svsb->mtdes << 8) | svsb->dvt_fixed; 1045 svs_writel_relaxed(svsp, temp_char, TEMPCHAR); 1046 1047 det_char = (svsb->dcbdet << 8) | svsb->dcmdet; 1048 svs_writel_relaxed(svsp, det_char, DETCHAR); 1049 1050 svs_writel_relaxed(svsp, svsb->dc_config, DCCONFIG); 1051 svs_writel_relaxed(svsp, svsb->age_config, AGECONFIG); 1052 svs_writel_relaxed(svsp, SVSB_RUNCONFIG_DEFAULT, RUNCONFIG); 1053 1054 svsb->set_freq_pct(svsp); 1055 1056 limit_vals = (svsb->vmax << 24) | (svsb->vmin << 16) | 1057 (SVSB_DTHI << 8) | SVSB_DTLO; 1058 svs_writel_relaxed(svsp, limit_vals, LIMITVALS); 1059 1060 svs_writel_relaxed(svsp, SVSB_DET_WINDOW, DETWINDOW); 1061 svs_writel_relaxed(svsp, SVSB_DET_MAX, CONFIG); 1062 svs_writel_relaxed(svsp, svsb->chk_shift, CHKSHIFT); 1063 svs_writel_relaxed(svsp, svsb->ctl0, CTL0); 1064 svs_writel_relaxed(svsp, SVSB_INTSTS_CLEAN, INTSTS); 1065 1066 switch (target_phase) { 1067 case SVSB_PHASE_INIT01: 1068 svs_writel_relaxed(svsp, svsb->vboot, VBOOT); 1069 svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN); 1070 svs_writel_relaxed(svsp, SVSB_EN_INIT01, SVSEN); 1071 break; 1072 case SVSB_PHASE_INIT02: 1073 svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN); 1074 init2vals = (svsb->age_voffset_in << 16) | svsb->dc_voffset_in; 1075 svs_writel_relaxed(svsp, init2vals, INIT2VALS); 1076 svs_writel_relaxed(svsp, SVSB_EN_INIT02, SVSEN); 1077 break; 1078 case SVSB_PHASE_MON: 1079 ts_calcs = (svsb->bts << 12) | svsb->mts; 1080 svs_writel_relaxed(svsp, ts_calcs, TSCALCS); 1081 svs_writel_relaxed(svsp, SVSB_INTEN_MONVOPEN, INTEN); 1082 svs_writel_relaxed(svsp, SVSB_EN_MON, SVSEN); 1083 break; 1084 default: 1085 dev_err(svsb->dev, "requested unknown target phase: %u\n", 1086 target_phase); 1087 break; 1088 } 1089 } 1090 1091 static inline void svs_save_bank_register_data(struct svs_platform *svsp, 1092 enum svsb_phase phase) 1093 { 1094 struct svs_bank *svsb = svsp->pbank; 1095 enum svs_reg_index rg_i; 1096 1097 for (rg_i = DESCHAR; rg_i < SVS_REG_MAX; rg_i++) 1098 svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i); 1099 } 1100 1101 static inline void svs_error_isr_handler(struct svs_platform *svsp) 1102 { 1103 struct svs_bank *svsb = svsp->pbank; 1104 1105 dev_err(svsb->dev, "%s: CORESEL = 0x%08x\n", 1106 __func__, svs_readl_relaxed(svsp, CORESEL)); 1107 dev_err(svsb->dev, "SVSEN = 0x%08x, INTSTS = 0x%08x\n", 1108 svs_readl_relaxed(svsp, SVSEN), 1109 svs_readl_relaxed(svsp, INTSTS)); 1110 dev_err(svsb->dev, "SMSTATE0 = 0x%08x, SMSTATE1 = 0x%08x\n", 1111 svs_readl_relaxed(svsp, SMSTATE0), 1112 svs_readl_relaxed(svsp, SMSTATE1)); 1113 dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP)); 1114 1115 svs_save_bank_register_data(svsp, SVSB_PHASE_ERROR); 1116 1117 svsb->phase = SVSB_PHASE_ERROR; 1118 svs_writel_relaxed(svsp, SVSB_EN_OFF, SVSEN); 1119 svs_writel_relaxed(svsp, SVSB_INTSTS_CLEAN, INTSTS); 1120 } 1121 1122 static inline void svs_init01_isr_handler(struct svs_platform *svsp) 1123 { 1124 struct svs_bank *svsb = svsp->pbank; 1125 1126 dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n", 1127 __func__, svs_readl_relaxed(svsp, VDESIGN74), 1128 svs_readl_relaxed(svsp, VDESIGN30), 1129 svs_readl_relaxed(svsp, DCVALUES)); 1130 1131 svs_save_bank_register_data(svsp, SVSB_PHASE_INIT01); 1132 1133 svsb->phase = SVSB_PHASE_INIT01; 1134 svsb->dc_voffset_in = ~(svs_readl_relaxed(svsp, DCVALUES) & 1135 GENMASK(15, 0)) + 1; 1136 if (svsb->volt_flags & SVSB_INIT01_VOLT_IGNORE || 1137 (svsb->dc_voffset_in & SVSB_DC_SIGNED_BIT && 1138 svsb->volt_flags & SVSB_INIT01_VOLT_INC_ONLY)) 1139 svsb->dc_voffset_in = 0; 1140 1141 svsb->age_voffset_in = svs_readl_relaxed(svsp, AGEVALUES) & 1142 GENMASK(15, 0); 1143 1144 svs_writel_relaxed(svsp, SVSB_EN_OFF, SVSEN); 1145 svs_writel_relaxed(svsp, SVSB_INTSTS_COMPLETE, INTSTS); 1146 svsb->core_sel &= ~SVSB_DET_CLK_EN; 1147 } 1148 1149 static inline void svs_init02_isr_handler(struct svs_platform *svsp) 1150 { 1151 struct svs_bank *svsb = svsp->pbank; 1152 1153 dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n", 1154 __func__, svs_readl_relaxed(svsp, VOP74), 1155 svs_readl_relaxed(svsp, VOP30), 1156 svs_readl_relaxed(svsp, DCVALUES)); 1157 1158 svs_save_bank_register_data(svsp, SVSB_PHASE_INIT02); 1159 1160 svsb->phase = SVSB_PHASE_INIT02; 1161 svsb->get_volts(svsp); 1162 1163 svs_writel_relaxed(svsp, SVSB_EN_OFF, SVSEN); 1164 svs_writel_relaxed(svsp, SVSB_INTSTS_COMPLETE, INTSTS); 1165 } 1166 1167 static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp) 1168 { 1169 struct svs_bank *svsb = svsp->pbank; 1170 1171 svs_save_bank_register_data(svsp, SVSB_PHASE_MON); 1172 1173 svsb->phase = SVSB_PHASE_MON; 1174 svsb->get_volts(svsp); 1175 1176 svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0); 1177 svs_writel_relaxed(svsp, SVSB_INTSTS_MONVOP, INTSTS); 1178 } 1179 1180 static irqreturn_t svs_isr(int irq, void *data) 1181 { 1182 struct svs_platform *svsp = data; 1183 struct svs_bank *svsb = NULL; 1184 unsigned long flags; 1185 u32 idx, int_sts, svs_en; 1186 1187 for (idx = 0; idx < svsp->bank_max; idx++) { 1188 svsb = &svsp->banks[idx]; 1189 WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name); 1190 1191 spin_lock_irqsave(&svs_lock, flags); 1192 svsp->pbank = svsb; 1193 1194 /* Find out which svs bank fires interrupt */ 1195 if (svsb->int_st & svs_readl_relaxed(svsp, INTST)) { 1196 spin_unlock_irqrestore(&svs_lock, flags); 1197 continue; 1198 } 1199 1200 svs_switch_bank(svsp); 1201 int_sts = svs_readl_relaxed(svsp, INTSTS); 1202 svs_en = svs_readl_relaxed(svsp, SVSEN); 1203 1204 if (int_sts == SVSB_INTSTS_COMPLETE && 1205 svs_en == SVSB_EN_INIT01) 1206 svs_init01_isr_handler(svsp); 1207 else if (int_sts == SVSB_INTSTS_COMPLETE && 1208 svs_en == SVSB_EN_INIT02) 1209 svs_init02_isr_handler(svsp); 1210 else if (int_sts & SVSB_INTSTS_MONVOP) 1211 svs_mon_mode_isr_handler(svsp); 1212 else 1213 svs_error_isr_handler(svsp); 1214 1215 spin_unlock_irqrestore(&svs_lock, flags); 1216 break; 1217 } 1218 1219 svs_adjust_pm_opp_volts(svsb); 1220 1221 if (svsb->phase == SVSB_PHASE_INIT01 || 1222 svsb->phase == SVSB_PHASE_INIT02) 1223 complete(&svsb->init_completion); 1224 1225 return IRQ_HANDLED; 1226 } 1227 1228 static int svs_init01(struct svs_platform *svsp) 1229 { 1230 struct svs_bank *svsb; 1231 unsigned long flags, time_left; 1232 bool search_done; 1233 int ret = 0, r; 1234 u32 opp_freq, opp_vboot, buck_volt, idx, i; 1235 1236 /* Keep CPUs' core power on for svs_init01 initialization */ 1237 cpuidle_pause_and_lock(); 1238 1239 /* Svs bank init01 preparation - power enable */ 1240 for (idx = 0; idx < svsp->bank_max; idx++) { 1241 svsb = &svsp->banks[idx]; 1242 1243 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1244 continue; 1245 1246 ret = regulator_enable(svsb->buck); 1247 if (ret) { 1248 dev_err(svsb->dev, "%s enable fail: %d\n", 1249 svsb->buck_name, ret); 1250 goto svs_init01_resume_cpuidle; 1251 } 1252 1253 /* Some buck doesn't support mode change. Show fail msg only */ 1254 ret = regulator_set_mode(svsb->buck, REGULATOR_MODE_FAST); 1255 if (ret) 1256 dev_notice(svsb->dev, "set fast mode fail: %d\n", ret); 1257 1258 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) { 1259 if (!pm_runtime_enabled(svsb->opp_dev)) { 1260 pm_runtime_enable(svsb->opp_dev); 1261 svsb->pm_runtime_enabled_count++; 1262 } 1263 1264 ret = pm_runtime_get_sync(svsb->opp_dev); 1265 if (ret < 0) { 1266 dev_err(svsb->dev, "mtcmos on fail: %d\n", ret); 1267 goto svs_init01_resume_cpuidle; 1268 } 1269 } 1270 } 1271 1272 /* 1273 * Svs bank init01 preparation - vboot voltage adjustment 1274 * Sometimes two svs banks use the same buck. Therefore, 1275 * we have to set each svs bank to target voltage(vboot) first. 1276 */ 1277 for (idx = 0; idx < svsp->bank_max; idx++) { 1278 svsb = &svsp->banks[idx]; 1279 1280 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1281 continue; 1282 1283 /* 1284 * Find the fastest freq that can be run at vboot and 1285 * fix to that freq until svs_init01 is done. 1286 */ 1287 search_done = false; 1288 opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, 1289 svsb->volt_step, 1290 svsb->volt_base); 1291 1292 for (i = 0; i < svsb->opp_count; i++) { 1293 opp_freq = svsb->opp_dfreq[i]; 1294 if (!search_done && svsb->opp_dvolt[i] <= opp_vboot) { 1295 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev, 1296 opp_freq, 1297 opp_vboot, 1298 opp_vboot, 1299 opp_vboot); 1300 if (ret) { 1301 dev_err(svsb->dev, 1302 "set opp %uuV vboot fail: %d\n", 1303 opp_vboot, ret); 1304 goto svs_init01_finish; 1305 } 1306 1307 search_done = true; 1308 } else { 1309 ret = dev_pm_opp_disable(svsb->opp_dev, 1310 svsb->opp_dfreq[i]); 1311 if (ret) { 1312 dev_err(svsb->dev, 1313 "opp %uHz disable fail: %d\n", 1314 svsb->opp_dfreq[i], ret); 1315 goto svs_init01_finish; 1316 } 1317 } 1318 } 1319 } 1320 1321 /* Svs bank init01 begins */ 1322 for (idx = 0; idx < svsp->bank_max; idx++) { 1323 svsb = &svsp->banks[idx]; 1324 1325 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1326 continue; 1327 1328 opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, 1329 svsb->volt_step, 1330 svsb->volt_base); 1331 1332 buck_volt = regulator_get_voltage(svsb->buck); 1333 if (buck_volt != opp_vboot) { 1334 dev_err(svsb->dev, 1335 "buck voltage: %uuV, expected vboot: %uuV\n", 1336 buck_volt, opp_vboot); 1337 ret = -EPERM; 1338 goto svs_init01_finish; 1339 } 1340 1341 spin_lock_irqsave(&svs_lock, flags); 1342 svsp->pbank = svsb; 1343 svs_set_bank_phase(svsp, SVSB_PHASE_INIT01); 1344 spin_unlock_irqrestore(&svs_lock, flags); 1345 1346 time_left = wait_for_completion_timeout(&svsb->init_completion, 1347 msecs_to_jiffies(5000)); 1348 if (!time_left) { 1349 dev_err(svsb->dev, "init01 completion timeout\n"); 1350 ret = -EBUSY; 1351 goto svs_init01_finish; 1352 } 1353 } 1354 1355 svs_init01_finish: 1356 for (idx = 0; idx < svsp->bank_max; idx++) { 1357 svsb = &svsp->banks[idx]; 1358 1359 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1360 continue; 1361 1362 for (i = 0; i < svsb->opp_count; i++) { 1363 r = dev_pm_opp_enable(svsb->opp_dev, 1364 svsb->opp_dfreq[i]); 1365 if (r) 1366 dev_err(svsb->dev, "opp %uHz enable fail: %d\n", 1367 svsb->opp_dfreq[i], r); 1368 } 1369 1370 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) { 1371 r = pm_runtime_put_sync(svsb->opp_dev); 1372 if (r) 1373 dev_err(svsb->dev, "mtcmos off fail: %d\n", r); 1374 1375 if (svsb->pm_runtime_enabled_count > 0) { 1376 pm_runtime_disable(svsb->opp_dev); 1377 svsb->pm_runtime_enabled_count--; 1378 } 1379 } 1380 1381 r = regulator_set_mode(svsb->buck, REGULATOR_MODE_NORMAL); 1382 if (r) 1383 dev_notice(svsb->dev, "set normal mode fail: %d\n", r); 1384 1385 r = regulator_disable(svsb->buck); 1386 if (r) 1387 dev_err(svsb->dev, "%s disable fail: %d\n", 1388 svsb->buck_name, r); 1389 } 1390 1391 svs_init01_resume_cpuidle: 1392 cpuidle_resume_and_unlock(); 1393 1394 return ret; 1395 } 1396 1397 static int svs_init02(struct svs_platform *svsp) 1398 { 1399 struct svs_bank *svsb; 1400 unsigned long flags, time_left; 1401 u32 idx; 1402 1403 for (idx = 0; idx < svsp->bank_max; idx++) { 1404 svsb = &svsp->banks[idx]; 1405 1406 if (!(svsb->mode_support & SVSB_MODE_INIT02)) 1407 continue; 1408 1409 reinit_completion(&svsb->init_completion); 1410 spin_lock_irqsave(&svs_lock, flags); 1411 svsp->pbank = svsb; 1412 svs_set_bank_phase(svsp, SVSB_PHASE_INIT02); 1413 spin_unlock_irqrestore(&svs_lock, flags); 1414 1415 time_left = wait_for_completion_timeout(&svsb->init_completion, 1416 msecs_to_jiffies(5000)); 1417 if (!time_left) { 1418 dev_err(svsb->dev, "init02 completion timeout\n"); 1419 return -EBUSY; 1420 } 1421 } 1422 1423 /* 1424 * 2-line high/low bank update its corresponding opp voltages only. 1425 * Therefore, we sync voltages from opp for high/low bank voltages 1426 * consistency. 1427 */ 1428 for (idx = 0; idx < svsp->bank_max; idx++) { 1429 svsb = &svsp->banks[idx]; 1430 1431 if (!(svsb->mode_support & SVSB_MODE_INIT02)) 1432 continue; 1433 1434 if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) { 1435 if (svs_sync_bank_volts_from_opp(svsb)) { 1436 dev_err(svsb->dev, "sync volt fail\n"); 1437 return -EPERM; 1438 } 1439 } 1440 } 1441 1442 return 0; 1443 } 1444 1445 static void svs_mon_mode(struct svs_platform *svsp) 1446 { 1447 struct svs_bank *svsb; 1448 unsigned long flags; 1449 u32 idx; 1450 1451 for (idx = 0; idx < svsp->bank_max; idx++) { 1452 svsb = &svsp->banks[idx]; 1453 1454 if (!(svsb->mode_support & SVSB_MODE_MON)) 1455 continue; 1456 1457 spin_lock_irqsave(&svs_lock, flags); 1458 svsp->pbank = svsb; 1459 svs_set_bank_phase(svsp, SVSB_PHASE_MON); 1460 spin_unlock_irqrestore(&svs_lock, flags); 1461 } 1462 } 1463 1464 static int svs_start(struct svs_platform *svsp) 1465 { 1466 int ret; 1467 1468 ret = svs_init01(svsp); 1469 if (ret) 1470 return ret; 1471 1472 ret = svs_init02(svsp); 1473 if (ret) 1474 return ret; 1475 1476 svs_mon_mode(svsp); 1477 1478 return 0; 1479 } 1480 1481 static int svs_suspend(struct device *dev) 1482 { 1483 struct svs_platform *svsp = dev_get_drvdata(dev); 1484 struct svs_bank *svsb; 1485 unsigned long flags; 1486 int ret; 1487 u32 idx; 1488 1489 for (idx = 0; idx < svsp->bank_max; idx++) { 1490 svsb = &svsp->banks[idx]; 1491 1492 /* This might wait for svs_isr() process */ 1493 spin_lock_irqsave(&svs_lock, flags); 1494 svsp->pbank = svsb; 1495 svs_switch_bank(svsp); 1496 svs_writel_relaxed(svsp, SVSB_EN_OFF, SVSEN); 1497 svs_writel_relaxed(svsp, SVSB_INTSTS_CLEAN, INTSTS); 1498 spin_unlock_irqrestore(&svs_lock, flags); 1499 1500 svsb->phase = SVSB_PHASE_ERROR; 1501 svs_adjust_pm_opp_volts(svsb); 1502 } 1503 1504 ret = reset_control_assert(svsp->rst); 1505 if (ret) { 1506 dev_err(svsp->dev, "cannot assert reset %d\n", ret); 1507 return ret; 1508 } 1509 1510 clk_disable_unprepare(svsp->main_clk); 1511 1512 return 0; 1513 } 1514 1515 static int svs_resume(struct device *dev) 1516 { 1517 struct svs_platform *svsp = dev_get_drvdata(dev); 1518 int ret; 1519 1520 ret = clk_prepare_enable(svsp->main_clk); 1521 if (ret) { 1522 dev_err(svsp->dev, "cannot enable main_clk, disable svs\n"); 1523 return ret; 1524 } 1525 1526 ret = reset_control_deassert(svsp->rst); 1527 if (ret) { 1528 dev_err(svsp->dev, "cannot deassert reset %d\n", ret); 1529 goto out_of_resume; 1530 } 1531 1532 ret = svs_init02(svsp); 1533 if (ret) 1534 goto out_of_resume; 1535 1536 svs_mon_mode(svsp); 1537 1538 return 0; 1539 1540 out_of_resume: 1541 clk_disable_unprepare(svsp->main_clk); 1542 return ret; 1543 } 1544 1545 static int svs_bank_resource_setup(struct svs_platform *svsp) 1546 { 1547 struct svs_bank *svsb; 1548 struct dev_pm_opp *opp; 1549 unsigned long freq; 1550 int count, ret; 1551 u32 idx, i; 1552 1553 dev_set_drvdata(svsp->dev, svsp); 1554 1555 for (idx = 0; idx < svsp->bank_max; idx++) { 1556 svsb = &svsp->banks[idx]; 1557 1558 switch (svsb->sw_id) { 1559 case SVSB_CPU_LITTLE: 1560 svsb->name = "SVSB_CPU_LITTLE"; 1561 break; 1562 case SVSB_CPU_BIG: 1563 svsb->name = "SVSB_CPU_BIG"; 1564 break; 1565 case SVSB_CCI: 1566 svsb->name = "SVSB_CCI"; 1567 break; 1568 case SVSB_GPU: 1569 if (svsb->type == SVSB_HIGH) 1570 svsb->name = "SVSB_GPU_HIGH"; 1571 else if (svsb->type == SVSB_LOW) 1572 svsb->name = "SVSB_GPU_LOW"; 1573 else 1574 svsb->name = "SVSB_GPU"; 1575 break; 1576 default: 1577 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 1578 return -EINVAL; 1579 } 1580 1581 svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev), 1582 GFP_KERNEL); 1583 if (!svsb->dev) 1584 return -ENOMEM; 1585 1586 ret = dev_set_name(svsb->dev, "%s", svsb->name); 1587 if (ret) 1588 return ret; 1589 1590 dev_set_drvdata(svsb->dev, svsp); 1591 1592 ret = dev_pm_opp_of_add_table(svsb->opp_dev); 1593 if (ret) { 1594 dev_err(svsb->dev, "add opp table fail: %d\n", ret); 1595 return ret; 1596 } 1597 1598 mutex_init(&svsb->lock); 1599 init_completion(&svsb->init_completion); 1600 1601 if (svsb->mode_support & SVSB_MODE_INIT01) { 1602 svsb->buck = devm_regulator_get_optional(svsb->opp_dev, 1603 svsb->buck_name); 1604 if (IS_ERR(svsb->buck)) { 1605 dev_err(svsb->dev, "cannot get \"%s-supply\"\n", 1606 svsb->buck_name); 1607 return PTR_ERR(svsb->buck); 1608 } 1609 } 1610 1611 if (svsb->mode_support & SVSB_MODE_MON) { 1612 svsb->tzd = thermal_zone_get_zone_by_name(svsb->tzone_name); 1613 if (IS_ERR(svsb->tzd)) { 1614 dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n", 1615 svsb->tzone_name); 1616 return PTR_ERR(svsb->tzd); 1617 } 1618 } 1619 1620 count = dev_pm_opp_get_opp_count(svsb->opp_dev); 1621 if (svsb->opp_count != count) { 1622 dev_err(svsb->dev, 1623 "opp_count not \"%u\" but get \"%d\"?\n", 1624 svsb->opp_count, count); 1625 return count; 1626 } 1627 1628 for (i = 0, freq = U32_MAX; i < svsb->opp_count; i++, freq--) { 1629 opp = dev_pm_opp_find_freq_floor(svsb->opp_dev, &freq); 1630 if (IS_ERR(opp)) { 1631 dev_err(svsb->dev, "cannot find freq = %ld\n", 1632 PTR_ERR(opp)); 1633 return PTR_ERR(opp); 1634 } 1635 1636 svsb->opp_dfreq[i] = freq; 1637 svsb->opp_dvolt[i] = dev_pm_opp_get_voltage(opp); 1638 svsb->freq_pct[i] = percent(svsb->opp_dfreq[i], 1639 svsb->freq_base); 1640 dev_pm_opp_put(opp); 1641 } 1642 } 1643 1644 return 0; 1645 } 1646 1647 static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) 1648 { 1649 struct svs_bank *svsb; 1650 struct nvmem_cell *cell; 1651 u32 idx, i, vmin, golden_temp; 1652 1653 for (i = 0; i < svsp->efuse_max; i++) 1654 if (svsp->efuse[i]) 1655 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", 1656 i, svsp->efuse[i]); 1657 1658 if (!svsp->efuse[9]) { 1659 dev_notice(svsp->dev, "svs_efuse[9] = 0x0?\n"); 1660 return false; 1661 } 1662 1663 /* Svs efuse parsing */ 1664 vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0); 1665 1666 for (idx = 0; idx < svsp->bank_max; idx++) { 1667 svsb = &svsp->banks[idx]; 1668 1669 if (vmin == 0x1) 1670 svsb->vmin = 0x1e; 1671 1672 if (svsb->type == SVSB_LOW) { 1673 svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); 1674 svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); 1675 svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); 1676 svsb->dcbdet = (svsp->efuse[17]) & GENMASK(7, 0); 1677 svsb->dcmdet = (svsp->efuse[17] >> 8) & GENMASK(7, 0); 1678 } else if (svsb->type == SVSB_HIGH) { 1679 svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); 1680 svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); 1681 svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); 1682 svsb->dcbdet = (svsp->efuse[17] >> 16) & GENMASK(7, 0); 1683 svsb->dcmdet = (svsp->efuse[17] >> 24) & GENMASK(7, 0); 1684 } 1685 1686 svsb->vmax += svsb->dvt_fixed; 1687 } 1688 1689 /* Thermal efuse parsing */ 1690 cell = nvmem_cell_get(svsp->dev, "t-calibration-data"); 1691 if (IS_ERR_OR_NULL(cell)) { 1692 dev_err(svsp->dev, "no \"t-calibration-data\"? %ld\n", 1693 PTR_ERR(cell)); 1694 return false; 1695 } 1696 1697 svsp->tefuse = nvmem_cell_read(cell, &svsp->tefuse_max); 1698 if (IS_ERR(svsp->tefuse)) { 1699 dev_err(svsp->dev, "cannot read thermal efuse: %ld\n", 1700 PTR_ERR(svsp->tefuse)); 1701 nvmem_cell_put(cell); 1702 return false; 1703 } 1704 1705 svsp->tefuse_max /= sizeof(u32); 1706 nvmem_cell_put(cell); 1707 1708 for (i = 0; i < svsp->tefuse_max; i++) 1709 if (svsp->tefuse[i] != 0) 1710 break; 1711 1712 if (i == svsp->tefuse_max) 1713 golden_temp = 50; /* All thermal efuse data are 0 */ 1714 else 1715 golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); 1716 1717 for (idx = 0; idx < svsp->bank_max; idx++) { 1718 svsb = &svsp->banks[idx]; 1719 svsb->mts = 500; 1720 svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; 1721 } 1722 1723 return true; 1724 } 1725 1726 static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) 1727 { 1728 struct svs_bank *svsb; 1729 struct nvmem_cell *cell; 1730 int format[6], x_roomt[6], o_vtsmcu[5], o_vtsabb, tb_roomt = 0; 1731 int adc_ge_t, adc_oe_t, ge, oe, gain, degc_cali, adc_cali_en_t; 1732 int o_slope, o_slope_sign, ts_id; 1733 u32 idx, i, ft_pgm, mts, temp0, temp1, temp2; 1734 1735 for (i = 0; i < svsp->efuse_max; i++) 1736 if (svsp->efuse[i]) 1737 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", 1738 i, svsp->efuse[i]); 1739 1740 if (!svsp->efuse[2]) { 1741 dev_notice(svsp->dev, "svs_efuse[2] = 0x0?\n"); 1742 return false; 1743 } 1744 1745 /* Svs efuse parsing */ 1746 ft_pgm = (svsp->efuse[0] >> 4) & GENMASK(3, 0); 1747 1748 for (idx = 0; idx < svsp->bank_max; idx++) { 1749 svsb = &svsp->banks[idx]; 1750 1751 if (ft_pgm <= 1) 1752 svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; 1753 1754 switch (svsb->sw_id) { 1755 case SVSB_CPU_LITTLE: 1756 svsb->bdes = svsp->efuse[16] & GENMASK(7, 0); 1757 svsb->mdes = (svsp->efuse[16] >> 8) & GENMASK(7, 0); 1758 svsb->dcbdet = (svsp->efuse[16] >> 16) & GENMASK(7, 0); 1759 svsb->dcmdet = (svsp->efuse[16] >> 24) & GENMASK(7, 0); 1760 svsb->mtdes = (svsp->efuse[17] >> 16) & GENMASK(7, 0); 1761 1762 if (ft_pgm <= 3) 1763 svsb->volt_od += 10; 1764 else 1765 svsb->volt_od += 2; 1766 break; 1767 case SVSB_CPU_BIG: 1768 svsb->bdes = svsp->efuse[18] & GENMASK(7, 0); 1769 svsb->mdes = (svsp->efuse[18] >> 8) & GENMASK(7, 0); 1770 svsb->dcbdet = (svsp->efuse[18] >> 16) & GENMASK(7, 0); 1771 svsb->dcmdet = (svsp->efuse[18] >> 24) & GENMASK(7, 0); 1772 svsb->mtdes = svsp->efuse[17] & GENMASK(7, 0); 1773 1774 if (ft_pgm <= 3) 1775 svsb->volt_od += 15; 1776 else 1777 svsb->volt_od += 12; 1778 break; 1779 case SVSB_CCI: 1780 svsb->bdes = svsp->efuse[4] & GENMASK(7, 0); 1781 svsb->mdes = (svsp->efuse[4] >> 8) & GENMASK(7, 0); 1782 svsb->dcbdet = (svsp->efuse[4] >> 16) & GENMASK(7, 0); 1783 svsb->dcmdet = (svsp->efuse[4] >> 24) & GENMASK(7, 0); 1784 svsb->mtdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); 1785 1786 if (ft_pgm <= 3) 1787 svsb->volt_od += 10; 1788 else 1789 svsb->volt_od += 2; 1790 break; 1791 case SVSB_GPU: 1792 svsb->bdes = svsp->efuse[6] & GENMASK(7, 0); 1793 svsb->mdes = (svsp->efuse[6] >> 8) & GENMASK(7, 0); 1794 svsb->dcbdet = (svsp->efuse[6] >> 16) & GENMASK(7, 0); 1795 svsb->dcmdet = (svsp->efuse[6] >> 24) & GENMASK(7, 0); 1796 svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); 1797 1798 if (ft_pgm >= 2) { 1799 svsb->freq_base = 800000000; /* 800MHz */ 1800 svsb->dvt_fixed = 2; 1801 } 1802 break; 1803 default: 1804 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 1805 return false; 1806 } 1807 } 1808 1809 /* Get thermal efuse by nvmem */ 1810 cell = nvmem_cell_get(svsp->dev, "t-calibration-data"); 1811 if (IS_ERR(cell)) { 1812 dev_err(svsp->dev, "no \"t-calibration-data\"? %ld\n", 1813 PTR_ERR(cell)); 1814 goto remove_mt8183_svsb_mon_mode; 1815 } 1816 1817 svsp->tefuse = nvmem_cell_read(cell, &svsp->tefuse_max); 1818 if (IS_ERR(svsp->tefuse)) { 1819 dev_err(svsp->dev, "cannot read thermal efuse: %ld\n", 1820 PTR_ERR(svsp->tefuse)); 1821 nvmem_cell_put(cell); 1822 goto remove_mt8183_svsb_mon_mode; 1823 } 1824 1825 svsp->tefuse_max /= sizeof(u32); 1826 nvmem_cell_put(cell); 1827 1828 /* Thermal efuse parsing */ 1829 adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0); 1830 adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0); 1831 1832 o_vtsmcu[0] = (svsp->tefuse[0] >> 17) & GENMASK(8, 0); 1833 o_vtsmcu[1] = (svsp->tefuse[0] >> 8) & GENMASK(8, 0); 1834 o_vtsmcu[2] = svsp->tefuse[1] & GENMASK(8, 0); 1835 o_vtsmcu[3] = (svsp->tefuse[2] >> 23) & GENMASK(8, 0); 1836 o_vtsmcu[4] = (svsp->tefuse[2] >> 5) & GENMASK(8, 0); 1837 o_vtsabb = (svsp->tefuse[2] >> 14) & GENMASK(8, 0); 1838 1839 degc_cali = (svsp->tefuse[0] >> 1) & GENMASK(5, 0); 1840 adc_cali_en_t = svsp->tefuse[0] & BIT(0); 1841 o_slope_sign = (svsp->tefuse[0] >> 7) & BIT(0); 1842 1843 ts_id = (svsp->tefuse[1] >> 9) & BIT(0); 1844 o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0); 1845 1846 if (adc_cali_en_t == 1) { 1847 if (!ts_id) 1848 o_slope = 0; 1849 1850 if (adc_ge_t < 265 || adc_ge_t > 758 || 1851 adc_oe_t < 265 || adc_oe_t > 758 || 1852 o_vtsmcu[0] < -8 || o_vtsmcu[0] > 484 || 1853 o_vtsmcu[1] < -8 || o_vtsmcu[1] > 484 || 1854 o_vtsmcu[2] < -8 || o_vtsmcu[2] > 484 || 1855 o_vtsmcu[3] < -8 || o_vtsmcu[3] > 484 || 1856 o_vtsmcu[4] < -8 || o_vtsmcu[4] > 484 || 1857 o_vtsabb < -8 || o_vtsabb > 484 || 1858 degc_cali < 1 || degc_cali > 63) { 1859 dev_err(svsp->dev, "bad thermal efuse, no mon mode\n"); 1860 goto remove_mt8183_svsb_mon_mode; 1861 } 1862 } else { 1863 dev_err(svsp->dev, "no thermal efuse, no mon mode\n"); 1864 goto remove_mt8183_svsb_mon_mode; 1865 } 1866 1867 ge = ((adc_ge_t - 512) * 10000) / 4096; 1868 oe = (adc_oe_t - 512); 1869 gain = (10000 + ge); 1870 1871 format[0] = (o_vtsmcu[0] + 3350 - oe); 1872 format[1] = (o_vtsmcu[1] + 3350 - oe); 1873 format[2] = (o_vtsmcu[2] + 3350 - oe); 1874 format[3] = (o_vtsmcu[3] + 3350 - oe); 1875 format[4] = (o_vtsmcu[4] + 3350 - oe); 1876 format[5] = (o_vtsabb + 3350 - oe); 1877 1878 for (i = 0; i < 6; i++) 1879 x_roomt[i] = (((format[i] * 10000) / 4096) * 10000) / gain; 1880 1881 temp0 = (10000 * 100000 / gain) * 15 / 18; 1882 1883 if (!o_slope_sign) 1884 mts = (temp0 * 10) / (1534 + o_slope * 10); 1885 else 1886 mts = (temp0 * 10) / (1534 - o_slope * 10); 1887 1888 for (idx = 0; idx < svsp->bank_max; idx++) { 1889 svsb = &svsp->banks[idx]; 1890 svsb->mts = mts; 1891 1892 switch (svsb->sw_id) { 1893 case SVSB_CPU_LITTLE: 1894 tb_roomt = x_roomt[3]; 1895 break; 1896 case SVSB_CPU_BIG: 1897 tb_roomt = x_roomt[4]; 1898 break; 1899 case SVSB_CCI: 1900 tb_roomt = x_roomt[3]; 1901 break; 1902 case SVSB_GPU: 1903 tb_roomt = x_roomt[1]; 1904 break; 1905 default: 1906 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 1907 goto remove_mt8183_svsb_mon_mode; 1908 } 1909 1910 temp0 = (degc_cali * 10 / 2); 1911 temp1 = ((10000 * 100000 / 4096 / gain) * 1912 oe + tb_roomt * 10) * 15 / 18; 1913 1914 if (!o_slope_sign) 1915 temp2 = temp1 * 100 / (1534 + o_slope * 10); 1916 else 1917 temp2 = temp1 * 100 / (1534 - o_slope * 10); 1918 1919 svsb->bts = (temp0 + temp2 - 250) * 4 / 10; 1920 } 1921 1922 return true; 1923 1924 remove_mt8183_svsb_mon_mode: 1925 for (idx = 0; idx < svsp->bank_max; idx++) { 1926 svsb = &svsp->banks[idx]; 1927 svsb->mode_support &= ~SVSB_MODE_MON; 1928 } 1929 1930 return true; 1931 } 1932 1933 static bool svs_is_efuse_data_correct(struct svs_platform *svsp) 1934 { 1935 struct nvmem_cell *cell; 1936 1937 /* Get svs efuse by nvmem */ 1938 cell = nvmem_cell_get(svsp->dev, "svs-calibration-data"); 1939 if (IS_ERR(cell)) { 1940 dev_err(svsp->dev, "no \"svs-calibration-data\"? %ld\n", 1941 PTR_ERR(cell)); 1942 return false; 1943 } 1944 1945 svsp->efuse = nvmem_cell_read(cell, &svsp->efuse_max); 1946 if (IS_ERR(svsp->efuse)) { 1947 dev_err(svsp->dev, "cannot read svs efuse: %ld\n", 1948 PTR_ERR(svsp->efuse)); 1949 nvmem_cell_put(cell); 1950 return false; 1951 } 1952 1953 svsp->efuse_max /= sizeof(u32); 1954 nvmem_cell_put(cell); 1955 1956 return svsp->efuse_parsing(svsp); 1957 } 1958 1959 static struct device *svs_get_subsys_device(struct svs_platform *svsp, 1960 const char *node_name) 1961 { 1962 struct platform_device *pdev; 1963 struct device_node *np; 1964 1965 np = of_find_node_by_name(NULL, node_name); 1966 if (!np) { 1967 dev_err(svsp->dev, "cannot find %s node\n", node_name); 1968 return ERR_PTR(-ENODEV); 1969 } 1970 1971 pdev = of_find_device_by_node(np); 1972 if (!pdev) { 1973 of_node_put(np); 1974 dev_err(svsp->dev, "cannot find pdev by %s\n", node_name); 1975 return ERR_PTR(-ENXIO); 1976 } 1977 1978 of_node_put(np); 1979 1980 return &pdev->dev; 1981 } 1982 1983 static struct device *svs_add_device_link(struct svs_platform *svsp, 1984 const char *node_name) 1985 { 1986 struct device *dev; 1987 struct device_link *sup_link; 1988 1989 if (!node_name) { 1990 dev_err(svsp->dev, "node name cannot be null\n"); 1991 return ERR_PTR(-EINVAL); 1992 } 1993 1994 dev = svs_get_subsys_device(svsp, node_name); 1995 if (IS_ERR(dev)) 1996 return dev; 1997 1998 sup_link = device_link_add(svsp->dev, dev, 1999 DL_FLAG_AUTOREMOVE_CONSUMER); 2000 if (!sup_link) { 2001 dev_err(svsp->dev, "sup_link is NULL\n"); 2002 return ERR_PTR(-EINVAL); 2003 } 2004 2005 if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND) 2006 return ERR_PTR(-EPROBE_DEFER); 2007 2008 return dev; 2009 } 2010 2011 static int svs_mt8192_platform_probe(struct svs_platform *svsp) 2012 { 2013 struct device *dev; 2014 struct svs_bank *svsb; 2015 u32 idx; 2016 2017 svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst"); 2018 if (IS_ERR(svsp->rst)) 2019 return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), 2020 "cannot get svs reset control\n"); 2021 2022 dev = svs_add_device_link(svsp, "lvts"); 2023 if (IS_ERR(dev)) 2024 return dev_err_probe(svsp->dev, PTR_ERR(dev), 2025 "failed to get lvts device\n"); 2026 2027 for (idx = 0; idx < svsp->bank_max; idx++) { 2028 svsb = &svsp->banks[idx]; 2029 2030 if (svsb->type == SVSB_HIGH) 2031 svsb->opp_dev = svs_add_device_link(svsp, "mali"); 2032 else if (svsb->type == SVSB_LOW) 2033 svsb->opp_dev = svs_get_subsys_device(svsp, "mali"); 2034 2035 if (IS_ERR(svsb->opp_dev)) 2036 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), 2037 "failed to get OPP device for bank %d\n", 2038 idx); 2039 } 2040 2041 return 0; 2042 } 2043 2044 static int svs_mt8183_platform_probe(struct svs_platform *svsp) 2045 { 2046 struct device *dev; 2047 struct svs_bank *svsb; 2048 u32 idx; 2049 2050 dev = svs_add_device_link(svsp, "thermal"); 2051 if (IS_ERR(dev)) 2052 return dev_err_probe(svsp->dev, PTR_ERR(dev), 2053 "failed to get thermal device\n"); 2054 2055 for (idx = 0; idx < svsp->bank_max; idx++) { 2056 svsb = &svsp->banks[idx]; 2057 2058 switch (svsb->sw_id) { 2059 case SVSB_CPU_LITTLE: 2060 case SVSB_CPU_BIG: 2061 svsb->opp_dev = get_cpu_device(svsb->cpu_id); 2062 break; 2063 case SVSB_CCI: 2064 svsb->opp_dev = svs_add_device_link(svsp, "cci"); 2065 break; 2066 case SVSB_GPU: 2067 svsb->opp_dev = svs_add_device_link(svsp, "gpu"); 2068 break; 2069 default: 2070 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 2071 return -EINVAL; 2072 } 2073 2074 if (IS_ERR(svsb->opp_dev)) 2075 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), 2076 "failed to get OPP device for bank %d\n", 2077 idx); 2078 } 2079 2080 return 0; 2081 } 2082 2083 static struct svs_bank svs_mt8192_banks[] = { 2084 { 2085 .sw_id = SVSB_GPU, 2086 .type = SVSB_LOW, 2087 .set_freq_pct = svs_set_bank_freq_pct_v3, 2088 .get_volts = svs_get_bank_volts_v3, 2089 .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, 2090 .mode_support = SVSB_MODE_INIT02, 2091 .opp_count = MAX_OPP_ENTRIES, 2092 .freq_base = 688000000, 2093 .turn_freq_base = 688000000, 2094 .volt_step = 6250, 2095 .volt_base = 400000, 2096 .vmax = 0x60, 2097 .vmin = 0x1a, 2098 .age_config = 0x555555, 2099 .dc_config = 0x1, 2100 .dvt_fixed = 0x1, 2101 .vco = 0x18, 2102 .chk_shift = 0x87, 2103 .core_sel = 0x0fff0100, 2104 .int_st = BIT(0), 2105 .ctl0 = 0x00540003, 2106 }, 2107 { 2108 .sw_id = SVSB_GPU, 2109 .type = SVSB_HIGH, 2110 .set_freq_pct = svs_set_bank_freq_pct_v3, 2111 .get_volts = svs_get_bank_volts_v3, 2112 .tzone_name = "gpu1", 2113 .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | 2114 SVSB_MON_VOLT_IGNORE, 2115 .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, 2116 .opp_count = MAX_OPP_ENTRIES, 2117 .freq_base = 902000000, 2118 .turn_freq_base = 688000000, 2119 .volt_step = 6250, 2120 .volt_base = 400000, 2121 .vmax = 0x60, 2122 .vmin = 0x1a, 2123 .age_config = 0x555555, 2124 .dc_config = 0x1, 2125 .dvt_fixed = 0x6, 2126 .vco = 0x18, 2127 .chk_shift = 0x87, 2128 .core_sel = 0x0fff0101, 2129 .int_st = BIT(1), 2130 .ctl0 = 0x00540003, 2131 .tzone_htemp = 85000, 2132 .tzone_htemp_voffset = 0, 2133 .tzone_ltemp = 25000, 2134 .tzone_ltemp_voffset = 7, 2135 }, 2136 }; 2137 2138 static struct svs_bank svs_mt8183_banks[] = { 2139 { 2140 .sw_id = SVSB_CPU_LITTLE, 2141 .set_freq_pct = svs_set_bank_freq_pct_v2, 2142 .get_volts = svs_get_bank_volts_v2, 2143 .cpu_id = 0, 2144 .buck_name = "proc", 2145 .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2146 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2147 .opp_count = MAX_OPP_ENTRIES, 2148 .freq_base = 1989000000, 2149 .vboot = 0x30, 2150 .volt_step = 6250, 2151 .volt_base = 500000, 2152 .vmax = 0x64, 2153 .vmin = 0x18, 2154 .age_config = 0x555555, 2155 .dc_config = 0x555555, 2156 .dvt_fixed = 0x7, 2157 .vco = 0x10, 2158 .chk_shift = 0x77, 2159 .core_sel = 0x8fff0000, 2160 .int_st = BIT(0), 2161 .ctl0 = 0x00010001, 2162 }, 2163 { 2164 .sw_id = SVSB_CPU_BIG, 2165 .set_freq_pct = svs_set_bank_freq_pct_v2, 2166 .get_volts = svs_get_bank_volts_v2, 2167 .cpu_id = 4, 2168 .buck_name = "proc", 2169 .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2170 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2171 .opp_count = MAX_OPP_ENTRIES, 2172 .freq_base = 1989000000, 2173 .vboot = 0x30, 2174 .volt_step = 6250, 2175 .volt_base = 500000, 2176 .vmax = 0x58, 2177 .vmin = 0x10, 2178 .age_config = 0x555555, 2179 .dc_config = 0x555555, 2180 .dvt_fixed = 0x7, 2181 .vco = 0x10, 2182 .chk_shift = 0x77, 2183 .core_sel = 0x8fff0001, 2184 .int_st = BIT(1), 2185 .ctl0 = 0x00000001, 2186 }, 2187 { 2188 .sw_id = SVSB_CCI, 2189 .set_freq_pct = svs_set_bank_freq_pct_v2, 2190 .get_volts = svs_get_bank_volts_v2, 2191 .buck_name = "proc", 2192 .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2193 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2194 .opp_count = MAX_OPP_ENTRIES, 2195 .freq_base = 1196000000, 2196 .vboot = 0x30, 2197 .volt_step = 6250, 2198 .volt_base = 500000, 2199 .vmax = 0x64, 2200 .vmin = 0x18, 2201 .age_config = 0x555555, 2202 .dc_config = 0x555555, 2203 .dvt_fixed = 0x7, 2204 .vco = 0x10, 2205 .chk_shift = 0x77, 2206 .core_sel = 0x8fff0002, 2207 .int_st = BIT(2), 2208 .ctl0 = 0x00100003, 2209 }, 2210 { 2211 .sw_id = SVSB_GPU, 2212 .set_freq_pct = svs_set_bank_freq_pct_v2, 2213 .get_volts = svs_get_bank_volts_v2, 2214 .buck_name = "mali", 2215 .tzone_name = "tzts2", 2216 .volt_flags = SVSB_INIT01_PD_REQ | 2217 SVSB_INIT01_VOLT_INC_ONLY, 2218 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02 | 2219 SVSB_MODE_MON, 2220 .opp_count = MAX_OPP_ENTRIES, 2221 .freq_base = 900000000, 2222 .vboot = 0x30, 2223 .volt_step = 6250, 2224 .volt_base = 500000, 2225 .vmax = 0x40, 2226 .vmin = 0x14, 2227 .age_config = 0x555555, 2228 .dc_config = 0x555555, 2229 .dvt_fixed = 0x3, 2230 .vco = 0x10, 2231 .chk_shift = 0x77, 2232 .core_sel = 0x8fff0003, 2233 .int_st = BIT(3), 2234 .ctl0 = 0x00050001, 2235 .tzone_htemp = 85000, 2236 .tzone_htemp_voffset = 0, 2237 .tzone_ltemp = 25000, 2238 .tzone_ltemp_voffset = 3, 2239 }, 2240 }; 2241 2242 static const struct svs_platform_data svs_mt8192_platform_data = { 2243 .name = "mt8192-svs", 2244 .banks = svs_mt8192_banks, 2245 .efuse_parsing = svs_mt8192_efuse_parsing, 2246 .probe = svs_mt8192_platform_probe, 2247 .irqflags = IRQF_TRIGGER_HIGH, 2248 .regs = svs_regs_v2, 2249 .bank_max = ARRAY_SIZE(svs_mt8192_banks), 2250 }; 2251 2252 static const struct svs_platform_data svs_mt8183_platform_data = { 2253 .name = "mt8183-svs", 2254 .banks = svs_mt8183_banks, 2255 .efuse_parsing = svs_mt8183_efuse_parsing, 2256 .probe = svs_mt8183_platform_probe, 2257 .irqflags = IRQF_TRIGGER_LOW, 2258 .regs = svs_regs_v2, 2259 .bank_max = ARRAY_SIZE(svs_mt8183_banks), 2260 }; 2261 2262 static const struct of_device_id svs_of_match[] = { 2263 { 2264 .compatible = "mediatek,mt8192-svs", 2265 .data = &svs_mt8192_platform_data, 2266 }, { 2267 .compatible = "mediatek,mt8183-svs", 2268 .data = &svs_mt8183_platform_data, 2269 }, { 2270 /* Sentinel */ 2271 }, 2272 }; 2273 2274 static struct svs_platform *svs_platform_probe(struct platform_device *pdev) 2275 { 2276 struct svs_platform *svsp; 2277 const struct svs_platform_data *svsp_data; 2278 int ret; 2279 2280 svsp_data = of_device_get_match_data(&pdev->dev); 2281 if (!svsp_data) { 2282 dev_err(&pdev->dev, "no svs platform data?\n"); 2283 return ERR_PTR(-EPERM); 2284 } 2285 2286 svsp = devm_kzalloc(&pdev->dev, sizeof(*svsp), GFP_KERNEL); 2287 if (!svsp) 2288 return ERR_PTR(-ENOMEM); 2289 2290 svsp->dev = &pdev->dev; 2291 svsp->name = svsp_data->name; 2292 svsp->banks = svsp_data->banks; 2293 svsp->efuse_parsing = svsp_data->efuse_parsing; 2294 svsp->probe = svsp_data->probe; 2295 svsp->irqflags = svsp_data->irqflags; 2296 svsp->regs = svsp_data->regs; 2297 svsp->bank_max = svsp_data->bank_max; 2298 2299 ret = svsp->probe(svsp); 2300 if (ret) 2301 return ERR_PTR(ret); 2302 2303 return svsp; 2304 } 2305 2306 static int svs_probe(struct platform_device *pdev) 2307 { 2308 struct svs_platform *svsp; 2309 unsigned int svsp_irq; 2310 int ret; 2311 2312 svsp = svs_platform_probe(pdev); 2313 if (IS_ERR(svsp)) 2314 return PTR_ERR(svsp); 2315 2316 if (!svs_is_efuse_data_correct(svsp)) { 2317 dev_notice(svsp->dev, "efuse data isn't correct\n"); 2318 ret = -EPERM; 2319 goto svs_probe_free_resource; 2320 } 2321 2322 ret = svs_bank_resource_setup(svsp); 2323 if (ret) { 2324 dev_err(svsp->dev, "svs bank resource setup fail: %d\n", ret); 2325 goto svs_probe_free_resource; 2326 } 2327 2328 svsp_irq = irq_of_parse_and_map(svsp->dev->of_node, 0); 2329 ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr, 2330 svsp->irqflags | IRQF_ONESHOT, 2331 svsp->name, svsp); 2332 if (ret) { 2333 dev_err(svsp->dev, "register irq(%d) failed: %d\n", 2334 svsp_irq, ret); 2335 goto svs_probe_free_resource; 2336 } 2337 2338 svsp->main_clk = devm_clk_get(svsp->dev, "main"); 2339 if (IS_ERR(svsp->main_clk)) { 2340 dev_err(svsp->dev, "failed to get clock: %ld\n", 2341 PTR_ERR(svsp->main_clk)); 2342 ret = PTR_ERR(svsp->main_clk); 2343 goto svs_probe_free_resource; 2344 } 2345 2346 ret = clk_prepare_enable(svsp->main_clk); 2347 if (ret) { 2348 dev_err(svsp->dev, "cannot enable main clk: %d\n", ret); 2349 goto svs_probe_free_resource; 2350 } 2351 2352 svsp->base = of_iomap(svsp->dev->of_node, 0); 2353 if (IS_ERR_OR_NULL(svsp->base)) { 2354 dev_err(svsp->dev, "cannot find svs register base\n"); 2355 ret = -EINVAL; 2356 goto svs_probe_clk_disable; 2357 } 2358 2359 ret = svs_start(svsp); 2360 if (ret) { 2361 dev_err(svsp->dev, "svs start fail: %d\n", ret); 2362 goto svs_probe_iounmap; 2363 } 2364 2365 ret = svs_create_debug_cmds(svsp); 2366 if (ret) { 2367 dev_err(svsp->dev, "svs create debug cmds fail: %d\n", ret); 2368 goto svs_probe_iounmap; 2369 } 2370 2371 return 0; 2372 2373 svs_probe_iounmap: 2374 iounmap(svsp->base); 2375 2376 svs_probe_clk_disable: 2377 clk_disable_unprepare(svsp->main_clk); 2378 2379 svs_probe_free_resource: 2380 if (!IS_ERR_OR_NULL(svsp->efuse)) 2381 kfree(svsp->efuse); 2382 if (!IS_ERR_OR_NULL(svsp->tefuse)) 2383 kfree(svsp->tefuse); 2384 2385 return ret; 2386 } 2387 2388 static DEFINE_SIMPLE_DEV_PM_OPS(svs_pm_ops, svs_suspend, svs_resume); 2389 2390 static struct platform_driver svs_driver = { 2391 .probe = svs_probe, 2392 .driver = { 2393 .name = "mtk-svs", 2394 .pm = &svs_pm_ops, 2395 .of_match_table = of_match_ptr(svs_of_match), 2396 }, 2397 }; 2398 2399 module_platform_driver(svs_driver); 2400 2401 MODULE_AUTHOR("Roger Lu <roger.lu@mediatek.com>"); 2402 MODULE_DESCRIPTION("MediaTek SVS driver"); 2403 MODULE_LICENSE("GPL"); 2404