1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/bits.h> 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/cpuidle.h> 11 #include <linux/debugfs.h> 12 #include <linux/device.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/kthread.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/nvmem-consumer.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_platform.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_domain.h> 25 #include <linux/pm_opp.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/regulator/consumer.h> 28 #include <linux/reset.h> 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 #include <linux/spinlock.h> 32 #include <linux/thermal.h> 33 34 /* svs bank 1-line software id */ 35 #define SVSB_CPU_LITTLE BIT(0) 36 #define SVSB_CPU_BIG BIT(1) 37 #define SVSB_CCI BIT(2) 38 #define SVSB_GPU BIT(3) 39 40 /* svs bank 2-line type */ 41 #define SVSB_LOW BIT(8) 42 #define SVSB_HIGH BIT(9) 43 44 /* svs bank mode support */ 45 #define SVSB_MODE_ALL_DISABLE 0 46 #define SVSB_MODE_INIT01 BIT(1) 47 #define SVSB_MODE_INIT02 BIT(2) 48 #define SVSB_MODE_MON BIT(3) 49 50 /* svs bank volt flags */ 51 #define SVSB_INIT01_PD_REQ BIT(0) 52 #define SVSB_INIT01_VOLT_IGNORE BIT(1) 53 #define SVSB_INIT01_VOLT_INC_ONLY BIT(2) 54 #define SVSB_MON_VOLT_IGNORE BIT(16) 55 #define SVSB_REMOVE_DVTFIXED_VOLT BIT(24) 56 57 /* svs bank register fields and common configuration */ 58 #define SVSB_PTPCONFIG_DETMAX GENMASK(15, 0) 59 #define SVSB_DET_MAX FIELD_PREP(SVSB_PTPCONFIG_DETMAX, 0xffff) 60 #define SVSB_DET_WINDOW 0xa28 61 62 /* DESCHAR */ 63 #define SVSB_DESCHAR_FLD_MDES GENMASK(7, 0) 64 #define SVSB_DESCHAR_FLD_BDES GENMASK(15, 8) 65 66 /* TEMPCHAR */ 67 #define SVSB_TEMPCHAR_FLD_DVT_FIXED GENMASK(7, 0) 68 #define SVSB_TEMPCHAR_FLD_MTDES GENMASK(15, 8) 69 #define SVSB_TEMPCHAR_FLD_VCO GENMASK(23, 16) 70 71 /* DETCHAR */ 72 #define SVSB_DETCHAR_FLD_DCMDET GENMASK(7, 0) 73 #define SVSB_DETCHAR_FLD_DCBDET GENMASK(15, 8) 74 75 /* SVSEN (PTPEN) */ 76 #define SVSB_PTPEN_INIT01 BIT(0) 77 #define SVSB_PTPEN_MON BIT(1) 78 #define SVSB_PTPEN_INIT02 (SVSB_PTPEN_INIT01 | BIT(2)) 79 #define SVSB_PTPEN_OFF 0x0 80 81 /* FREQPCTS */ 82 #define SVSB_FREQPCTS_FLD_PCT0_4 GENMASK(7, 0) 83 #define SVSB_FREQPCTS_FLD_PCT1_5 GENMASK(15, 8) 84 #define SVSB_FREQPCTS_FLD_PCT2_6 GENMASK(23, 16) 85 #define SVSB_FREQPCTS_FLD_PCT3_7 GENMASK(31, 24) 86 87 /* INTSTS */ 88 #define SVSB_INTSTS_VAL_CLEAN 0x00ffffff 89 #define SVSB_INTSTS_F0_COMPLETE BIT(0) 90 #define SVSB_INTSTS_FLD_MONVOP GENMASK(23, 16) 91 #define SVSB_RUNCONFIG_DEFAULT 0x80000000 92 93 /* LIMITVALS */ 94 #define SVSB_LIMITVALS_FLD_DTLO GENMASK(7, 0) 95 #define SVSB_LIMITVALS_FLD_DTHI GENMASK(15, 8) 96 #define SVSB_LIMITVALS_FLD_VMIN GENMASK(23, 16) 97 #define SVSB_LIMITVALS_FLD_VMAX GENMASK(31, 24) 98 #define SVSB_VAL_DTHI 0x1 99 #define SVSB_VAL_DTLO 0xfe 100 101 /* INTEN */ 102 #define SVSB_INTEN_F0EN BIT(0) 103 #define SVSB_INTEN_DACK0UPEN BIT(8) 104 #define SVSB_INTEN_DC0EN BIT(9) 105 #define SVSB_INTEN_DC1EN BIT(10) 106 #define SVSB_INTEN_DACK0LOEN BIT(11) 107 #define SVSB_INTEN_INITPROD_OVF_EN BIT(12) 108 #define SVSB_INTEN_INITSUM_OVF_EN BIT(14) 109 #define SVSB_INTEN_MONVOPEN GENMASK(23, 16) 110 #define SVSB_INTEN_INIT0x (SVSB_INTEN_F0EN | SVSB_INTEN_DACK0UPEN | \ 111 SVSB_INTEN_DC0EN | SVSB_INTEN_DC1EN | \ 112 SVSB_INTEN_DACK0LOEN | \ 113 SVSB_INTEN_INITPROD_OVF_EN | \ 114 SVSB_INTEN_INITSUM_OVF_EN) 115 116 /* TSCALCS */ 117 #define SVSB_TSCALCS_FLD_MTS GENMASK(11, 0) 118 #define SVSB_TSCALCS_FLD_BTS GENMASK(23, 12) 119 120 /* INIT2VALS */ 121 #define SVSB_INIT2VALS_FLD_DCVOFFSETIN GENMASK(15, 0) 122 #define SVSB_INIT2VALS_FLD_AGEVOFFSETIN GENMASK(31, 16) 123 124 /* VOPS */ 125 #define SVSB_VOPS_FLD_VOP0_4 GENMASK(7, 0) 126 #define SVSB_VOPS_FLD_VOP1_5 GENMASK(15, 8) 127 #define SVSB_VOPS_FLD_VOP2_6 GENMASK(23, 16) 128 #define SVSB_VOPS_FLD_VOP3_7 GENMASK(31, 24) 129 130 /* svs bank related setting */ 131 #define BITS8 8 132 #define MAX_OPP_ENTRIES 16 133 #define REG_BYTES 4 134 #define SVSB_DC_SIGNED_BIT BIT(15) 135 #define SVSB_DET_CLK_EN BIT(31) 136 #define SVSB_TEMP_LOWER_BOUND 0xb2 137 #define SVSB_TEMP_UPPER_BOUND 0x64 138 139 static DEFINE_SPINLOCK(svs_lock); 140 141 #define debug_fops_ro(name) \ 142 static int svs_##name##_debug_open(struct inode *inode, \ 143 struct file *filp) \ 144 { \ 145 return single_open(filp, svs_##name##_debug_show, \ 146 inode->i_private); \ 147 } \ 148 static const struct file_operations svs_##name##_debug_fops = { \ 149 .owner = THIS_MODULE, \ 150 .open = svs_##name##_debug_open, \ 151 .read = seq_read, \ 152 .llseek = seq_lseek, \ 153 .release = single_release, \ 154 } 155 156 #define debug_fops_rw(name) \ 157 static int svs_##name##_debug_open(struct inode *inode, \ 158 struct file *filp) \ 159 { \ 160 return single_open(filp, svs_##name##_debug_show, \ 161 inode->i_private); \ 162 } \ 163 static const struct file_operations svs_##name##_debug_fops = { \ 164 .owner = THIS_MODULE, \ 165 .open = svs_##name##_debug_open, \ 166 .read = seq_read, \ 167 .write = svs_##name##_debug_write, \ 168 .llseek = seq_lseek, \ 169 .release = single_release, \ 170 } 171 172 #define svs_dentry_data(name) {__stringify(name), &svs_##name##_debug_fops} 173 174 /** 175 * enum svsb_phase - svs bank phase enumeration 176 * @SVSB_PHASE_ERROR: svs bank encounters unexpected condition 177 * @SVSB_PHASE_INIT01: svs bank basic init for data calibration 178 * @SVSB_PHASE_INIT02: svs bank can provide voltages to opp table 179 * @SVSB_PHASE_MON: svs bank can provide voltages with thermal effect 180 * @SVSB_PHASE_MAX: total number of svs bank phase (debug purpose) 181 * 182 * Each svs bank has its own independent phase and we enable each svs bank by 183 * running their phase orderly. However, when svs bank encounters unexpected 184 * condition, it will fire an irq (PHASE_ERROR) to inform svs software. 185 * 186 * svs bank general phase-enabled order: 187 * SVSB_PHASE_INIT01 -> SVSB_PHASE_INIT02 -> SVSB_PHASE_MON 188 */ 189 enum svsb_phase { 190 SVSB_PHASE_ERROR = 0, 191 SVSB_PHASE_INIT01, 192 SVSB_PHASE_INIT02, 193 SVSB_PHASE_MON, 194 SVSB_PHASE_MAX, 195 }; 196 197 enum svs_reg_index { 198 DESCHAR = 0, 199 TEMPCHAR, 200 DETCHAR, 201 AGECHAR, 202 DCCONFIG, 203 AGECONFIG, 204 FREQPCT30, 205 FREQPCT74, 206 LIMITVALS, 207 VBOOT, 208 DETWINDOW, 209 CONFIG, 210 TSCALCS, 211 RUNCONFIG, 212 SVSEN, 213 INIT2VALS, 214 DCVALUES, 215 AGEVALUES, 216 VOP30, 217 VOP74, 218 TEMP, 219 INTSTS, 220 INTSTSRAW, 221 INTEN, 222 CHKINT, 223 CHKSHIFT, 224 STATUS, 225 VDESIGN30, 226 VDESIGN74, 227 DVT30, 228 DVT74, 229 AGECOUNT, 230 SMSTATE0, 231 SMSTATE1, 232 CTL0, 233 DESDETSEC, 234 TEMPAGESEC, 235 CTRLSPARE0, 236 CTRLSPARE1, 237 CTRLSPARE2, 238 CTRLSPARE3, 239 CORESEL, 240 THERMINTST, 241 INTST, 242 THSTAGE0ST, 243 THSTAGE1ST, 244 THSTAGE2ST, 245 THAHBST0, 246 THAHBST1, 247 SPARE0, 248 SPARE1, 249 SPARE2, 250 SPARE3, 251 THSLPEVEB, 252 SVS_REG_MAX, 253 }; 254 255 static const u32 svs_regs_v2[] = { 256 [DESCHAR] = 0xc00, 257 [TEMPCHAR] = 0xc04, 258 [DETCHAR] = 0xc08, 259 [AGECHAR] = 0xc0c, 260 [DCCONFIG] = 0xc10, 261 [AGECONFIG] = 0xc14, 262 [FREQPCT30] = 0xc18, 263 [FREQPCT74] = 0xc1c, 264 [LIMITVALS] = 0xc20, 265 [VBOOT] = 0xc24, 266 [DETWINDOW] = 0xc28, 267 [CONFIG] = 0xc2c, 268 [TSCALCS] = 0xc30, 269 [RUNCONFIG] = 0xc34, 270 [SVSEN] = 0xc38, 271 [INIT2VALS] = 0xc3c, 272 [DCVALUES] = 0xc40, 273 [AGEVALUES] = 0xc44, 274 [VOP30] = 0xc48, 275 [VOP74] = 0xc4c, 276 [TEMP] = 0xc50, 277 [INTSTS] = 0xc54, 278 [INTSTSRAW] = 0xc58, 279 [INTEN] = 0xc5c, 280 [CHKINT] = 0xc60, 281 [CHKSHIFT] = 0xc64, 282 [STATUS] = 0xc68, 283 [VDESIGN30] = 0xc6c, 284 [VDESIGN74] = 0xc70, 285 [DVT30] = 0xc74, 286 [DVT74] = 0xc78, 287 [AGECOUNT] = 0xc7c, 288 [SMSTATE0] = 0xc80, 289 [SMSTATE1] = 0xc84, 290 [CTL0] = 0xc88, 291 [DESDETSEC] = 0xce0, 292 [TEMPAGESEC] = 0xce4, 293 [CTRLSPARE0] = 0xcf0, 294 [CTRLSPARE1] = 0xcf4, 295 [CTRLSPARE2] = 0xcf8, 296 [CTRLSPARE3] = 0xcfc, 297 [CORESEL] = 0xf00, 298 [THERMINTST] = 0xf04, 299 [INTST] = 0xf08, 300 [THSTAGE0ST] = 0xf0c, 301 [THSTAGE1ST] = 0xf10, 302 [THSTAGE2ST] = 0xf14, 303 [THAHBST0] = 0xf18, 304 [THAHBST1] = 0xf1c, 305 [SPARE0] = 0xf20, 306 [SPARE1] = 0xf24, 307 [SPARE2] = 0xf28, 308 [SPARE3] = 0xf2c, 309 [THSLPEVEB] = 0xf30, 310 }; 311 312 /** 313 * struct svs_platform - svs platform control 314 * @name: svs platform name 315 * @base: svs platform register base 316 * @dev: svs platform device 317 * @main_clk: main clock for svs bank 318 * @pbank: svs bank pointer needing to be protected by spin_lock section 319 * @banks: svs banks that svs platform supports 320 * @rst: svs platform reset control 321 * @efuse_parsing: svs platform efuse parsing function pointer 322 * @probe: svs platform probe function pointer 323 * @efuse_max: total number of svs efuse 324 * @tefuse_max: total number of thermal efuse 325 * @regs: svs platform registers map 326 * @bank_max: total number of svs banks 327 * @efuse: svs efuse data received from NVMEM framework 328 * @tefuse: thermal efuse data received from NVMEM framework 329 */ 330 struct svs_platform { 331 char *name; 332 void __iomem *base; 333 struct device *dev; 334 struct clk *main_clk; 335 struct svs_bank *pbank; 336 struct svs_bank *banks; 337 struct reset_control *rst; 338 bool (*efuse_parsing)(struct svs_platform *svsp); 339 int (*probe)(struct svs_platform *svsp); 340 size_t efuse_max; 341 size_t tefuse_max; 342 const u32 *regs; 343 u32 bank_max; 344 u32 *efuse; 345 u32 *tefuse; 346 }; 347 348 struct svs_platform_data { 349 char *name; 350 struct svs_bank *banks; 351 bool (*efuse_parsing)(struct svs_platform *svsp); 352 int (*probe)(struct svs_platform *svsp); 353 const u32 *regs; 354 u32 bank_max; 355 }; 356 357 /** 358 * struct svs_bank - svs bank representation 359 * @dev: bank device 360 * @opp_dev: device for opp table/buck control 361 * @init_completion: the timeout completion for bank init 362 * @buck: regulator used by opp_dev 363 * @tzd: thermal zone device for getting temperature 364 * @lock: mutex lock to protect voltage update process 365 * @set_freq_pct: function pointer to set bank frequency percent table 366 * @get_volts: function pointer to get bank voltages 367 * @name: bank name 368 * @buck_name: regulator name 369 * @tzone_name: thermal zone name 370 * @phase: bank current phase 371 * @volt_od: bank voltage overdrive 372 * @reg_data: bank register data in different phase for debug purpose 373 * @pm_runtime_enabled_count: bank pm runtime enabled count 374 * @mode_support: bank mode support. 375 * @freq_base: reference frequency for bank init 376 * @turn_freq_base: refenrece frequency for 2-line turn point 377 * @vboot: voltage request for bank init01 only 378 * @opp_dfreq: default opp frequency table 379 * @opp_dvolt: default opp voltage table 380 * @freq_pct: frequency percent table for bank init 381 * @volt: bank voltage table 382 * @volt_step: bank voltage step 383 * @volt_base: bank voltage base 384 * @volt_flags: bank voltage flags 385 * @vmax: bank voltage maximum 386 * @vmin: bank voltage minimum 387 * @age_config: bank age configuration 388 * @age_voffset_in: bank age voltage offset 389 * @dc_config: bank dc configuration 390 * @dc_voffset_in: bank dc voltage offset 391 * @dvt_fixed: bank dvt fixed value 392 * @vco: bank VCO value 393 * @chk_shift: bank chicken shift 394 * @core_sel: bank selection 395 * @opp_count: bank opp count 396 * @int_st: bank interrupt identification 397 * @sw_id: bank software identification 398 * @cpu_id: cpu core id for SVS CPU bank use only 399 * @ctl0: TS-x selection 400 * @temp: bank temperature 401 * @tzone_htemp: thermal zone high temperature threshold 402 * @tzone_htemp_voffset: thermal zone high temperature voltage offset 403 * @tzone_ltemp: thermal zone low temperature threshold 404 * @tzone_ltemp_voffset: thermal zone low temperature voltage offset 405 * @bts: svs efuse data 406 * @mts: svs efuse data 407 * @bdes: svs efuse data 408 * @mdes: svs efuse data 409 * @mtdes: svs efuse data 410 * @dcbdet: svs efuse data 411 * @dcmdet: svs efuse data 412 * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank 413 * @type: bank type to represent it is 2-line (high/low) bank or 1-line bank 414 * 415 * Svs bank will generate suitalbe voltages by below general math equation 416 * and provide these voltages to opp voltage table. 417 * 418 * opp_volt[i] = (volt[i] * volt_step) + volt_base; 419 */ 420 struct svs_bank { 421 struct device *dev; 422 struct device *opp_dev; 423 struct completion init_completion; 424 struct regulator *buck; 425 struct thermal_zone_device *tzd; 426 struct mutex lock; /* lock to protect voltage update process */ 427 void (*set_freq_pct)(struct svs_platform *svsp); 428 void (*get_volts)(struct svs_platform *svsp); 429 char *name; 430 char *buck_name; 431 char *tzone_name; 432 enum svsb_phase phase; 433 s32 volt_od; 434 u32 reg_data[SVSB_PHASE_MAX][SVS_REG_MAX]; 435 u32 pm_runtime_enabled_count; 436 u32 mode_support; 437 u32 freq_base; 438 u32 turn_freq_base; 439 u32 vboot; 440 u32 opp_dfreq[MAX_OPP_ENTRIES]; 441 u32 opp_dvolt[MAX_OPP_ENTRIES]; 442 u32 freq_pct[MAX_OPP_ENTRIES]; 443 u32 volt[MAX_OPP_ENTRIES]; 444 u32 volt_step; 445 u32 volt_base; 446 u32 volt_flags; 447 u32 vmax; 448 u32 vmin; 449 u32 age_config; 450 u32 age_voffset_in; 451 u32 dc_config; 452 u32 dc_voffset_in; 453 u32 dvt_fixed; 454 u32 vco; 455 u32 chk_shift; 456 u32 core_sel; 457 u32 opp_count; 458 u32 int_st; 459 u32 sw_id; 460 u32 cpu_id; 461 u32 ctl0; 462 u32 temp; 463 u32 tzone_htemp; 464 u32 tzone_htemp_voffset; 465 u32 tzone_ltemp; 466 u32 tzone_ltemp_voffset; 467 u32 bts; 468 u32 mts; 469 u32 bdes; 470 u32 mdes; 471 u32 mtdes; 472 u32 dcbdet; 473 u32 dcmdet; 474 u32 turn_pt; 475 u32 type; 476 }; 477 478 static u32 percent(u32 numerator, u32 denominator) 479 { 480 /* If not divide 1000, "numerator * 100" will have data overflow. */ 481 numerator /= 1000; 482 denominator /= 1000; 483 484 return DIV_ROUND_UP(numerator * 100, denominator); 485 } 486 487 static u32 svs_readl_relaxed(struct svs_platform *svsp, enum svs_reg_index rg_i) 488 { 489 return readl_relaxed(svsp->base + svsp->regs[rg_i]); 490 } 491 492 static void svs_writel_relaxed(struct svs_platform *svsp, u32 val, 493 enum svs_reg_index rg_i) 494 { 495 writel_relaxed(val, svsp->base + svsp->regs[rg_i]); 496 } 497 498 static void svs_switch_bank(struct svs_platform *svsp) 499 { 500 struct svs_bank *svsb = svsp->pbank; 501 502 svs_writel_relaxed(svsp, svsb->core_sel, CORESEL); 503 } 504 505 static u32 svs_bank_volt_to_opp_volt(u32 svsb_volt, u32 svsb_volt_step, 506 u32 svsb_volt_base) 507 { 508 return (svsb_volt * svsb_volt_step) + svsb_volt_base; 509 } 510 511 static u32 svs_opp_volt_to_bank_volt(u32 opp_u_volt, u32 svsb_volt_step, 512 u32 svsb_volt_base) 513 { 514 return (opp_u_volt - svsb_volt_base) / svsb_volt_step; 515 } 516 517 static int svs_sync_bank_volts_from_opp(struct svs_bank *svsb) 518 { 519 struct dev_pm_opp *opp; 520 u32 i, opp_u_volt; 521 522 for (i = 0; i < svsb->opp_count; i++) { 523 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, 524 svsb->opp_dfreq[i], 525 true); 526 if (IS_ERR(opp)) { 527 dev_err(svsb->dev, "cannot find freq = %u (%ld)\n", 528 svsb->opp_dfreq[i], PTR_ERR(opp)); 529 return PTR_ERR(opp); 530 } 531 532 opp_u_volt = dev_pm_opp_get_voltage(opp); 533 svsb->volt[i] = svs_opp_volt_to_bank_volt(opp_u_volt, 534 svsb->volt_step, 535 svsb->volt_base); 536 dev_pm_opp_put(opp); 537 } 538 539 return 0; 540 } 541 542 static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) 543 { 544 int ret = -EPERM, tzone_temp = 0; 545 u32 i, svsb_volt, opp_volt, temp_voffset = 0, opp_start, opp_stop; 546 547 mutex_lock(&svsb->lock); 548 549 /* 550 * 2-line bank updates its corresponding opp volts. 551 * 1-line bank updates all opp volts. 552 */ 553 if (svsb->type == SVSB_HIGH) { 554 opp_start = 0; 555 opp_stop = svsb->turn_pt; 556 } else if (svsb->type == SVSB_LOW) { 557 opp_start = svsb->turn_pt; 558 opp_stop = svsb->opp_count; 559 } else { 560 opp_start = 0; 561 opp_stop = svsb->opp_count; 562 } 563 564 /* Get thermal effect */ 565 if (svsb->phase == SVSB_PHASE_MON) { 566 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); 567 if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND && 568 svsb->temp < SVSB_TEMP_LOWER_BOUND)) { 569 dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n", 570 svsb->tzone_name, ret, svsb->temp); 571 svsb->phase = SVSB_PHASE_ERROR; 572 } 573 574 if (tzone_temp >= svsb->tzone_htemp) 575 temp_voffset += svsb->tzone_htemp_voffset; 576 else if (tzone_temp <= svsb->tzone_ltemp) 577 temp_voffset += svsb->tzone_ltemp_voffset; 578 579 /* 2-line bank update all opp volts when running mon mode */ 580 if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) { 581 opp_start = 0; 582 opp_stop = svsb->opp_count; 583 } 584 } 585 586 /* vmin <= svsb_volt (opp_volt) <= default opp voltage */ 587 for (i = opp_start; i < opp_stop; i++) { 588 switch (svsb->phase) { 589 case SVSB_PHASE_ERROR: 590 opp_volt = svsb->opp_dvolt[i]; 591 break; 592 case SVSB_PHASE_INIT01: 593 /* do nothing */ 594 goto unlock_mutex; 595 case SVSB_PHASE_INIT02: 596 svsb_volt = max(svsb->volt[i], svsb->vmin); 597 opp_volt = svs_bank_volt_to_opp_volt(svsb_volt, 598 svsb->volt_step, 599 svsb->volt_base); 600 break; 601 case SVSB_PHASE_MON: 602 svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin); 603 opp_volt = svs_bank_volt_to_opp_volt(svsb_volt, 604 svsb->volt_step, 605 svsb->volt_base); 606 break; 607 default: 608 dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase); 609 ret = -EINVAL; 610 goto unlock_mutex; 611 } 612 613 opp_volt = min(opp_volt, svsb->opp_dvolt[i]); 614 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev, 615 svsb->opp_dfreq[i], 616 opp_volt, opp_volt, 617 svsb->opp_dvolt[i]); 618 if (ret) { 619 dev_err(svsb->dev, "set %uuV fail: %d\n", 620 opp_volt, ret); 621 goto unlock_mutex; 622 } 623 } 624 625 unlock_mutex: 626 mutex_unlock(&svsb->lock); 627 628 return ret; 629 } 630 631 static int svs_dump_debug_show(struct seq_file *m, void *p) 632 { 633 struct svs_platform *svsp = (struct svs_platform *)m->private; 634 struct svs_bank *svsb; 635 unsigned long svs_reg_addr; 636 u32 idx, i, j, bank_id; 637 638 for (i = 0; i < svsp->efuse_max; i++) 639 if (svsp->efuse && svsp->efuse[i]) 640 seq_printf(m, "M_HW_RES%d = 0x%08x\n", 641 i, svsp->efuse[i]); 642 643 for (i = 0; i < svsp->tefuse_max; i++) 644 if (svsp->tefuse) 645 seq_printf(m, "THERMAL_EFUSE%d = 0x%08x\n", 646 i, svsp->tefuse[i]); 647 648 for (bank_id = 0, idx = 0; idx < svsp->bank_max; idx++, bank_id++) { 649 svsb = &svsp->banks[idx]; 650 651 for (i = SVSB_PHASE_INIT01; i <= SVSB_PHASE_MON; i++) { 652 seq_printf(m, "Bank_number = %u\n", bank_id); 653 654 if (i == SVSB_PHASE_INIT01 || i == SVSB_PHASE_INIT02) 655 seq_printf(m, "mode = init%d\n", i); 656 else if (i == SVSB_PHASE_MON) 657 seq_puts(m, "mode = mon\n"); 658 else 659 seq_puts(m, "mode = error\n"); 660 661 for (j = DESCHAR; j < SVS_REG_MAX; j++) { 662 svs_reg_addr = (unsigned long)(svsp->base + 663 svsp->regs[j]); 664 seq_printf(m, "0x%08lx = 0x%08x\n", 665 svs_reg_addr, svsb->reg_data[i][j]); 666 } 667 } 668 } 669 670 return 0; 671 } 672 673 debug_fops_ro(dump); 674 675 static int svs_enable_debug_show(struct seq_file *m, void *v) 676 { 677 struct svs_bank *svsb = (struct svs_bank *)m->private; 678 679 switch (svsb->phase) { 680 case SVSB_PHASE_ERROR: 681 seq_puts(m, "disabled\n"); 682 break; 683 case SVSB_PHASE_INIT01: 684 seq_puts(m, "init1\n"); 685 break; 686 case SVSB_PHASE_INIT02: 687 seq_puts(m, "init2\n"); 688 break; 689 case SVSB_PHASE_MON: 690 seq_puts(m, "mon mode\n"); 691 break; 692 default: 693 seq_puts(m, "unknown\n"); 694 break; 695 } 696 697 return 0; 698 } 699 700 static ssize_t svs_enable_debug_write(struct file *filp, 701 const char __user *buffer, 702 size_t count, loff_t *pos) 703 { 704 struct svs_bank *svsb = file_inode(filp)->i_private; 705 struct svs_platform *svsp = dev_get_drvdata(svsb->dev); 706 unsigned long flags; 707 int enabled, ret; 708 char *buf = NULL; 709 710 if (count >= PAGE_SIZE) 711 return -EINVAL; 712 713 buf = (char *)memdup_user_nul(buffer, count); 714 if (IS_ERR(buf)) 715 return PTR_ERR(buf); 716 717 ret = kstrtoint(buf, 10, &enabled); 718 if (ret) 719 return ret; 720 721 if (!enabled) { 722 spin_lock_irqsave(&svs_lock, flags); 723 svsp->pbank = svsb; 724 svsb->mode_support = SVSB_MODE_ALL_DISABLE; 725 svs_switch_bank(svsp); 726 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); 727 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); 728 spin_unlock_irqrestore(&svs_lock, flags); 729 730 svsb->phase = SVSB_PHASE_ERROR; 731 svs_adjust_pm_opp_volts(svsb); 732 } 733 734 kfree(buf); 735 736 return count; 737 } 738 739 debug_fops_rw(enable); 740 741 static int svs_status_debug_show(struct seq_file *m, void *v) 742 { 743 struct svs_bank *svsb = (struct svs_bank *)m->private; 744 struct dev_pm_opp *opp; 745 int tzone_temp = 0, ret; 746 u32 i; 747 748 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); 749 if (ret) 750 seq_printf(m, "%s: temperature ignore, turn_pt = %u\n", 751 svsb->name, svsb->turn_pt); 752 else 753 seq_printf(m, "%s: temperature = %d, turn_pt = %u\n", 754 svsb->name, tzone_temp, svsb->turn_pt); 755 756 for (i = 0; i < svsb->opp_count; i++) { 757 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, 758 svsb->opp_dfreq[i], true); 759 if (IS_ERR(opp)) { 760 seq_printf(m, "%s: cannot find freq = %u (%ld)\n", 761 svsb->name, svsb->opp_dfreq[i], 762 PTR_ERR(opp)); 763 return PTR_ERR(opp); 764 } 765 766 seq_printf(m, "opp_freq[%02u]: %u, opp_volt[%02u]: %lu, ", 767 i, svsb->opp_dfreq[i], i, 768 dev_pm_opp_get_voltage(opp)); 769 seq_printf(m, "svsb_volt[%02u]: 0x%x, freq_pct[%02u]: %u\n", 770 i, svsb->volt[i], i, svsb->freq_pct[i]); 771 dev_pm_opp_put(opp); 772 } 773 774 return 0; 775 } 776 777 debug_fops_ro(status); 778 779 static int svs_create_debug_cmds(struct svs_platform *svsp) 780 { 781 struct svs_bank *svsb; 782 struct dentry *svs_dir, *svsb_dir, *file_entry; 783 const char *d = "/sys/kernel/debug/svs"; 784 u32 i, idx; 785 786 struct svs_dentry { 787 const char *name; 788 const struct file_operations *fops; 789 }; 790 791 struct svs_dentry svs_entries[] = { 792 svs_dentry_data(dump), 793 }; 794 795 struct svs_dentry svsb_entries[] = { 796 svs_dentry_data(enable), 797 svs_dentry_data(status), 798 }; 799 800 svs_dir = debugfs_create_dir("svs", NULL); 801 if (IS_ERR(svs_dir)) { 802 dev_err(svsp->dev, "cannot create %s: %ld\n", 803 d, PTR_ERR(svs_dir)); 804 return PTR_ERR(svs_dir); 805 } 806 807 for (i = 0; i < ARRAY_SIZE(svs_entries); i++) { 808 file_entry = debugfs_create_file(svs_entries[i].name, 0664, 809 svs_dir, svsp, 810 svs_entries[i].fops); 811 if (IS_ERR(file_entry)) { 812 dev_err(svsp->dev, "cannot create %s/%s: %ld\n", 813 d, svs_entries[i].name, PTR_ERR(file_entry)); 814 return PTR_ERR(file_entry); 815 } 816 } 817 818 for (idx = 0; idx < svsp->bank_max; idx++) { 819 svsb = &svsp->banks[idx]; 820 821 if (svsb->mode_support == SVSB_MODE_ALL_DISABLE) 822 continue; 823 824 svsb_dir = debugfs_create_dir(svsb->name, svs_dir); 825 if (IS_ERR(svsb_dir)) { 826 dev_err(svsp->dev, "cannot create %s/%s: %ld\n", 827 d, svsb->name, PTR_ERR(svsb_dir)); 828 return PTR_ERR(svsb_dir); 829 } 830 831 for (i = 0; i < ARRAY_SIZE(svsb_entries); i++) { 832 file_entry = debugfs_create_file(svsb_entries[i].name, 833 0664, svsb_dir, svsb, 834 svsb_entries[i].fops); 835 if (IS_ERR(file_entry)) { 836 dev_err(svsp->dev, "no %s/%s/%s?: %ld\n", 837 d, svsb->name, svsb_entries[i].name, 838 PTR_ERR(file_entry)); 839 return PTR_ERR(file_entry); 840 } 841 } 842 } 843 844 return 0; 845 } 846 847 static u32 interpolate(u32 f0, u32 f1, u32 v0, u32 v1, u32 fx) 848 { 849 u32 vx; 850 851 if (v0 == v1 || f0 == f1) 852 return v0; 853 854 /* *100 to have decimal fraction factor */ 855 vx = (v0 * 100) - ((((v0 - v1) * 100) / (f0 - f1)) * (f0 - fx)); 856 857 return DIV_ROUND_UP(vx, 100); 858 } 859 860 static void svs_get_bank_volts_v3(struct svs_platform *svsp) 861 { 862 struct svs_bank *svsb = svsp->pbank; 863 u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt; 864 u32 b_sft, shift_byte = 0, opp_start = 0, opp_stop = 0; 865 u32 middle_index = (svsb->opp_count / 2); 866 867 if (svsb->phase == SVSB_PHASE_MON && 868 svsb->volt_flags & SVSB_MON_VOLT_IGNORE) 869 return; 870 871 vop74 = svs_readl_relaxed(svsp, VOP74); 872 vop30 = svs_readl_relaxed(svsp, VOP30); 873 874 /* Target is to set svsb->volt[] by algorithm */ 875 if (turn_pt < middle_index) { 876 if (svsb->type == SVSB_HIGH) { 877 /* volt[0] ~ volt[turn_pt - 1] */ 878 for (i = 0; i < turn_pt; i++) { 879 b_sft = BITS8 * (shift_byte % REG_BYTES); 880 vop = (shift_byte < REG_BYTES) ? &vop30 : 881 &vop74; 882 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); 883 shift_byte++; 884 } 885 } else if (svsb->type == SVSB_LOW) { 886 /* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */ 887 j = svsb->opp_count - 7; 888 svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); 889 shift_byte++; 890 for (i = j; i < svsb->opp_count; i++) { 891 b_sft = BITS8 * (shift_byte % REG_BYTES); 892 vop = (shift_byte < REG_BYTES) ? &vop30 : 893 &vop74; 894 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); 895 shift_byte++; 896 } 897 898 /* volt[turn_pt + 1] ~ volt[j - 1] by interpolate */ 899 for (i = turn_pt + 1; i < j; i++) 900 svsb->volt[i] = interpolate(svsb->freq_pct[turn_pt], 901 svsb->freq_pct[j], 902 svsb->volt[turn_pt], 903 svsb->volt[j], 904 svsb->freq_pct[i]); 905 } 906 } else { 907 if (svsb->type == SVSB_HIGH) { 908 /* volt[0] + volt[j] ~ volt[turn_pt - 1] */ 909 j = turn_pt - 7; 910 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); 911 shift_byte++; 912 for (i = j; i < turn_pt; i++) { 913 b_sft = BITS8 * (shift_byte % REG_BYTES); 914 vop = (shift_byte < REG_BYTES) ? &vop30 : 915 &vop74; 916 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); 917 shift_byte++; 918 } 919 920 /* volt[1] ~ volt[j - 1] by interpolate */ 921 for (i = 1; i < j; i++) 922 svsb->volt[i] = interpolate(svsb->freq_pct[0], 923 svsb->freq_pct[j], 924 svsb->volt[0], 925 svsb->volt[j], 926 svsb->freq_pct[i]); 927 } else if (svsb->type == SVSB_LOW) { 928 /* volt[turn_pt] ~ volt[opp_count - 1] */ 929 for (i = turn_pt; i < svsb->opp_count; i++) { 930 b_sft = BITS8 * (shift_byte % REG_BYTES); 931 vop = (shift_byte < REG_BYTES) ? &vop30 : 932 &vop74; 933 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); 934 shift_byte++; 935 } 936 } 937 } 938 939 if (svsb->type == SVSB_HIGH) { 940 opp_start = 0; 941 opp_stop = svsb->turn_pt; 942 } else if (svsb->type == SVSB_LOW) { 943 opp_start = svsb->turn_pt; 944 opp_stop = svsb->opp_count; 945 } 946 947 for (i = opp_start; i < opp_stop; i++) 948 if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT) 949 svsb->volt[i] -= svsb->dvt_fixed; 950 } 951 952 static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) 953 { 954 struct svs_bank *svsb = svsp->pbank; 955 u32 i, j, *freq_pct, freq_pct74 = 0, freq_pct30 = 0; 956 u32 b_sft, shift_byte = 0, turn_pt; 957 u32 middle_index = (svsb->opp_count / 2); 958 959 for (i = 0; i < svsb->opp_count; i++) { 960 if (svsb->opp_dfreq[i] <= svsb->turn_freq_base) { 961 svsb->turn_pt = i; 962 break; 963 } 964 } 965 966 turn_pt = svsb->turn_pt; 967 968 /* Target is to fill out freq_pct74 / freq_pct30 by algorithm */ 969 if (turn_pt < middle_index) { 970 if (svsb->type == SVSB_HIGH) { 971 /* 972 * If we don't handle this situation, 973 * SVSB_HIGH's FREQPCT74 / FREQPCT30 would keep "0" 974 * and this leads SVSB_LOW to work abnormally. 975 */ 976 if (turn_pt == 0) 977 freq_pct30 = svsb->freq_pct[0]; 978 979 /* freq_pct[0] ~ freq_pct[turn_pt - 1] */ 980 for (i = 0; i < turn_pt; i++) { 981 b_sft = BITS8 * (shift_byte % REG_BYTES); 982 freq_pct = (shift_byte < REG_BYTES) ? 983 &freq_pct30 : &freq_pct74; 984 *freq_pct |= (svsb->freq_pct[i] << b_sft); 985 shift_byte++; 986 } 987 } else if (svsb->type == SVSB_LOW) { 988 /* 989 * freq_pct[turn_pt] + 990 * freq_pct[opp_count - 7] ~ freq_pct[opp_count -1] 991 */ 992 freq_pct30 = svsb->freq_pct[turn_pt]; 993 shift_byte++; 994 j = svsb->opp_count - 7; 995 for (i = j; i < svsb->opp_count; i++) { 996 b_sft = BITS8 * (shift_byte % REG_BYTES); 997 freq_pct = (shift_byte < REG_BYTES) ? 998 &freq_pct30 : &freq_pct74; 999 *freq_pct |= (svsb->freq_pct[i] << b_sft); 1000 shift_byte++; 1001 } 1002 } 1003 } else { 1004 if (svsb->type == SVSB_HIGH) { 1005 /* 1006 * freq_pct[0] + 1007 * freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1] 1008 */ 1009 freq_pct30 = svsb->freq_pct[0]; 1010 shift_byte++; 1011 j = turn_pt - 7; 1012 for (i = j; i < turn_pt; i++) { 1013 b_sft = BITS8 * (shift_byte % REG_BYTES); 1014 freq_pct = (shift_byte < REG_BYTES) ? 1015 &freq_pct30 : &freq_pct74; 1016 *freq_pct |= (svsb->freq_pct[i] << b_sft); 1017 shift_byte++; 1018 } 1019 } else if (svsb->type == SVSB_LOW) { 1020 /* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */ 1021 for (i = turn_pt; i < svsb->opp_count; i++) { 1022 b_sft = BITS8 * (shift_byte % REG_BYTES); 1023 freq_pct = (shift_byte < REG_BYTES) ? 1024 &freq_pct30 : &freq_pct74; 1025 *freq_pct |= (svsb->freq_pct[i] << b_sft); 1026 shift_byte++; 1027 } 1028 } 1029 } 1030 1031 svs_writel_relaxed(svsp, freq_pct74, FREQPCT74); 1032 svs_writel_relaxed(svsp, freq_pct30, FREQPCT30); 1033 } 1034 1035 static void svs_get_bank_volts_v2(struct svs_platform *svsp) 1036 { 1037 struct svs_bank *svsb = svsp->pbank; 1038 u32 temp, i; 1039 1040 temp = svs_readl_relaxed(svsp, VOP74); 1041 svsb->volt[14] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp); 1042 svsb->volt[12] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp); 1043 svsb->volt[10] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp); 1044 svsb->volt[8] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp); 1045 1046 temp = svs_readl_relaxed(svsp, VOP30); 1047 svsb->volt[6] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp); 1048 svsb->volt[4] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp); 1049 svsb->volt[2] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp); 1050 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp); 1051 1052 for (i = 0; i <= 12; i += 2) 1053 svsb->volt[i + 1] = interpolate(svsb->freq_pct[i], 1054 svsb->freq_pct[i + 2], 1055 svsb->volt[i], 1056 svsb->volt[i + 2], 1057 svsb->freq_pct[i + 1]); 1058 1059 svsb->volt[15] = interpolate(svsb->freq_pct[12], 1060 svsb->freq_pct[14], 1061 svsb->volt[12], 1062 svsb->volt[14], 1063 svsb->freq_pct[15]); 1064 1065 for (i = 0; i < svsb->opp_count; i++) 1066 svsb->volt[i] += svsb->volt_od; 1067 } 1068 1069 static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp) 1070 { 1071 struct svs_bank *svsb = svsp->pbank; 1072 u32 freqpct74_val, freqpct30_val; 1073 1074 freqpct74_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[8]) | 1075 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[10]) | 1076 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[12]) | 1077 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[14]); 1078 1079 freqpct30_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[0]) | 1080 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[2]) | 1081 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[4]) | 1082 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[6]); 1083 1084 svs_writel_relaxed(svsp, freqpct74_val, FREQPCT74); 1085 svs_writel_relaxed(svsp, freqpct30_val, FREQPCT30); 1086 } 1087 1088 static void svs_set_bank_phase(struct svs_platform *svsp, 1089 enum svsb_phase target_phase) 1090 { 1091 struct svs_bank *svsb = svsp->pbank; 1092 u32 des_char, temp_char, det_char, limit_vals, init2vals, ts_calcs; 1093 1094 svs_switch_bank(svsp); 1095 1096 des_char = FIELD_PREP(SVSB_DESCHAR_FLD_BDES, svsb->bdes) | 1097 FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes); 1098 svs_writel_relaxed(svsp, des_char, DESCHAR); 1099 1100 temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, svsb->vco) | 1101 FIELD_PREP(SVSB_TEMPCHAR_FLD_MTDES, svsb->mtdes) | 1102 FIELD_PREP(SVSB_TEMPCHAR_FLD_DVT_FIXED, svsb->dvt_fixed); 1103 svs_writel_relaxed(svsp, temp_char, TEMPCHAR); 1104 1105 det_char = FIELD_PREP(SVSB_DETCHAR_FLD_DCBDET, svsb->dcbdet) | 1106 FIELD_PREP(SVSB_DETCHAR_FLD_DCMDET, svsb->dcmdet); 1107 svs_writel_relaxed(svsp, det_char, DETCHAR); 1108 1109 svs_writel_relaxed(svsp, svsb->dc_config, DCCONFIG); 1110 svs_writel_relaxed(svsp, svsb->age_config, AGECONFIG); 1111 svs_writel_relaxed(svsp, SVSB_RUNCONFIG_DEFAULT, RUNCONFIG); 1112 1113 svsb->set_freq_pct(svsp); 1114 1115 limit_vals = FIELD_PREP(SVSB_LIMITVALS_FLD_DTLO, SVSB_VAL_DTLO) | 1116 FIELD_PREP(SVSB_LIMITVALS_FLD_DTHI, SVSB_VAL_DTHI) | 1117 FIELD_PREP(SVSB_LIMITVALS_FLD_VMIN, svsb->vmin) | 1118 FIELD_PREP(SVSB_LIMITVALS_FLD_VMAX, svsb->vmax); 1119 svs_writel_relaxed(svsp, limit_vals, LIMITVALS); 1120 1121 svs_writel_relaxed(svsp, SVSB_DET_WINDOW, DETWINDOW); 1122 svs_writel_relaxed(svsp, SVSB_DET_MAX, CONFIG); 1123 svs_writel_relaxed(svsp, svsb->chk_shift, CHKSHIFT); 1124 svs_writel_relaxed(svsp, svsb->ctl0, CTL0); 1125 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); 1126 1127 switch (target_phase) { 1128 case SVSB_PHASE_INIT01: 1129 svs_writel_relaxed(svsp, svsb->vboot, VBOOT); 1130 svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN); 1131 svs_writel_relaxed(svsp, SVSB_PTPEN_INIT01, SVSEN); 1132 break; 1133 case SVSB_PHASE_INIT02: 1134 init2vals = FIELD_PREP(SVSB_INIT2VALS_FLD_AGEVOFFSETIN, svsb->age_voffset_in) | 1135 FIELD_PREP(SVSB_INIT2VALS_FLD_DCVOFFSETIN, svsb->dc_voffset_in); 1136 svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN); 1137 svs_writel_relaxed(svsp, init2vals, INIT2VALS); 1138 svs_writel_relaxed(svsp, SVSB_PTPEN_INIT02, SVSEN); 1139 break; 1140 case SVSB_PHASE_MON: 1141 ts_calcs = FIELD_PREP(SVSB_TSCALCS_FLD_BTS, svsb->bts) | 1142 FIELD_PREP(SVSB_TSCALCS_FLD_MTS, svsb->mts); 1143 svs_writel_relaxed(svsp, ts_calcs, TSCALCS); 1144 svs_writel_relaxed(svsp, SVSB_INTEN_MONVOPEN, INTEN); 1145 svs_writel_relaxed(svsp, SVSB_PTPEN_MON, SVSEN); 1146 break; 1147 default: 1148 dev_err(svsb->dev, "requested unknown target phase: %u\n", 1149 target_phase); 1150 break; 1151 } 1152 } 1153 1154 static inline void svs_save_bank_register_data(struct svs_platform *svsp, 1155 enum svsb_phase phase) 1156 { 1157 struct svs_bank *svsb = svsp->pbank; 1158 enum svs_reg_index rg_i; 1159 1160 for (rg_i = DESCHAR; rg_i < SVS_REG_MAX; rg_i++) 1161 svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i); 1162 } 1163 1164 static inline void svs_error_isr_handler(struct svs_platform *svsp) 1165 { 1166 struct svs_bank *svsb = svsp->pbank; 1167 1168 dev_err(svsb->dev, "%s: CORESEL = 0x%08x\n", 1169 __func__, svs_readl_relaxed(svsp, CORESEL)); 1170 dev_err(svsb->dev, "SVSEN = 0x%08x, INTSTS = 0x%08x\n", 1171 svs_readl_relaxed(svsp, SVSEN), 1172 svs_readl_relaxed(svsp, INTSTS)); 1173 dev_err(svsb->dev, "SMSTATE0 = 0x%08x, SMSTATE1 = 0x%08x\n", 1174 svs_readl_relaxed(svsp, SMSTATE0), 1175 svs_readl_relaxed(svsp, SMSTATE1)); 1176 dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP)); 1177 1178 svs_save_bank_register_data(svsp, SVSB_PHASE_ERROR); 1179 1180 svsb->phase = SVSB_PHASE_ERROR; 1181 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); 1182 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); 1183 } 1184 1185 static inline void svs_init01_isr_handler(struct svs_platform *svsp) 1186 { 1187 struct svs_bank *svsb = svsp->pbank; 1188 1189 dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n", 1190 __func__, svs_readl_relaxed(svsp, VDESIGN74), 1191 svs_readl_relaxed(svsp, VDESIGN30), 1192 svs_readl_relaxed(svsp, DCVALUES)); 1193 1194 svs_save_bank_register_data(svsp, SVSB_PHASE_INIT01); 1195 1196 svsb->phase = SVSB_PHASE_INIT01; 1197 svsb->dc_voffset_in = ~(svs_readl_relaxed(svsp, DCVALUES) & 1198 GENMASK(15, 0)) + 1; 1199 if (svsb->volt_flags & SVSB_INIT01_VOLT_IGNORE || 1200 (svsb->dc_voffset_in & SVSB_DC_SIGNED_BIT && 1201 svsb->volt_flags & SVSB_INIT01_VOLT_INC_ONLY)) 1202 svsb->dc_voffset_in = 0; 1203 1204 svsb->age_voffset_in = svs_readl_relaxed(svsp, AGEVALUES) & 1205 GENMASK(15, 0); 1206 1207 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); 1208 svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS); 1209 svsb->core_sel &= ~SVSB_DET_CLK_EN; 1210 } 1211 1212 static inline void svs_init02_isr_handler(struct svs_platform *svsp) 1213 { 1214 struct svs_bank *svsb = svsp->pbank; 1215 1216 dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n", 1217 __func__, svs_readl_relaxed(svsp, VOP74), 1218 svs_readl_relaxed(svsp, VOP30), 1219 svs_readl_relaxed(svsp, DCVALUES)); 1220 1221 svs_save_bank_register_data(svsp, SVSB_PHASE_INIT02); 1222 1223 svsb->phase = SVSB_PHASE_INIT02; 1224 svsb->get_volts(svsp); 1225 1226 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); 1227 svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS); 1228 } 1229 1230 static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp) 1231 { 1232 struct svs_bank *svsb = svsp->pbank; 1233 1234 svs_save_bank_register_data(svsp, SVSB_PHASE_MON); 1235 1236 svsb->phase = SVSB_PHASE_MON; 1237 svsb->get_volts(svsp); 1238 1239 svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0); 1240 svs_writel_relaxed(svsp, SVSB_INTSTS_FLD_MONVOP, INTSTS); 1241 } 1242 1243 static irqreturn_t svs_isr(int irq, void *data) 1244 { 1245 struct svs_platform *svsp = data; 1246 struct svs_bank *svsb = NULL; 1247 unsigned long flags; 1248 u32 idx, int_sts, svs_en; 1249 1250 for (idx = 0; idx < svsp->bank_max; idx++) { 1251 svsb = &svsp->banks[idx]; 1252 WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name); 1253 1254 spin_lock_irqsave(&svs_lock, flags); 1255 svsp->pbank = svsb; 1256 1257 /* Find out which svs bank fires interrupt */ 1258 if (svsb->int_st & svs_readl_relaxed(svsp, INTST)) { 1259 spin_unlock_irqrestore(&svs_lock, flags); 1260 continue; 1261 } 1262 1263 svs_switch_bank(svsp); 1264 int_sts = svs_readl_relaxed(svsp, INTSTS); 1265 svs_en = svs_readl_relaxed(svsp, SVSEN); 1266 1267 if (int_sts == SVSB_INTSTS_F0_COMPLETE && 1268 svs_en == SVSB_PTPEN_INIT01) 1269 svs_init01_isr_handler(svsp); 1270 else if (int_sts == SVSB_INTSTS_F0_COMPLETE && 1271 svs_en == SVSB_PTPEN_INIT02) 1272 svs_init02_isr_handler(svsp); 1273 else if (int_sts & SVSB_INTSTS_FLD_MONVOP) 1274 svs_mon_mode_isr_handler(svsp); 1275 else 1276 svs_error_isr_handler(svsp); 1277 1278 spin_unlock_irqrestore(&svs_lock, flags); 1279 break; 1280 } 1281 1282 svs_adjust_pm_opp_volts(svsb); 1283 1284 if (svsb->phase == SVSB_PHASE_INIT01 || 1285 svsb->phase == SVSB_PHASE_INIT02) 1286 complete(&svsb->init_completion); 1287 1288 return IRQ_HANDLED; 1289 } 1290 1291 static int svs_init01(struct svs_platform *svsp) 1292 { 1293 struct svs_bank *svsb; 1294 unsigned long flags, time_left; 1295 bool search_done; 1296 int ret = 0, r; 1297 u32 opp_freq, opp_vboot, buck_volt, idx, i; 1298 1299 /* Keep CPUs' core power on for svs_init01 initialization */ 1300 cpuidle_pause_and_lock(); 1301 1302 /* Svs bank init01 preparation - power enable */ 1303 for (idx = 0; idx < svsp->bank_max; idx++) { 1304 svsb = &svsp->banks[idx]; 1305 1306 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1307 continue; 1308 1309 ret = regulator_enable(svsb->buck); 1310 if (ret) { 1311 dev_err(svsb->dev, "%s enable fail: %d\n", 1312 svsb->buck_name, ret); 1313 goto svs_init01_resume_cpuidle; 1314 } 1315 1316 /* Some buck doesn't support mode change. Show fail msg only */ 1317 ret = regulator_set_mode(svsb->buck, REGULATOR_MODE_FAST); 1318 if (ret) 1319 dev_notice(svsb->dev, "set fast mode fail: %d\n", ret); 1320 1321 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) { 1322 if (!pm_runtime_enabled(svsb->opp_dev)) { 1323 pm_runtime_enable(svsb->opp_dev); 1324 svsb->pm_runtime_enabled_count++; 1325 } 1326 1327 ret = pm_runtime_get_sync(svsb->opp_dev); 1328 if (ret < 0) { 1329 dev_err(svsb->dev, "mtcmos on fail: %d\n", ret); 1330 goto svs_init01_resume_cpuidle; 1331 } 1332 } 1333 } 1334 1335 /* 1336 * Svs bank init01 preparation - vboot voltage adjustment 1337 * Sometimes two svs banks use the same buck. Therefore, 1338 * we have to set each svs bank to target voltage(vboot) first. 1339 */ 1340 for (idx = 0; idx < svsp->bank_max; idx++) { 1341 svsb = &svsp->banks[idx]; 1342 1343 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1344 continue; 1345 1346 /* 1347 * Find the fastest freq that can be run at vboot and 1348 * fix to that freq until svs_init01 is done. 1349 */ 1350 search_done = false; 1351 opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, 1352 svsb->volt_step, 1353 svsb->volt_base); 1354 1355 for (i = 0; i < svsb->opp_count; i++) { 1356 opp_freq = svsb->opp_dfreq[i]; 1357 if (!search_done && svsb->opp_dvolt[i] <= opp_vboot) { 1358 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev, 1359 opp_freq, 1360 opp_vboot, 1361 opp_vboot, 1362 opp_vboot); 1363 if (ret) { 1364 dev_err(svsb->dev, 1365 "set opp %uuV vboot fail: %d\n", 1366 opp_vboot, ret); 1367 goto svs_init01_finish; 1368 } 1369 1370 search_done = true; 1371 } else { 1372 ret = dev_pm_opp_disable(svsb->opp_dev, 1373 svsb->opp_dfreq[i]); 1374 if (ret) { 1375 dev_err(svsb->dev, 1376 "opp %uHz disable fail: %d\n", 1377 svsb->opp_dfreq[i], ret); 1378 goto svs_init01_finish; 1379 } 1380 } 1381 } 1382 } 1383 1384 /* Svs bank init01 begins */ 1385 for (idx = 0; idx < svsp->bank_max; idx++) { 1386 svsb = &svsp->banks[idx]; 1387 1388 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1389 continue; 1390 1391 opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, 1392 svsb->volt_step, 1393 svsb->volt_base); 1394 1395 buck_volt = regulator_get_voltage(svsb->buck); 1396 if (buck_volt != opp_vboot) { 1397 dev_err(svsb->dev, 1398 "buck voltage: %uuV, expected vboot: %uuV\n", 1399 buck_volt, opp_vboot); 1400 ret = -EPERM; 1401 goto svs_init01_finish; 1402 } 1403 1404 spin_lock_irqsave(&svs_lock, flags); 1405 svsp->pbank = svsb; 1406 svs_set_bank_phase(svsp, SVSB_PHASE_INIT01); 1407 spin_unlock_irqrestore(&svs_lock, flags); 1408 1409 time_left = wait_for_completion_timeout(&svsb->init_completion, 1410 msecs_to_jiffies(5000)); 1411 if (!time_left) { 1412 dev_err(svsb->dev, "init01 completion timeout\n"); 1413 ret = -EBUSY; 1414 goto svs_init01_finish; 1415 } 1416 } 1417 1418 svs_init01_finish: 1419 for (idx = 0; idx < svsp->bank_max; idx++) { 1420 svsb = &svsp->banks[idx]; 1421 1422 if (!(svsb->mode_support & SVSB_MODE_INIT01)) 1423 continue; 1424 1425 for (i = 0; i < svsb->opp_count; i++) { 1426 r = dev_pm_opp_enable(svsb->opp_dev, 1427 svsb->opp_dfreq[i]); 1428 if (r) 1429 dev_err(svsb->dev, "opp %uHz enable fail: %d\n", 1430 svsb->opp_dfreq[i], r); 1431 } 1432 1433 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) { 1434 r = pm_runtime_put_sync(svsb->opp_dev); 1435 if (r) 1436 dev_err(svsb->dev, "mtcmos off fail: %d\n", r); 1437 1438 if (svsb->pm_runtime_enabled_count > 0) { 1439 pm_runtime_disable(svsb->opp_dev); 1440 svsb->pm_runtime_enabled_count--; 1441 } 1442 } 1443 1444 r = regulator_set_mode(svsb->buck, REGULATOR_MODE_NORMAL); 1445 if (r) 1446 dev_notice(svsb->dev, "set normal mode fail: %d\n", r); 1447 1448 r = regulator_disable(svsb->buck); 1449 if (r) 1450 dev_err(svsb->dev, "%s disable fail: %d\n", 1451 svsb->buck_name, r); 1452 } 1453 1454 svs_init01_resume_cpuidle: 1455 cpuidle_resume_and_unlock(); 1456 1457 return ret; 1458 } 1459 1460 static int svs_init02(struct svs_platform *svsp) 1461 { 1462 struct svs_bank *svsb; 1463 unsigned long flags, time_left; 1464 u32 idx; 1465 1466 for (idx = 0; idx < svsp->bank_max; idx++) { 1467 svsb = &svsp->banks[idx]; 1468 1469 if (!(svsb->mode_support & SVSB_MODE_INIT02)) 1470 continue; 1471 1472 reinit_completion(&svsb->init_completion); 1473 spin_lock_irqsave(&svs_lock, flags); 1474 svsp->pbank = svsb; 1475 svs_set_bank_phase(svsp, SVSB_PHASE_INIT02); 1476 spin_unlock_irqrestore(&svs_lock, flags); 1477 1478 time_left = wait_for_completion_timeout(&svsb->init_completion, 1479 msecs_to_jiffies(5000)); 1480 if (!time_left) { 1481 dev_err(svsb->dev, "init02 completion timeout\n"); 1482 return -EBUSY; 1483 } 1484 } 1485 1486 /* 1487 * 2-line high/low bank update its corresponding opp voltages only. 1488 * Therefore, we sync voltages from opp for high/low bank voltages 1489 * consistency. 1490 */ 1491 for (idx = 0; idx < svsp->bank_max; idx++) { 1492 svsb = &svsp->banks[idx]; 1493 1494 if (!(svsb->mode_support & SVSB_MODE_INIT02)) 1495 continue; 1496 1497 if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) { 1498 if (svs_sync_bank_volts_from_opp(svsb)) { 1499 dev_err(svsb->dev, "sync volt fail\n"); 1500 return -EPERM; 1501 } 1502 } 1503 } 1504 1505 return 0; 1506 } 1507 1508 static void svs_mon_mode(struct svs_platform *svsp) 1509 { 1510 struct svs_bank *svsb; 1511 unsigned long flags; 1512 u32 idx; 1513 1514 for (idx = 0; idx < svsp->bank_max; idx++) { 1515 svsb = &svsp->banks[idx]; 1516 1517 if (!(svsb->mode_support & SVSB_MODE_MON)) 1518 continue; 1519 1520 spin_lock_irqsave(&svs_lock, flags); 1521 svsp->pbank = svsb; 1522 svs_set_bank_phase(svsp, SVSB_PHASE_MON); 1523 spin_unlock_irqrestore(&svs_lock, flags); 1524 } 1525 } 1526 1527 static int svs_start(struct svs_platform *svsp) 1528 { 1529 int ret; 1530 1531 ret = svs_init01(svsp); 1532 if (ret) 1533 return ret; 1534 1535 ret = svs_init02(svsp); 1536 if (ret) 1537 return ret; 1538 1539 svs_mon_mode(svsp); 1540 1541 return 0; 1542 } 1543 1544 static int svs_suspend(struct device *dev) 1545 { 1546 struct svs_platform *svsp = dev_get_drvdata(dev); 1547 struct svs_bank *svsb; 1548 unsigned long flags; 1549 int ret; 1550 u32 idx; 1551 1552 for (idx = 0; idx < svsp->bank_max; idx++) { 1553 svsb = &svsp->banks[idx]; 1554 1555 /* This might wait for svs_isr() process */ 1556 spin_lock_irqsave(&svs_lock, flags); 1557 svsp->pbank = svsb; 1558 svs_switch_bank(svsp); 1559 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); 1560 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); 1561 spin_unlock_irqrestore(&svs_lock, flags); 1562 1563 svsb->phase = SVSB_PHASE_ERROR; 1564 svs_adjust_pm_opp_volts(svsb); 1565 } 1566 1567 ret = reset_control_assert(svsp->rst); 1568 if (ret) { 1569 dev_err(svsp->dev, "cannot assert reset %d\n", ret); 1570 return ret; 1571 } 1572 1573 clk_disable_unprepare(svsp->main_clk); 1574 1575 return 0; 1576 } 1577 1578 static int svs_resume(struct device *dev) 1579 { 1580 struct svs_platform *svsp = dev_get_drvdata(dev); 1581 int ret; 1582 1583 ret = clk_prepare_enable(svsp->main_clk); 1584 if (ret) { 1585 dev_err(svsp->dev, "cannot enable main_clk, disable svs\n"); 1586 return ret; 1587 } 1588 1589 ret = reset_control_deassert(svsp->rst); 1590 if (ret) { 1591 dev_err(svsp->dev, "cannot deassert reset %d\n", ret); 1592 goto out_of_resume; 1593 } 1594 1595 ret = svs_init02(svsp); 1596 if (ret) 1597 goto out_of_resume; 1598 1599 svs_mon_mode(svsp); 1600 1601 return 0; 1602 1603 out_of_resume: 1604 clk_disable_unprepare(svsp->main_clk); 1605 return ret; 1606 } 1607 1608 static int svs_bank_resource_setup(struct svs_platform *svsp) 1609 { 1610 struct svs_bank *svsb; 1611 struct dev_pm_opp *opp; 1612 unsigned long freq; 1613 int count, ret; 1614 u32 idx, i; 1615 1616 dev_set_drvdata(svsp->dev, svsp); 1617 1618 for (idx = 0; idx < svsp->bank_max; idx++) { 1619 svsb = &svsp->banks[idx]; 1620 1621 switch (svsb->sw_id) { 1622 case SVSB_CPU_LITTLE: 1623 svsb->name = "SVSB_CPU_LITTLE"; 1624 break; 1625 case SVSB_CPU_BIG: 1626 svsb->name = "SVSB_CPU_BIG"; 1627 break; 1628 case SVSB_CCI: 1629 svsb->name = "SVSB_CCI"; 1630 break; 1631 case SVSB_GPU: 1632 if (svsb->type == SVSB_HIGH) 1633 svsb->name = "SVSB_GPU_HIGH"; 1634 else if (svsb->type == SVSB_LOW) 1635 svsb->name = "SVSB_GPU_LOW"; 1636 else 1637 svsb->name = "SVSB_GPU"; 1638 break; 1639 default: 1640 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 1641 return -EINVAL; 1642 } 1643 1644 svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev), 1645 GFP_KERNEL); 1646 if (!svsb->dev) 1647 return -ENOMEM; 1648 1649 ret = dev_set_name(svsb->dev, "%s", svsb->name); 1650 if (ret) 1651 return ret; 1652 1653 dev_set_drvdata(svsb->dev, svsp); 1654 1655 ret = devm_pm_opp_of_add_table(svsb->opp_dev); 1656 if (ret) { 1657 dev_err(svsb->dev, "add opp table fail: %d\n", ret); 1658 return ret; 1659 } 1660 1661 mutex_init(&svsb->lock); 1662 init_completion(&svsb->init_completion); 1663 1664 if (svsb->mode_support & SVSB_MODE_INIT01) { 1665 svsb->buck = devm_regulator_get_optional(svsb->opp_dev, 1666 svsb->buck_name); 1667 if (IS_ERR(svsb->buck)) { 1668 dev_err(svsb->dev, "cannot get \"%s-supply\"\n", 1669 svsb->buck_name); 1670 return PTR_ERR(svsb->buck); 1671 } 1672 } 1673 1674 if (svsb->mode_support & SVSB_MODE_MON) { 1675 svsb->tzd = thermal_zone_get_zone_by_name(svsb->tzone_name); 1676 if (IS_ERR(svsb->tzd)) { 1677 dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n", 1678 svsb->tzone_name); 1679 return PTR_ERR(svsb->tzd); 1680 } 1681 } 1682 1683 count = dev_pm_opp_get_opp_count(svsb->opp_dev); 1684 if (svsb->opp_count != count) { 1685 dev_err(svsb->dev, 1686 "opp_count not \"%u\" but get \"%d\"?\n", 1687 svsb->opp_count, count); 1688 return count; 1689 } 1690 1691 for (i = 0, freq = U32_MAX; i < svsb->opp_count; i++, freq--) { 1692 opp = dev_pm_opp_find_freq_floor(svsb->opp_dev, &freq); 1693 if (IS_ERR(opp)) { 1694 dev_err(svsb->dev, "cannot find freq = %ld\n", 1695 PTR_ERR(opp)); 1696 return PTR_ERR(opp); 1697 } 1698 1699 svsb->opp_dfreq[i] = freq; 1700 svsb->opp_dvolt[i] = dev_pm_opp_get_voltage(opp); 1701 svsb->freq_pct[i] = percent(svsb->opp_dfreq[i], 1702 svsb->freq_base); 1703 dev_pm_opp_put(opp); 1704 } 1705 } 1706 1707 return 0; 1708 } 1709 1710 static int svs_thermal_efuse_get_data(struct svs_platform *svsp) 1711 { 1712 struct nvmem_cell *cell; 1713 1714 /* Thermal efuse parsing */ 1715 cell = nvmem_cell_get(svsp->dev, "t-calibration-data"); 1716 if (IS_ERR_OR_NULL(cell)) { 1717 dev_err(svsp->dev, "no \"t-calibration-data\"? %ld\n", PTR_ERR(cell)); 1718 return PTR_ERR(cell); 1719 } 1720 1721 svsp->tefuse = nvmem_cell_read(cell, &svsp->tefuse_max); 1722 if (IS_ERR(svsp->tefuse)) { 1723 dev_err(svsp->dev, "cannot read thermal efuse: %ld\n", 1724 PTR_ERR(svsp->tefuse)); 1725 nvmem_cell_put(cell); 1726 return PTR_ERR(svsp->tefuse); 1727 } 1728 1729 svsp->tefuse_max /= sizeof(u32); 1730 nvmem_cell_put(cell); 1731 1732 return 0; 1733 } 1734 1735 static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) 1736 { 1737 struct svs_bank *svsb; 1738 u32 idx, i, vmin, golden_temp; 1739 int ret; 1740 1741 for (i = 0; i < svsp->efuse_max; i++) 1742 if (svsp->efuse[i]) 1743 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", 1744 i, svsp->efuse[i]); 1745 1746 if (!svsp->efuse[9]) { 1747 dev_notice(svsp->dev, "svs_efuse[9] = 0x0?\n"); 1748 return false; 1749 } 1750 1751 /* Svs efuse parsing */ 1752 vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0); 1753 1754 for (idx = 0; idx < svsp->bank_max; idx++) { 1755 svsb = &svsp->banks[idx]; 1756 1757 if (vmin == 0x1) 1758 svsb->vmin = 0x1e; 1759 1760 if (svsb->type == SVSB_LOW) { 1761 svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); 1762 svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); 1763 svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); 1764 svsb->dcbdet = (svsp->efuse[17]) & GENMASK(7, 0); 1765 svsb->dcmdet = (svsp->efuse[17] >> 8) & GENMASK(7, 0); 1766 } else if (svsb->type == SVSB_HIGH) { 1767 svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); 1768 svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); 1769 svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); 1770 svsb->dcbdet = (svsp->efuse[17] >> 16) & GENMASK(7, 0); 1771 svsb->dcmdet = (svsp->efuse[17] >> 24) & GENMASK(7, 0); 1772 } 1773 1774 svsb->vmax += svsb->dvt_fixed; 1775 } 1776 1777 ret = svs_thermal_efuse_get_data(svsp); 1778 if (ret) 1779 return false; 1780 1781 for (i = 0; i < svsp->tefuse_max; i++) 1782 if (svsp->tefuse[i] != 0) 1783 break; 1784 1785 if (i == svsp->tefuse_max) 1786 golden_temp = 50; /* All thermal efuse data are 0 */ 1787 else 1788 golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); 1789 1790 for (idx = 0; idx < svsp->bank_max; idx++) { 1791 svsb = &svsp->banks[idx]; 1792 svsb->mts = 500; 1793 svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; 1794 } 1795 1796 return true; 1797 } 1798 1799 static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) 1800 { 1801 struct svs_bank *svsb; 1802 int format[6], x_roomt[6], o_vtsmcu[5], o_vtsabb, tb_roomt = 0; 1803 int adc_ge_t, adc_oe_t, ge, oe, gain, degc_cali, adc_cali_en_t; 1804 int o_slope, o_slope_sign, ts_id; 1805 u32 idx, i, ft_pgm, mts, temp0, temp1, temp2; 1806 int ret; 1807 1808 for (i = 0; i < svsp->efuse_max; i++) 1809 if (svsp->efuse[i]) 1810 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", 1811 i, svsp->efuse[i]); 1812 1813 if (!svsp->efuse[2]) { 1814 dev_notice(svsp->dev, "svs_efuse[2] = 0x0?\n"); 1815 return false; 1816 } 1817 1818 /* Svs efuse parsing */ 1819 ft_pgm = (svsp->efuse[0] >> 4) & GENMASK(3, 0); 1820 1821 for (idx = 0; idx < svsp->bank_max; idx++) { 1822 svsb = &svsp->banks[idx]; 1823 1824 if (ft_pgm <= 1) 1825 svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; 1826 1827 switch (svsb->sw_id) { 1828 case SVSB_CPU_LITTLE: 1829 svsb->bdes = svsp->efuse[16] & GENMASK(7, 0); 1830 svsb->mdes = (svsp->efuse[16] >> 8) & GENMASK(7, 0); 1831 svsb->dcbdet = (svsp->efuse[16] >> 16) & GENMASK(7, 0); 1832 svsb->dcmdet = (svsp->efuse[16] >> 24) & GENMASK(7, 0); 1833 svsb->mtdes = (svsp->efuse[17] >> 16) & GENMASK(7, 0); 1834 1835 if (ft_pgm <= 3) 1836 svsb->volt_od += 10; 1837 else 1838 svsb->volt_od += 2; 1839 break; 1840 case SVSB_CPU_BIG: 1841 svsb->bdes = svsp->efuse[18] & GENMASK(7, 0); 1842 svsb->mdes = (svsp->efuse[18] >> 8) & GENMASK(7, 0); 1843 svsb->dcbdet = (svsp->efuse[18] >> 16) & GENMASK(7, 0); 1844 svsb->dcmdet = (svsp->efuse[18] >> 24) & GENMASK(7, 0); 1845 svsb->mtdes = svsp->efuse[17] & GENMASK(7, 0); 1846 1847 if (ft_pgm <= 3) 1848 svsb->volt_od += 15; 1849 else 1850 svsb->volt_od += 12; 1851 break; 1852 case SVSB_CCI: 1853 svsb->bdes = svsp->efuse[4] & GENMASK(7, 0); 1854 svsb->mdes = (svsp->efuse[4] >> 8) & GENMASK(7, 0); 1855 svsb->dcbdet = (svsp->efuse[4] >> 16) & GENMASK(7, 0); 1856 svsb->dcmdet = (svsp->efuse[4] >> 24) & GENMASK(7, 0); 1857 svsb->mtdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); 1858 1859 if (ft_pgm <= 3) 1860 svsb->volt_od += 10; 1861 else 1862 svsb->volt_od += 2; 1863 break; 1864 case SVSB_GPU: 1865 svsb->bdes = svsp->efuse[6] & GENMASK(7, 0); 1866 svsb->mdes = (svsp->efuse[6] >> 8) & GENMASK(7, 0); 1867 svsb->dcbdet = (svsp->efuse[6] >> 16) & GENMASK(7, 0); 1868 svsb->dcmdet = (svsp->efuse[6] >> 24) & GENMASK(7, 0); 1869 svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); 1870 1871 if (ft_pgm >= 2) { 1872 svsb->freq_base = 800000000; /* 800MHz */ 1873 svsb->dvt_fixed = 2; 1874 } 1875 break; 1876 default: 1877 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 1878 return false; 1879 } 1880 } 1881 1882 ret = svs_thermal_efuse_get_data(svsp); 1883 if (ret) 1884 return false; 1885 1886 /* Thermal efuse parsing */ 1887 adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0); 1888 adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0); 1889 1890 o_vtsmcu[0] = (svsp->tefuse[0] >> 17) & GENMASK(8, 0); 1891 o_vtsmcu[1] = (svsp->tefuse[0] >> 8) & GENMASK(8, 0); 1892 o_vtsmcu[2] = svsp->tefuse[1] & GENMASK(8, 0); 1893 o_vtsmcu[3] = (svsp->tefuse[2] >> 23) & GENMASK(8, 0); 1894 o_vtsmcu[4] = (svsp->tefuse[2] >> 5) & GENMASK(8, 0); 1895 o_vtsabb = (svsp->tefuse[2] >> 14) & GENMASK(8, 0); 1896 1897 degc_cali = (svsp->tefuse[0] >> 1) & GENMASK(5, 0); 1898 adc_cali_en_t = svsp->tefuse[0] & BIT(0); 1899 o_slope_sign = (svsp->tefuse[0] >> 7) & BIT(0); 1900 1901 ts_id = (svsp->tefuse[1] >> 9) & BIT(0); 1902 o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0); 1903 1904 if (adc_cali_en_t == 1) { 1905 if (!ts_id) 1906 o_slope = 0; 1907 1908 if (adc_ge_t < 265 || adc_ge_t > 758 || 1909 adc_oe_t < 265 || adc_oe_t > 758 || 1910 o_vtsmcu[0] < -8 || o_vtsmcu[0] > 484 || 1911 o_vtsmcu[1] < -8 || o_vtsmcu[1] > 484 || 1912 o_vtsmcu[2] < -8 || o_vtsmcu[2] > 484 || 1913 o_vtsmcu[3] < -8 || o_vtsmcu[3] > 484 || 1914 o_vtsmcu[4] < -8 || o_vtsmcu[4] > 484 || 1915 o_vtsabb < -8 || o_vtsabb > 484 || 1916 degc_cali < 1 || degc_cali > 63) { 1917 dev_err(svsp->dev, "bad thermal efuse, no mon mode\n"); 1918 goto remove_mt8183_svsb_mon_mode; 1919 } 1920 } else { 1921 dev_err(svsp->dev, "no thermal efuse, no mon mode\n"); 1922 goto remove_mt8183_svsb_mon_mode; 1923 } 1924 1925 ge = ((adc_ge_t - 512) * 10000) / 4096; 1926 oe = (adc_oe_t - 512); 1927 gain = (10000 + ge); 1928 1929 format[0] = (o_vtsmcu[0] + 3350 - oe); 1930 format[1] = (o_vtsmcu[1] + 3350 - oe); 1931 format[2] = (o_vtsmcu[2] + 3350 - oe); 1932 format[3] = (o_vtsmcu[3] + 3350 - oe); 1933 format[4] = (o_vtsmcu[4] + 3350 - oe); 1934 format[5] = (o_vtsabb + 3350 - oe); 1935 1936 for (i = 0; i < 6; i++) 1937 x_roomt[i] = (((format[i] * 10000) / 4096) * 10000) / gain; 1938 1939 temp0 = (10000 * 100000 / gain) * 15 / 18; 1940 1941 if (!o_slope_sign) 1942 mts = (temp0 * 10) / (1534 + o_slope * 10); 1943 else 1944 mts = (temp0 * 10) / (1534 - o_slope * 10); 1945 1946 for (idx = 0; idx < svsp->bank_max; idx++) { 1947 svsb = &svsp->banks[idx]; 1948 svsb->mts = mts; 1949 1950 switch (svsb->sw_id) { 1951 case SVSB_CPU_LITTLE: 1952 tb_roomt = x_roomt[3]; 1953 break; 1954 case SVSB_CPU_BIG: 1955 tb_roomt = x_roomt[4]; 1956 break; 1957 case SVSB_CCI: 1958 tb_roomt = x_roomt[3]; 1959 break; 1960 case SVSB_GPU: 1961 tb_roomt = x_roomt[1]; 1962 break; 1963 default: 1964 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 1965 goto remove_mt8183_svsb_mon_mode; 1966 } 1967 1968 temp0 = (degc_cali * 10 / 2); 1969 temp1 = ((10000 * 100000 / 4096 / gain) * 1970 oe + tb_roomt * 10) * 15 / 18; 1971 1972 if (!o_slope_sign) 1973 temp2 = temp1 * 100 / (1534 + o_slope * 10); 1974 else 1975 temp2 = temp1 * 100 / (1534 - o_slope * 10); 1976 1977 svsb->bts = (temp0 + temp2 - 250) * 4 / 10; 1978 } 1979 1980 return true; 1981 1982 remove_mt8183_svsb_mon_mode: 1983 for (idx = 0; idx < svsp->bank_max; idx++) { 1984 svsb = &svsp->banks[idx]; 1985 svsb->mode_support &= ~SVSB_MODE_MON; 1986 } 1987 1988 return true; 1989 } 1990 1991 static bool svs_is_efuse_data_correct(struct svs_platform *svsp) 1992 { 1993 struct nvmem_cell *cell; 1994 1995 /* Get svs efuse by nvmem */ 1996 cell = nvmem_cell_get(svsp->dev, "svs-calibration-data"); 1997 if (IS_ERR(cell)) { 1998 dev_err(svsp->dev, "no \"svs-calibration-data\"? %ld\n", 1999 PTR_ERR(cell)); 2000 return false; 2001 } 2002 2003 svsp->efuse = nvmem_cell_read(cell, &svsp->efuse_max); 2004 if (IS_ERR(svsp->efuse)) { 2005 dev_err(svsp->dev, "cannot read svs efuse: %ld\n", 2006 PTR_ERR(svsp->efuse)); 2007 nvmem_cell_put(cell); 2008 return false; 2009 } 2010 2011 svsp->efuse_max /= sizeof(u32); 2012 nvmem_cell_put(cell); 2013 2014 return svsp->efuse_parsing(svsp); 2015 } 2016 2017 static struct device *svs_get_subsys_device(struct svs_platform *svsp, 2018 const char *node_name) 2019 { 2020 struct platform_device *pdev; 2021 struct device_node *np; 2022 2023 np = of_find_node_by_name(NULL, node_name); 2024 if (!np) { 2025 dev_err(svsp->dev, "cannot find %s node\n", node_name); 2026 return ERR_PTR(-ENODEV); 2027 } 2028 2029 pdev = of_find_device_by_node(np); 2030 if (!pdev) { 2031 of_node_put(np); 2032 dev_err(svsp->dev, "cannot find pdev by %s\n", node_name); 2033 return ERR_PTR(-ENXIO); 2034 } 2035 2036 of_node_put(np); 2037 2038 return &pdev->dev; 2039 } 2040 2041 static struct device *svs_add_device_link(struct svs_platform *svsp, 2042 const char *node_name) 2043 { 2044 struct device *dev; 2045 struct device_link *sup_link; 2046 2047 if (!node_name) { 2048 dev_err(svsp->dev, "node name cannot be null\n"); 2049 return ERR_PTR(-EINVAL); 2050 } 2051 2052 dev = svs_get_subsys_device(svsp, node_name); 2053 if (IS_ERR(dev)) 2054 return dev; 2055 2056 sup_link = device_link_add(svsp->dev, dev, 2057 DL_FLAG_AUTOREMOVE_CONSUMER); 2058 if (!sup_link) { 2059 dev_err(svsp->dev, "sup_link is NULL\n"); 2060 return ERR_PTR(-EINVAL); 2061 } 2062 2063 if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND) 2064 return ERR_PTR(-EPROBE_DEFER); 2065 2066 return dev; 2067 } 2068 2069 static int svs_mt8192_platform_probe(struct svs_platform *svsp) 2070 { 2071 struct device *dev; 2072 struct svs_bank *svsb; 2073 u32 idx; 2074 2075 svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst"); 2076 if (IS_ERR(svsp->rst)) 2077 return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), 2078 "cannot get svs reset control\n"); 2079 2080 dev = svs_add_device_link(svsp, "lvts"); 2081 if (IS_ERR(dev)) 2082 return dev_err_probe(svsp->dev, PTR_ERR(dev), 2083 "failed to get lvts device\n"); 2084 2085 for (idx = 0; idx < svsp->bank_max; idx++) { 2086 svsb = &svsp->banks[idx]; 2087 2088 if (svsb->type == SVSB_HIGH) 2089 svsb->opp_dev = svs_add_device_link(svsp, "mali"); 2090 else if (svsb->type == SVSB_LOW) 2091 svsb->opp_dev = svs_get_subsys_device(svsp, "mali"); 2092 2093 if (IS_ERR(svsb->opp_dev)) 2094 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), 2095 "failed to get OPP device for bank %d\n", 2096 idx); 2097 } 2098 2099 return 0; 2100 } 2101 2102 static int svs_mt8183_platform_probe(struct svs_platform *svsp) 2103 { 2104 struct device *dev; 2105 struct svs_bank *svsb; 2106 u32 idx; 2107 2108 dev = svs_add_device_link(svsp, "thermal"); 2109 if (IS_ERR(dev)) 2110 return dev_err_probe(svsp->dev, PTR_ERR(dev), 2111 "failed to get thermal device\n"); 2112 2113 for (idx = 0; idx < svsp->bank_max; idx++) { 2114 svsb = &svsp->banks[idx]; 2115 2116 switch (svsb->sw_id) { 2117 case SVSB_CPU_LITTLE: 2118 case SVSB_CPU_BIG: 2119 svsb->opp_dev = get_cpu_device(svsb->cpu_id); 2120 break; 2121 case SVSB_CCI: 2122 svsb->opp_dev = svs_add_device_link(svsp, "cci"); 2123 break; 2124 case SVSB_GPU: 2125 svsb->opp_dev = svs_add_device_link(svsp, "gpu"); 2126 break; 2127 default: 2128 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); 2129 return -EINVAL; 2130 } 2131 2132 if (IS_ERR(svsb->opp_dev)) 2133 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), 2134 "failed to get OPP device for bank %d\n", 2135 idx); 2136 } 2137 2138 return 0; 2139 } 2140 2141 static struct svs_bank svs_mt8192_banks[] = { 2142 { 2143 .sw_id = SVSB_GPU, 2144 .type = SVSB_LOW, 2145 .set_freq_pct = svs_set_bank_freq_pct_v3, 2146 .get_volts = svs_get_bank_volts_v3, 2147 .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, 2148 .mode_support = SVSB_MODE_INIT02, 2149 .opp_count = MAX_OPP_ENTRIES, 2150 .freq_base = 688000000, 2151 .turn_freq_base = 688000000, 2152 .volt_step = 6250, 2153 .volt_base = 400000, 2154 .vmax = 0x60, 2155 .vmin = 0x1a, 2156 .age_config = 0x555555, 2157 .dc_config = 0x1, 2158 .dvt_fixed = 0x1, 2159 .vco = 0x18, 2160 .chk_shift = 0x87, 2161 .core_sel = 0x0fff0100, 2162 .int_st = BIT(0), 2163 .ctl0 = 0x00540003, 2164 }, 2165 { 2166 .sw_id = SVSB_GPU, 2167 .type = SVSB_HIGH, 2168 .set_freq_pct = svs_set_bank_freq_pct_v3, 2169 .get_volts = svs_get_bank_volts_v3, 2170 .tzone_name = "gpu1", 2171 .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | 2172 SVSB_MON_VOLT_IGNORE, 2173 .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, 2174 .opp_count = MAX_OPP_ENTRIES, 2175 .freq_base = 902000000, 2176 .turn_freq_base = 688000000, 2177 .volt_step = 6250, 2178 .volt_base = 400000, 2179 .vmax = 0x60, 2180 .vmin = 0x1a, 2181 .age_config = 0x555555, 2182 .dc_config = 0x1, 2183 .dvt_fixed = 0x6, 2184 .vco = 0x18, 2185 .chk_shift = 0x87, 2186 .core_sel = 0x0fff0101, 2187 .int_st = BIT(1), 2188 .ctl0 = 0x00540003, 2189 .tzone_htemp = 85000, 2190 .tzone_htemp_voffset = 0, 2191 .tzone_ltemp = 25000, 2192 .tzone_ltemp_voffset = 7, 2193 }, 2194 }; 2195 2196 static struct svs_bank svs_mt8183_banks[] = { 2197 { 2198 .sw_id = SVSB_CPU_LITTLE, 2199 .set_freq_pct = svs_set_bank_freq_pct_v2, 2200 .get_volts = svs_get_bank_volts_v2, 2201 .cpu_id = 0, 2202 .buck_name = "proc", 2203 .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2204 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2205 .opp_count = MAX_OPP_ENTRIES, 2206 .freq_base = 1989000000, 2207 .vboot = 0x30, 2208 .volt_step = 6250, 2209 .volt_base = 500000, 2210 .vmax = 0x64, 2211 .vmin = 0x18, 2212 .age_config = 0x555555, 2213 .dc_config = 0x555555, 2214 .dvt_fixed = 0x7, 2215 .vco = 0x10, 2216 .chk_shift = 0x77, 2217 .core_sel = 0x8fff0000, 2218 .int_st = BIT(0), 2219 .ctl0 = 0x00010001, 2220 }, 2221 { 2222 .sw_id = SVSB_CPU_BIG, 2223 .set_freq_pct = svs_set_bank_freq_pct_v2, 2224 .get_volts = svs_get_bank_volts_v2, 2225 .cpu_id = 4, 2226 .buck_name = "proc", 2227 .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2228 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2229 .opp_count = MAX_OPP_ENTRIES, 2230 .freq_base = 1989000000, 2231 .vboot = 0x30, 2232 .volt_step = 6250, 2233 .volt_base = 500000, 2234 .vmax = 0x58, 2235 .vmin = 0x10, 2236 .age_config = 0x555555, 2237 .dc_config = 0x555555, 2238 .dvt_fixed = 0x7, 2239 .vco = 0x10, 2240 .chk_shift = 0x77, 2241 .core_sel = 0x8fff0001, 2242 .int_st = BIT(1), 2243 .ctl0 = 0x00000001, 2244 }, 2245 { 2246 .sw_id = SVSB_CCI, 2247 .set_freq_pct = svs_set_bank_freq_pct_v2, 2248 .get_volts = svs_get_bank_volts_v2, 2249 .buck_name = "proc", 2250 .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, 2251 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, 2252 .opp_count = MAX_OPP_ENTRIES, 2253 .freq_base = 1196000000, 2254 .vboot = 0x30, 2255 .volt_step = 6250, 2256 .volt_base = 500000, 2257 .vmax = 0x64, 2258 .vmin = 0x18, 2259 .age_config = 0x555555, 2260 .dc_config = 0x555555, 2261 .dvt_fixed = 0x7, 2262 .vco = 0x10, 2263 .chk_shift = 0x77, 2264 .core_sel = 0x8fff0002, 2265 .int_st = BIT(2), 2266 .ctl0 = 0x00100003, 2267 }, 2268 { 2269 .sw_id = SVSB_GPU, 2270 .set_freq_pct = svs_set_bank_freq_pct_v2, 2271 .get_volts = svs_get_bank_volts_v2, 2272 .buck_name = "mali", 2273 .tzone_name = "tzts2", 2274 .volt_flags = SVSB_INIT01_PD_REQ | 2275 SVSB_INIT01_VOLT_INC_ONLY, 2276 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02 | 2277 SVSB_MODE_MON, 2278 .opp_count = MAX_OPP_ENTRIES, 2279 .freq_base = 900000000, 2280 .vboot = 0x30, 2281 .volt_step = 6250, 2282 .volt_base = 500000, 2283 .vmax = 0x40, 2284 .vmin = 0x14, 2285 .age_config = 0x555555, 2286 .dc_config = 0x555555, 2287 .dvt_fixed = 0x3, 2288 .vco = 0x10, 2289 .chk_shift = 0x77, 2290 .core_sel = 0x8fff0003, 2291 .int_st = BIT(3), 2292 .ctl0 = 0x00050001, 2293 .tzone_htemp = 85000, 2294 .tzone_htemp_voffset = 0, 2295 .tzone_ltemp = 25000, 2296 .tzone_ltemp_voffset = 3, 2297 }, 2298 }; 2299 2300 static const struct svs_platform_data svs_mt8192_platform_data = { 2301 .name = "mt8192-svs", 2302 .banks = svs_mt8192_banks, 2303 .efuse_parsing = svs_mt8192_efuse_parsing, 2304 .probe = svs_mt8192_platform_probe, 2305 .regs = svs_regs_v2, 2306 .bank_max = ARRAY_SIZE(svs_mt8192_banks), 2307 }; 2308 2309 static const struct svs_platform_data svs_mt8183_platform_data = { 2310 .name = "mt8183-svs", 2311 .banks = svs_mt8183_banks, 2312 .efuse_parsing = svs_mt8183_efuse_parsing, 2313 .probe = svs_mt8183_platform_probe, 2314 .regs = svs_regs_v2, 2315 .bank_max = ARRAY_SIZE(svs_mt8183_banks), 2316 }; 2317 2318 static const struct of_device_id svs_of_match[] = { 2319 { 2320 .compatible = "mediatek,mt8192-svs", 2321 .data = &svs_mt8192_platform_data, 2322 }, { 2323 .compatible = "mediatek,mt8183-svs", 2324 .data = &svs_mt8183_platform_data, 2325 }, { 2326 /* Sentinel */ 2327 }, 2328 }; 2329 2330 static struct svs_platform *svs_platform_probe(struct platform_device *pdev) 2331 { 2332 struct svs_platform *svsp; 2333 const struct svs_platform_data *svsp_data; 2334 int ret; 2335 2336 svsp_data = of_device_get_match_data(&pdev->dev); 2337 if (!svsp_data) { 2338 dev_err(&pdev->dev, "no svs platform data?\n"); 2339 return ERR_PTR(-EPERM); 2340 } 2341 2342 svsp = devm_kzalloc(&pdev->dev, sizeof(*svsp), GFP_KERNEL); 2343 if (!svsp) 2344 return ERR_PTR(-ENOMEM); 2345 2346 svsp->dev = &pdev->dev; 2347 svsp->name = svsp_data->name; 2348 svsp->banks = svsp_data->banks; 2349 svsp->efuse_parsing = svsp_data->efuse_parsing; 2350 svsp->probe = svsp_data->probe; 2351 svsp->regs = svsp_data->regs; 2352 svsp->bank_max = svsp_data->bank_max; 2353 2354 ret = svsp->probe(svsp); 2355 if (ret) 2356 return ERR_PTR(ret); 2357 2358 return svsp; 2359 } 2360 2361 static int svs_probe(struct platform_device *pdev) 2362 { 2363 struct svs_platform *svsp; 2364 int svsp_irq, ret; 2365 2366 svsp = svs_platform_probe(pdev); 2367 if (IS_ERR(svsp)) 2368 return PTR_ERR(svsp); 2369 2370 if (!svs_is_efuse_data_correct(svsp)) { 2371 dev_notice(svsp->dev, "efuse data isn't correct\n"); 2372 ret = -EPERM; 2373 goto svs_probe_free_resource; 2374 } 2375 2376 ret = svs_bank_resource_setup(svsp); 2377 if (ret) { 2378 dev_err(svsp->dev, "svs bank resource setup fail: %d\n", ret); 2379 goto svs_probe_free_resource; 2380 } 2381 2382 svsp_irq = platform_get_irq(pdev, 0); 2383 if (svsp_irq < 0) { 2384 ret = svsp_irq; 2385 goto svs_probe_free_resource; 2386 } 2387 2388 ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr, 2389 IRQF_ONESHOT, svsp->name, svsp); 2390 if (ret) { 2391 dev_err(svsp->dev, "register irq(%d) failed: %d\n", 2392 svsp_irq, ret); 2393 goto svs_probe_free_resource; 2394 } 2395 2396 svsp->main_clk = devm_clk_get(svsp->dev, "main"); 2397 if (IS_ERR(svsp->main_clk)) { 2398 dev_err(svsp->dev, "failed to get clock: %ld\n", 2399 PTR_ERR(svsp->main_clk)); 2400 ret = PTR_ERR(svsp->main_clk); 2401 goto svs_probe_free_resource; 2402 } 2403 2404 ret = clk_prepare_enable(svsp->main_clk); 2405 if (ret) { 2406 dev_err(svsp->dev, "cannot enable main clk: %d\n", ret); 2407 goto svs_probe_free_resource; 2408 } 2409 2410 svsp->base = of_iomap(svsp->dev->of_node, 0); 2411 if (IS_ERR_OR_NULL(svsp->base)) { 2412 dev_err(svsp->dev, "cannot find svs register base\n"); 2413 ret = -EINVAL; 2414 goto svs_probe_clk_disable; 2415 } 2416 2417 ret = svs_start(svsp); 2418 if (ret) { 2419 dev_err(svsp->dev, "svs start fail: %d\n", ret); 2420 goto svs_probe_iounmap; 2421 } 2422 2423 ret = svs_create_debug_cmds(svsp); 2424 if (ret) { 2425 dev_err(svsp->dev, "svs create debug cmds fail: %d\n", ret); 2426 goto svs_probe_iounmap; 2427 } 2428 2429 return 0; 2430 2431 svs_probe_iounmap: 2432 iounmap(svsp->base); 2433 2434 svs_probe_clk_disable: 2435 clk_disable_unprepare(svsp->main_clk); 2436 2437 svs_probe_free_resource: 2438 if (!IS_ERR_OR_NULL(svsp->efuse)) 2439 kfree(svsp->efuse); 2440 if (!IS_ERR_OR_NULL(svsp->tefuse)) 2441 kfree(svsp->tefuse); 2442 2443 return ret; 2444 } 2445 2446 static DEFINE_SIMPLE_DEV_PM_OPS(svs_pm_ops, svs_suspend, svs_resume); 2447 2448 static struct platform_driver svs_driver = { 2449 .probe = svs_probe, 2450 .driver = { 2451 .name = "mtk-svs", 2452 .pm = &svs_pm_ops, 2453 .of_match_table = svs_of_match, 2454 }, 2455 }; 2456 2457 module_platform_driver(svs_driver); 2458 2459 MODULE_AUTHOR("Roger Lu <roger.lu@mediatek.com>"); 2460 MODULE_DESCRIPTION("MediaTek SVS driver"); 2461 MODULE_LICENSE("GPL"); 2462