1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Flora Fu, MediaTek 5 */ 6 #include <linux/clk.h> 7 #include <linux/interrupt.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/reset.h> 15 16 #define PWRAP_POLL_DELAY_US 10 17 #define PWRAP_POLL_TIMEOUT_US 10000 18 19 #define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4 20 #define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10 21 #define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14 22 #define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24 23 #define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28 24 #define PWRAP_MT8135_BRIDGE_INT_EN 0x38 25 #define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48 26 #define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50 27 #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54 28 29 /* macro for wrapper status */ 30 #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff) 31 #define PWRAP_GET_WACS_ARB_FSM(x) (((x) >> 1) & 0x00000007) 32 #define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007) 33 #define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001) 34 #define PWRAP_STATE_SYNC_IDLE0 BIT(20) 35 #define PWRAP_STATE_INIT_DONE0 BIT(21) 36 #define PWRAP_STATE_INIT_DONE0_MT8186 BIT(22) 37 #define PWRAP_STATE_INIT_DONE1 BIT(15) 38 39 /* macro for WACS FSM */ 40 #define PWRAP_WACS_FSM_IDLE 0x00 41 #define PWRAP_WACS_FSM_REQ 0x02 42 #define PWRAP_WACS_FSM_WFDLE 0x04 43 #define PWRAP_WACS_FSM_WFVLDCLR 0x06 44 #define PWRAP_WACS_INIT_DONE 0x01 45 #define PWRAP_WACS_WACS_SYNC_IDLE 0x01 46 #define PWRAP_WACS_SYNC_BUSY 0x00 47 48 /* macro for device wrapper default value */ 49 #define PWRAP_DEW_READ_TEST_VAL 0x5aa5 50 #define PWRAP_DEW_COMP_READ_TEST_VAL 0xa55a 51 #define PWRAP_DEW_WRITE_TEST_VAL 0xa55a 52 53 /* macro for manual command */ 54 #define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14) 55 #define PWRAP_MAN_CMD_SPI_WRITE (1 << 13) 56 #define PWRAP_MAN_CMD_OP_CSH (0x0 << 8) 57 #define PWRAP_MAN_CMD_OP_CSL (0x1 << 8) 58 #define PWRAP_MAN_CMD_OP_CK (0x2 << 8) 59 #define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8) 60 #define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8) 61 #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8) 62 63 /* macro for Watch Dog Timer Source */ 64 #define PWRAP_WDT_SRC_EN_STAUPD_TRIG (1 << 25) 65 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE (1 << 20) 66 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE (1 << 6) 67 #define PWRAP_WDT_SRC_MASK_ALL 0xffffffff 68 #define PWRAP_WDT_SRC_MASK_NO_STAUPD ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \ 69 PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \ 70 PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE) 71 72 /* Group of bits used for shown slave capability */ 73 #define PWRAP_SLV_CAP_SPI BIT(0) 74 #define PWRAP_SLV_CAP_DUALIO BIT(1) 75 #define PWRAP_SLV_CAP_SECURITY BIT(2) 76 #define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x)) 77 78 /* Group of bits used for shown pwrap capability */ 79 #define PWRAP_CAP_BRIDGE BIT(0) 80 #define PWRAP_CAP_RESET BIT(1) 81 #define PWRAP_CAP_DCM BIT(2) 82 #define PWRAP_CAP_INT1_EN BIT(3) 83 #define PWRAP_CAP_WDT_SRC1 BIT(4) 84 #define PWRAP_CAP_ARB BIT(5) 85 #define PWRAP_CAP_ARB_MT8186 BIT(8) 86 87 /* defines for slave device wrapper registers */ 88 enum dew_regs { 89 PWRAP_DEW_BASE, 90 PWRAP_DEW_DIO_EN, 91 PWRAP_DEW_READ_TEST, 92 PWRAP_DEW_WRITE_TEST, 93 PWRAP_DEW_CRC_EN, 94 PWRAP_DEW_CRC_VAL, 95 PWRAP_DEW_MON_GRP_SEL, 96 PWRAP_DEW_CIPHER_KEY_SEL, 97 PWRAP_DEW_CIPHER_IV_SEL, 98 PWRAP_DEW_CIPHER_RDY, 99 PWRAP_DEW_CIPHER_MODE, 100 PWRAP_DEW_CIPHER_SWRST, 101 102 /* MT6323 only regs */ 103 PWRAP_DEW_CIPHER_EN, 104 PWRAP_DEW_RDDMY_NO, 105 106 /* MT6358 only regs */ 107 PWRAP_SMT_CON1, 108 PWRAP_DRV_CON1, 109 PWRAP_FILTER_CON0, 110 PWRAP_GPIO_PULLEN0_CLR, 111 PWRAP_RG_SPI_CON0, 112 PWRAP_RG_SPI_RECORD0, 113 PWRAP_RG_SPI_CON2, 114 PWRAP_RG_SPI_CON3, 115 PWRAP_RG_SPI_CON4, 116 PWRAP_RG_SPI_CON5, 117 PWRAP_RG_SPI_CON6, 118 PWRAP_RG_SPI_CON7, 119 PWRAP_RG_SPI_CON8, 120 PWRAP_RG_SPI_CON13, 121 PWRAP_SPISLV_KEY, 122 123 /* MT6359 only regs */ 124 PWRAP_DEW_CRC_SWRST, 125 PWRAP_DEW_RG_EN_RECORD, 126 PWRAP_DEW_RECORD_CMD0, 127 PWRAP_DEW_RECORD_CMD1, 128 PWRAP_DEW_RECORD_CMD2, 129 PWRAP_DEW_RECORD_CMD3, 130 PWRAP_DEW_RECORD_CMD4, 131 PWRAP_DEW_RECORD_CMD5, 132 PWRAP_DEW_RECORD_WDATA0, 133 PWRAP_DEW_RECORD_WDATA1, 134 PWRAP_DEW_RECORD_WDATA2, 135 PWRAP_DEW_RECORD_WDATA3, 136 PWRAP_DEW_RECORD_WDATA4, 137 PWRAP_DEW_RECORD_WDATA5, 138 PWRAP_DEW_RG_ADDR_TARGET, 139 PWRAP_DEW_RG_ADDR_MASK, 140 PWRAP_DEW_RG_WDATA_TARGET, 141 PWRAP_DEW_RG_WDATA_MASK, 142 PWRAP_DEW_RG_SPI_RECORD_CLR, 143 PWRAP_DEW_RG_CMD_ALERT_CLR, 144 145 /* MT6397 only regs */ 146 PWRAP_DEW_EVENT_OUT_EN, 147 PWRAP_DEW_EVENT_SRC_EN, 148 PWRAP_DEW_EVENT_SRC, 149 PWRAP_DEW_EVENT_FLAG, 150 PWRAP_DEW_MON_FLAG_SEL, 151 PWRAP_DEW_EVENT_TEST, 152 PWRAP_DEW_CIPHER_LOAD, 153 PWRAP_DEW_CIPHER_START, 154 }; 155 156 static const u32 mt6323_regs[] = { 157 [PWRAP_DEW_BASE] = 0x0000, 158 [PWRAP_DEW_DIO_EN] = 0x018a, 159 [PWRAP_DEW_READ_TEST] = 0x018c, 160 [PWRAP_DEW_WRITE_TEST] = 0x018e, 161 [PWRAP_DEW_CRC_EN] = 0x0192, 162 [PWRAP_DEW_CRC_VAL] = 0x0194, 163 [PWRAP_DEW_MON_GRP_SEL] = 0x0196, 164 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0198, 165 [PWRAP_DEW_CIPHER_IV_SEL] = 0x019a, 166 [PWRAP_DEW_CIPHER_EN] = 0x019c, 167 [PWRAP_DEW_CIPHER_RDY] = 0x019e, 168 [PWRAP_DEW_CIPHER_MODE] = 0x01a0, 169 [PWRAP_DEW_CIPHER_SWRST] = 0x01a2, 170 [PWRAP_DEW_RDDMY_NO] = 0x01a4, 171 }; 172 173 static const u32 mt6331_regs[] = { 174 [PWRAP_DEW_DIO_EN] = 0x018c, 175 [PWRAP_DEW_READ_TEST] = 0x018e, 176 [PWRAP_DEW_WRITE_TEST] = 0x0190, 177 [PWRAP_DEW_CRC_SWRST] = 0x0192, 178 [PWRAP_DEW_CRC_EN] = 0x0194, 179 [PWRAP_DEW_CRC_VAL] = 0x0196, 180 [PWRAP_DEW_MON_GRP_SEL] = 0x0198, 181 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x019a, 182 [PWRAP_DEW_CIPHER_IV_SEL] = 0x019c, 183 [PWRAP_DEW_CIPHER_EN] = 0x019e, 184 [PWRAP_DEW_CIPHER_RDY] = 0x01a0, 185 [PWRAP_DEW_CIPHER_MODE] = 0x01a2, 186 [PWRAP_DEW_CIPHER_SWRST] = 0x01a4, 187 [PWRAP_DEW_RDDMY_NO] = 0x01a6, 188 }; 189 190 static const u32 mt6332_regs[] = { 191 [PWRAP_DEW_DIO_EN] = 0x80f6, 192 [PWRAP_DEW_READ_TEST] = 0x80f8, 193 [PWRAP_DEW_WRITE_TEST] = 0x80fa, 194 [PWRAP_DEW_CRC_SWRST] = 0x80fc, 195 [PWRAP_DEW_CRC_EN] = 0x80fe, 196 [PWRAP_DEW_CRC_VAL] = 0x8100, 197 [PWRAP_DEW_MON_GRP_SEL] = 0x8102, 198 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x8104, 199 [PWRAP_DEW_CIPHER_IV_SEL] = 0x8106, 200 [PWRAP_DEW_CIPHER_EN] = 0x8108, 201 [PWRAP_DEW_CIPHER_RDY] = 0x810a, 202 [PWRAP_DEW_CIPHER_MODE] = 0x810c, 203 [PWRAP_DEW_CIPHER_SWRST] = 0x810e, 204 [PWRAP_DEW_RDDMY_NO] = 0x8110, 205 }; 206 207 static const u32 mt6351_regs[] = { 208 [PWRAP_DEW_DIO_EN] = 0x02F2, 209 [PWRAP_DEW_READ_TEST] = 0x02F4, 210 [PWRAP_DEW_WRITE_TEST] = 0x02F6, 211 [PWRAP_DEW_CRC_EN] = 0x02FA, 212 [PWRAP_DEW_CRC_VAL] = 0x02FC, 213 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0300, 214 [PWRAP_DEW_CIPHER_IV_SEL] = 0x0302, 215 [PWRAP_DEW_CIPHER_EN] = 0x0304, 216 [PWRAP_DEW_CIPHER_RDY] = 0x0306, 217 [PWRAP_DEW_CIPHER_MODE] = 0x0308, 218 [PWRAP_DEW_CIPHER_SWRST] = 0x030A, 219 [PWRAP_DEW_RDDMY_NO] = 0x030C, 220 }; 221 222 static const u32 mt6357_regs[] = { 223 [PWRAP_DEW_DIO_EN] = 0x040A, 224 [PWRAP_DEW_READ_TEST] = 0x040C, 225 [PWRAP_DEW_WRITE_TEST] = 0x040E, 226 [PWRAP_DEW_CRC_EN] = 0x0412, 227 [PWRAP_DEW_CRC_VAL] = 0x0414, 228 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418, 229 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041A, 230 [PWRAP_DEW_CIPHER_EN] = 0x041C, 231 [PWRAP_DEW_CIPHER_RDY] = 0x041E, 232 [PWRAP_DEW_CIPHER_MODE] = 0x0420, 233 [PWRAP_DEW_CIPHER_SWRST] = 0x0422, 234 [PWRAP_DEW_RDDMY_NO] = 0x0424, 235 }; 236 237 static const u32 mt6358_regs[] = { 238 [PWRAP_SMT_CON1] = 0x0030, 239 [PWRAP_DRV_CON1] = 0x0038, 240 [PWRAP_FILTER_CON0] = 0x0040, 241 [PWRAP_GPIO_PULLEN0_CLR] = 0x0098, 242 [PWRAP_RG_SPI_CON0] = 0x0408, 243 [PWRAP_RG_SPI_RECORD0] = 0x040a, 244 [PWRAP_DEW_DIO_EN] = 0x040c, 245 [PWRAP_DEW_READ_TEST] = 0x040e, 246 [PWRAP_DEW_WRITE_TEST] = 0x0410, 247 [PWRAP_DEW_CRC_EN] = 0x0414, 248 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x041a, 249 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041c, 250 [PWRAP_DEW_CIPHER_EN] = 0x041e, 251 [PWRAP_DEW_CIPHER_RDY] = 0x0420, 252 [PWRAP_DEW_CIPHER_MODE] = 0x0422, 253 [PWRAP_DEW_CIPHER_SWRST] = 0x0424, 254 [PWRAP_RG_SPI_CON2] = 0x0432, 255 [PWRAP_RG_SPI_CON3] = 0x0434, 256 [PWRAP_RG_SPI_CON4] = 0x0436, 257 [PWRAP_RG_SPI_CON5] = 0x0438, 258 [PWRAP_RG_SPI_CON6] = 0x043a, 259 [PWRAP_RG_SPI_CON7] = 0x043c, 260 [PWRAP_RG_SPI_CON8] = 0x043e, 261 [PWRAP_RG_SPI_CON13] = 0x0448, 262 [PWRAP_SPISLV_KEY] = 0x044a, 263 }; 264 265 static const u32 mt6359_regs[] = { 266 [PWRAP_DEW_RG_EN_RECORD] = 0x040a, 267 [PWRAP_DEW_DIO_EN] = 0x040c, 268 [PWRAP_DEW_READ_TEST] = 0x040e, 269 [PWRAP_DEW_WRITE_TEST] = 0x0410, 270 [PWRAP_DEW_CRC_SWRST] = 0x0412, 271 [PWRAP_DEW_CRC_EN] = 0x0414, 272 [PWRAP_DEW_CRC_VAL] = 0x0416, 273 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418, 274 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041a, 275 [PWRAP_DEW_CIPHER_EN] = 0x041c, 276 [PWRAP_DEW_CIPHER_RDY] = 0x041e, 277 [PWRAP_DEW_CIPHER_MODE] = 0x0420, 278 [PWRAP_DEW_CIPHER_SWRST] = 0x0422, 279 [PWRAP_DEW_RDDMY_NO] = 0x0424, 280 [PWRAP_DEW_RECORD_CMD0] = 0x0428, 281 [PWRAP_DEW_RECORD_CMD1] = 0x042a, 282 [PWRAP_DEW_RECORD_CMD2] = 0x042c, 283 [PWRAP_DEW_RECORD_CMD3] = 0x042e, 284 [PWRAP_DEW_RECORD_CMD4] = 0x0430, 285 [PWRAP_DEW_RECORD_CMD5] = 0x0432, 286 [PWRAP_DEW_RECORD_WDATA0] = 0x0434, 287 [PWRAP_DEW_RECORD_WDATA1] = 0x0436, 288 [PWRAP_DEW_RECORD_WDATA2] = 0x0438, 289 [PWRAP_DEW_RECORD_WDATA3] = 0x043a, 290 [PWRAP_DEW_RECORD_WDATA4] = 0x043c, 291 [PWRAP_DEW_RECORD_WDATA5] = 0x043e, 292 [PWRAP_DEW_RG_ADDR_TARGET] = 0x0440, 293 [PWRAP_DEW_RG_ADDR_MASK] = 0x0442, 294 [PWRAP_DEW_RG_WDATA_TARGET] = 0x0444, 295 [PWRAP_DEW_RG_WDATA_MASK] = 0x0446, 296 [PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448, 297 [PWRAP_DEW_RG_CMD_ALERT_CLR] = 0x0448, 298 [PWRAP_SPISLV_KEY] = 0x044a, 299 }; 300 301 static const u32 mt6397_regs[] = { 302 [PWRAP_DEW_BASE] = 0xbc00, 303 [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00, 304 [PWRAP_DEW_DIO_EN] = 0xbc02, 305 [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04, 306 [PWRAP_DEW_EVENT_SRC] = 0xbc06, 307 [PWRAP_DEW_EVENT_FLAG] = 0xbc08, 308 [PWRAP_DEW_READ_TEST] = 0xbc0a, 309 [PWRAP_DEW_WRITE_TEST] = 0xbc0c, 310 [PWRAP_DEW_CRC_EN] = 0xbc0e, 311 [PWRAP_DEW_CRC_VAL] = 0xbc10, 312 [PWRAP_DEW_MON_GRP_SEL] = 0xbc12, 313 [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14, 314 [PWRAP_DEW_EVENT_TEST] = 0xbc16, 315 [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18, 316 [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a, 317 [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c, 318 [PWRAP_DEW_CIPHER_START] = 0xbc1e, 319 [PWRAP_DEW_CIPHER_RDY] = 0xbc20, 320 [PWRAP_DEW_CIPHER_MODE] = 0xbc22, 321 [PWRAP_DEW_CIPHER_SWRST] = 0xbc24, 322 }; 323 324 enum pwrap_regs { 325 PWRAP_MUX_SEL, 326 PWRAP_WRAP_EN, 327 PWRAP_DIO_EN, 328 PWRAP_SIDLY, 329 PWRAP_CSHEXT_WRITE, 330 PWRAP_CSHEXT_READ, 331 PWRAP_CSLEXT_START, 332 PWRAP_CSLEXT_END, 333 PWRAP_STAUPD_PRD, 334 PWRAP_STAUPD_GRPEN, 335 PWRAP_STAUPD_MAN_TRIG, 336 PWRAP_STAUPD_STA, 337 PWRAP_WRAP_STA, 338 PWRAP_HARB_INIT, 339 PWRAP_HARB_HPRIO, 340 PWRAP_HIPRIO_ARB_EN, 341 PWRAP_HARB_STA0, 342 PWRAP_HARB_STA1, 343 PWRAP_MAN_EN, 344 PWRAP_MAN_CMD, 345 PWRAP_MAN_RDATA, 346 PWRAP_MAN_VLDCLR, 347 PWRAP_WACS0_EN, 348 PWRAP_INIT_DONE0, 349 PWRAP_WACS0_CMD, 350 PWRAP_WACS0_RDATA, 351 PWRAP_WACS0_VLDCLR, 352 PWRAP_WACS1_EN, 353 PWRAP_INIT_DONE1, 354 PWRAP_WACS1_CMD, 355 PWRAP_WACS1_RDATA, 356 PWRAP_WACS1_VLDCLR, 357 PWRAP_WACS2_EN, 358 PWRAP_INIT_DONE2, 359 PWRAP_WACS2_CMD, 360 PWRAP_WACS2_RDATA, 361 PWRAP_WACS2_VLDCLR, 362 PWRAP_INT_EN, 363 PWRAP_INT_FLG_RAW, 364 PWRAP_INT_FLG, 365 PWRAP_INT_CLR, 366 PWRAP_SIG_ADR, 367 PWRAP_SIG_MODE, 368 PWRAP_SIG_VALUE, 369 PWRAP_SIG_ERRVAL, 370 PWRAP_CRC_EN, 371 PWRAP_TIMER_EN, 372 PWRAP_TIMER_STA, 373 PWRAP_WDT_UNIT, 374 PWRAP_WDT_SRC_EN, 375 PWRAP_WDT_FLG, 376 PWRAP_DEBUG_INT_SEL, 377 PWRAP_CIPHER_KEY_SEL, 378 PWRAP_CIPHER_IV_SEL, 379 PWRAP_CIPHER_RDY, 380 PWRAP_CIPHER_MODE, 381 PWRAP_CIPHER_SWRST, 382 PWRAP_DCM_EN, 383 PWRAP_DCM_DBC_PRD, 384 PWRAP_EINT_STA0_ADR, 385 PWRAP_EINT_STA1_ADR, 386 PWRAP_SWINF_2_WDATA_31_0, 387 PWRAP_SWINF_2_RDATA_31_0, 388 389 /* MT2701 only regs */ 390 PWRAP_ADC_CMD_ADDR, 391 PWRAP_PWRAP_ADC_CMD, 392 PWRAP_ADC_RDY_ADDR, 393 PWRAP_ADC_RDATA_ADDR1, 394 PWRAP_ADC_RDATA_ADDR2, 395 396 /* MT7622 only regs */ 397 PWRAP_STA, 398 PWRAP_CLR, 399 PWRAP_DVFS_ADR8, 400 PWRAP_DVFS_WDATA8, 401 PWRAP_DVFS_ADR9, 402 PWRAP_DVFS_WDATA9, 403 PWRAP_DVFS_ADR10, 404 PWRAP_DVFS_WDATA10, 405 PWRAP_DVFS_ADR11, 406 PWRAP_DVFS_WDATA11, 407 PWRAP_DVFS_ADR12, 408 PWRAP_DVFS_WDATA12, 409 PWRAP_DVFS_ADR13, 410 PWRAP_DVFS_WDATA13, 411 PWRAP_DVFS_ADR14, 412 PWRAP_DVFS_WDATA14, 413 PWRAP_DVFS_ADR15, 414 PWRAP_DVFS_WDATA15, 415 PWRAP_EXT_CK, 416 PWRAP_ADC_RDATA_ADDR, 417 PWRAP_GPS_STA, 418 PWRAP_SW_RST, 419 PWRAP_DVFS_STEP_CTRL0, 420 PWRAP_DVFS_STEP_CTRL1, 421 PWRAP_DVFS_STEP_CTRL2, 422 PWRAP_SPI2_CTRL, 423 424 /* MT8135 only regs */ 425 PWRAP_CSHEXT, 426 PWRAP_EVENT_IN_EN, 427 PWRAP_EVENT_DST_EN, 428 PWRAP_RRARB_INIT, 429 PWRAP_RRARB_EN, 430 PWRAP_RRARB_STA0, 431 PWRAP_RRARB_STA1, 432 PWRAP_EVENT_STA, 433 PWRAP_EVENT_STACLR, 434 PWRAP_CIPHER_LOAD, 435 PWRAP_CIPHER_START, 436 437 /* MT8173 only regs */ 438 PWRAP_RDDMY, 439 PWRAP_SI_CK_CON, 440 PWRAP_DVFS_ADR0, 441 PWRAP_DVFS_WDATA0, 442 PWRAP_DVFS_ADR1, 443 PWRAP_DVFS_WDATA1, 444 PWRAP_DVFS_ADR2, 445 PWRAP_DVFS_WDATA2, 446 PWRAP_DVFS_ADR3, 447 PWRAP_DVFS_WDATA3, 448 PWRAP_DVFS_ADR4, 449 PWRAP_DVFS_WDATA4, 450 PWRAP_DVFS_ADR5, 451 PWRAP_DVFS_WDATA5, 452 PWRAP_DVFS_ADR6, 453 PWRAP_DVFS_WDATA6, 454 PWRAP_DVFS_ADR7, 455 PWRAP_DVFS_WDATA7, 456 PWRAP_SPMINF_STA, 457 PWRAP_CIPHER_EN, 458 459 /* MT8183 only regs */ 460 PWRAP_SI_SAMPLE_CTRL, 461 PWRAP_CSLEXT_WRITE, 462 PWRAP_CSLEXT_READ, 463 PWRAP_EXT_CK_WRITE, 464 PWRAP_STAUPD_CTRL, 465 PWRAP_WACS_P2P_EN, 466 PWRAP_INIT_DONE_P2P, 467 PWRAP_WACS_MD32_EN, 468 PWRAP_INIT_DONE_MD32, 469 PWRAP_INT1_EN, 470 PWRAP_INT1_FLG, 471 PWRAP_INT1_CLR, 472 PWRAP_WDT_SRC_EN_1, 473 PWRAP_INT_GPS_AUXADC_CMD_ADDR, 474 PWRAP_INT_GPS_AUXADC_CMD, 475 PWRAP_INT_GPS_AUXADC_RDATA_ADDR, 476 PWRAP_EXT_GPS_AUXADC_RDATA_ADDR, 477 PWRAP_GPSINF_0_STA, 478 PWRAP_GPSINF_1_STA, 479 480 /* MT8516 only regs */ 481 PWRAP_OP_TYPE, 482 PWRAP_MSB_FIRST, 483 }; 484 485 static int mt2701_regs[] = { 486 [PWRAP_MUX_SEL] = 0x0, 487 [PWRAP_WRAP_EN] = 0x4, 488 [PWRAP_DIO_EN] = 0x8, 489 [PWRAP_SIDLY] = 0xc, 490 [PWRAP_RDDMY] = 0x18, 491 [PWRAP_SI_CK_CON] = 0x1c, 492 [PWRAP_CSHEXT_WRITE] = 0x20, 493 [PWRAP_CSHEXT_READ] = 0x24, 494 [PWRAP_CSLEXT_START] = 0x28, 495 [PWRAP_CSLEXT_END] = 0x2c, 496 [PWRAP_STAUPD_PRD] = 0x30, 497 [PWRAP_STAUPD_GRPEN] = 0x34, 498 [PWRAP_STAUPD_MAN_TRIG] = 0x38, 499 [PWRAP_STAUPD_STA] = 0x3c, 500 [PWRAP_WRAP_STA] = 0x44, 501 [PWRAP_HARB_INIT] = 0x48, 502 [PWRAP_HARB_HPRIO] = 0x4c, 503 [PWRAP_HIPRIO_ARB_EN] = 0x50, 504 [PWRAP_HARB_STA0] = 0x54, 505 [PWRAP_HARB_STA1] = 0x58, 506 [PWRAP_MAN_EN] = 0x5c, 507 [PWRAP_MAN_CMD] = 0x60, 508 [PWRAP_MAN_RDATA] = 0x64, 509 [PWRAP_MAN_VLDCLR] = 0x68, 510 [PWRAP_WACS0_EN] = 0x6c, 511 [PWRAP_INIT_DONE0] = 0x70, 512 [PWRAP_WACS0_CMD] = 0x74, 513 [PWRAP_WACS0_RDATA] = 0x78, 514 [PWRAP_WACS0_VLDCLR] = 0x7c, 515 [PWRAP_WACS1_EN] = 0x80, 516 [PWRAP_INIT_DONE1] = 0x84, 517 [PWRAP_WACS1_CMD] = 0x88, 518 [PWRAP_WACS1_RDATA] = 0x8c, 519 [PWRAP_WACS1_VLDCLR] = 0x90, 520 [PWRAP_WACS2_EN] = 0x94, 521 [PWRAP_INIT_DONE2] = 0x98, 522 [PWRAP_WACS2_CMD] = 0x9c, 523 [PWRAP_WACS2_RDATA] = 0xa0, 524 [PWRAP_WACS2_VLDCLR] = 0xa4, 525 [PWRAP_INT_EN] = 0xa8, 526 [PWRAP_INT_FLG_RAW] = 0xac, 527 [PWRAP_INT_FLG] = 0xb0, 528 [PWRAP_INT_CLR] = 0xb4, 529 [PWRAP_SIG_ADR] = 0xb8, 530 [PWRAP_SIG_MODE] = 0xbc, 531 [PWRAP_SIG_VALUE] = 0xc0, 532 [PWRAP_SIG_ERRVAL] = 0xc4, 533 [PWRAP_CRC_EN] = 0xc8, 534 [PWRAP_TIMER_EN] = 0xcc, 535 [PWRAP_TIMER_STA] = 0xd0, 536 [PWRAP_WDT_UNIT] = 0xd4, 537 [PWRAP_WDT_SRC_EN] = 0xd8, 538 [PWRAP_WDT_FLG] = 0xdc, 539 [PWRAP_DEBUG_INT_SEL] = 0xe0, 540 [PWRAP_DVFS_ADR0] = 0xe4, 541 [PWRAP_DVFS_WDATA0] = 0xe8, 542 [PWRAP_DVFS_ADR1] = 0xec, 543 [PWRAP_DVFS_WDATA1] = 0xf0, 544 [PWRAP_DVFS_ADR2] = 0xf4, 545 [PWRAP_DVFS_WDATA2] = 0xf8, 546 [PWRAP_DVFS_ADR3] = 0xfc, 547 [PWRAP_DVFS_WDATA3] = 0x100, 548 [PWRAP_DVFS_ADR4] = 0x104, 549 [PWRAP_DVFS_WDATA4] = 0x108, 550 [PWRAP_DVFS_ADR5] = 0x10c, 551 [PWRAP_DVFS_WDATA5] = 0x110, 552 [PWRAP_DVFS_ADR6] = 0x114, 553 [PWRAP_DVFS_WDATA6] = 0x118, 554 [PWRAP_DVFS_ADR7] = 0x11c, 555 [PWRAP_DVFS_WDATA7] = 0x120, 556 [PWRAP_CIPHER_KEY_SEL] = 0x124, 557 [PWRAP_CIPHER_IV_SEL] = 0x128, 558 [PWRAP_CIPHER_EN] = 0x12c, 559 [PWRAP_CIPHER_RDY] = 0x130, 560 [PWRAP_CIPHER_MODE] = 0x134, 561 [PWRAP_CIPHER_SWRST] = 0x138, 562 [PWRAP_DCM_EN] = 0x13c, 563 [PWRAP_DCM_DBC_PRD] = 0x140, 564 [PWRAP_ADC_CMD_ADDR] = 0x144, 565 [PWRAP_PWRAP_ADC_CMD] = 0x148, 566 [PWRAP_ADC_RDY_ADDR] = 0x14c, 567 [PWRAP_ADC_RDATA_ADDR1] = 0x150, 568 [PWRAP_ADC_RDATA_ADDR2] = 0x154, 569 }; 570 571 static int mt6765_regs[] = { 572 [PWRAP_MUX_SEL] = 0x0, 573 [PWRAP_WRAP_EN] = 0x4, 574 [PWRAP_DIO_EN] = 0x8, 575 [PWRAP_RDDMY] = 0x20, 576 [PWRAP_CSHEXT_WRITE] = 0x24, 577 [PWRAP_CSHEXT_READ] = 0x28, 578 [PWRAP_CSLEXT_START] = 0x2C, 579 [PWRAP_CSLEXT_END] = 0x30, 580 [PWRAP_STAUPD_PRD] = 0x3C, 581 [PWRAP_HARB_HPRIO] = 0x68, 582 [PWRAP_HIPRIO_ARB_EN] = 0x6C, 583 [PWRAP_MAN_EN] = 0x7C, 584 [PWRAP_MAN_CMD] = 0x80, 585 [PWRAP_WACS0_EN] = 0x8C, 586 [PWRAP_WACS1_EN] = 0x94, 587 [PWRAP_WACS2_EN] = 0x9C, 588 [PWRAP_INIT_DONE2] = 0xA0, 589 [PWRAP_WACS2_CMD] = 0xC20, 590 [PWRAP_WACS2_RDATA] = 0xC24, 591 [PWRAP_WACS2_VLDCLR] = 0xC28, 592 [PWRAP_INT_EN] = 0xB4, 593 [PWRAP_INT_FLG_RAW] = 0xB8, 594 [PWRAP_INT_FLG] = 0xBC, 595 [PWRAP_INT_CLR] = 0xC0, 596 [PWRAP_TIMER_EN] = 0xE8, 597 [PWRAP_WDT_UNIT] = 0xF0, 598 [PWRAP_WDT_SRC_EN] = 0xF4, 599 [PWRAP_DCM_EN] = 0x1DC, 600 [PWRAP_DCM_DBC_PRD] = 0x1E0, 601 }; 602 603 static int mt6779_regs[] = { 604 [PWRAP_MUX_SEL] = 0x0, 605 [PWRAP_WRAP_EN] = 0x4, 606 [PWRAP_DIO_EN] = 0x8, 607 [PWRAP_RDDMY] = 0x20, 608 [PWRAP_CSHEXT_WRITE] = 0x24, 609 [PWRAP_CSHEXT_READ] = 0x28, 610 [PWRAP_CSLEXT_WRITE] = 0x2C, 611 [PWRAP_CSLEXT_READ] = 0x30, 612 [PWRAP_EXT_CK_WRITE] = 0x34, 613 [PWRAP_STAUPD_CTRL] = 0x3C, 614 [PWRAP_STAUPD_GRPEN] = 0x40, 615 [PWRAP_EINT_STA0_ADR] = 0x44, 616 [PWRAP_HARB_HPRIO] = 0x68, 617 [PWRAP_HIPRIO_ARB_EN] = 0x6C, 618 [PWRAP_MAN_EN] = 0x7C, 619 [PWRAP_MAN_CMD] = 0x80, 620 [PWRAP_WACS0_EN] = 0x8C, 621 [PWRAP_INIT_DONE0] = 0x90, 622 [PWRAP_WACS1_EN] = 0x94, 623 [PWRAP_WACS2_EN] = 0x9C, 624 [PWRAP_INIT_DONE1] = 0x98, 625 [PWRAP_INIT_DONE2] = 0xA0, 626 [PWRAP_INT_EN] = 0xBC, 627 [PWRAP_INT_FLG_RAW] = 0xC0, 628 [PWRAP_INT_FLG] = 0xC4, 629 [PWRAP_INT_CLR] = 0xC8, 630 [PWRAP_INT1_EN] = 0xCC, 631 [PWRAP_INT1_FLG] = 0xD4, 632 [PWRAP_INT1_CLR] = 0xD8, 633 [PWRAP_TIMER_EN] = 0xF0, 634 [PWRAP_WDT_UNIT] = 0xF8, 635 [PWRAP_WDT_SRC_EN] = 0xFC, 636 [PWRAP_WDT_SRC_EN_1] = 0x100, 637 [PWRAP_WACS2_CMD] = 0xC20, 638 [PWRAP_WACS2_RDATA] = 0xC24, 639 [PWRAP_WACS2_VLDCLR] = 0xC28, 640 }; 641 642 static int mt6795_regs[] = { 643 [PWRAP_MUX_SEL] = 0x0, 644 [PWRAP_WRAP_EN] = 0x4, 645 [PWRAP_DIO_EN] = 0x8, 646 [PWRAP_SIDLY] = 0xc, 647 [PWRAP_RDDMY] = 0x10, 648 [PWRAP_SI_CK_CON] = 0x14, 649 [PWRAP_CSHEXT_WRITE] = 0x18, 650 [PWRAP_CSHEXT_READ] = 0x1c, 651 [PWRAP_CSLEXT_START] = 0x20, 652 [PWRAP_CSLEXT_END] = 0x24, 653 [PWRAP_STAUPD_PRD] = 0x28, 654 [PWRAP_STAUPD_GRPEN] = 0x2c, 655 [PWRAP_EINT_STA0_ADR] = 0x30, 656 [PWRAP_EINT_STA1_ADR] = 0x34, 657 [PWRAP_STAUPD_MAN_TRIG] = 0x40, 658 [PWRAP_STAUPD_STA] = 0x44, 659 [PWRAP_WRAP_STA] = 0x48, 660 [PWRAP_HARB_INIT] = 0x4c, 661 [PWRAP_HARB_HPRIO] = 0x50, 662 [PWRAP_HIPRIO_ARB_EN] = 0x54, 663 [PWRAP_HARB_STA0] = 0x58, 664 [PWRAP_HARB_STA1] = 0x5c, 665 [PWRAP_MAN_EN] = 0x60, 666 [PWRAP_MAN_CMD] = 0x64, 667 [PWRAP_MAN_RDATA] = 0x68, 668 [PWRAP_MAN_VLDCLR] = 0x6c, 669 [PWRAP_WACS0_EN] = 0x70, 670 [PWRAP_INIT_DONE0] = 0x74, 671 [PWRAP_WACS0_CMD] = 0x78, 672 [PWRAP_WACS0_RDATA] = 0x7c, 673 [PWRAP_WACS0_VLDCLR] = 0x80, 674 [PWRAP_WACS1_EN] = 0x84, 675 [PWRAP_INIT_DONE1] = 0x88, 676 [PWRAP_WACS1_CMD] = 0x8c, 677 [PWRAP_WACS1_RDATA] = 0x90, 678 [PWRAP_WACS1_VLDCLR] = 0x94, 679 [PWRAP_WACS2_EN] = 0x98, 680 [PWRAP_INIT_DONE2] = 0x9c, 681 [PWRAP_WACS2_CMD] = 0xa0, 682 [PWRAP_WACS2_RDATA] = 0xa4, 683 [PWRAP_WACS2_VLDCLR] = 0xa8, 684 [PWRAP_INT_EN] = 0xac, 685 [PWRAP_INT_FLG_RAW] = 0xb0, 686 [PWRAP_INT_FLG] = 0xb4, 687 [PWRAP_INT_CLR] = 0xb8, 688 [PWRAP_SIG_ADR] = 0xbc, 689 [PWRAP_SIG_MODE] = 0xc0, 690 [PWRAP_SIG_VALUE] = 0xc4, 691 [PWRAP_SIG_ERRVAL] = 0xc8, 692 [PWRAP_CRC_EN] = 0xcc, 693 [PWRAP_TIMER_EN] = 0xd0, 694 [PWRAP_TIMER_STA] = 0xd4, 695 [PWRAP_WDT_UNIT] = 0xd8, 696 [PWRAP_WDT_SRC_EN] = 0xdc, 697 [PWRAP_WDT_FLG] = 0xe0, 698 [PWRAP_DEBUG_INT_SEL] = 0xe4, 699 [PWRAP_DVFS_ADR0] = 0xe8, 700 [PWRAP_DVFS_WDATA0] = 0xec, 701 [PWRAP_DVFS_ADR1] = 0xf0, 702 [PWRAP_DVFS_WDATA1] = 0xf4, 703 [PWRAP_DVFS_ADR2] = 0xf8, 704 [PWRAP_DVFS_WDATA2] = 0xfc, 705 [PWRAP_DVFS_ADR3] = 0x100, 706 [PWRAP_DVFS_WDATA3] = 0x104, 707 [PWRAP_DVFS_ADR4] = 0x108, 708 [PWRAP_DVFS_WDATA4] = 0x10c, 709 [PWRAP_DVFS_ADR5] = 0x110, 710 [PWRAP_DVFS_WDATA5] = 0x114, 711 [PWRAP_DVFS_ADR6] = 0x118, 712 [PWRAP_DVFS_WDATA6] = 0x11c, 713 [PWRAP_DVFS_ADR7] = 0x120, 714 [PWRAP_DVFS_WDATA7] = 0x124, 715 [PWRAP_SPMINF_STA] = 0x128, 716 [PWRAP_CIPHER_KEY_SEL] = 0x12c, 717 [PWRAP_CIPHER_IV_SEL] = 0x130, 718 [PWRAP_CIPHER_EN] = 0x134, 719 [PWRAP_CIPHER_RDY] = 0x138, 720 [PWRAP_CIPHER_MODE] = 0x13c, 721 [PWRAP_CIPHER_SWRST] = 0x140, 722 [PWRAP_DCM_EN] = 0x144, 723 [PWRAP_DCM_DBC_PRD] = 0x148, 724 [PWRAP_EXT_CK] = 0x14c, 725 }; 726 727 static int mt6797_regs[] = { 728 [PWRAP_MUX_SEL] = 0x0, 729 [PWRAP_WRAP_EN] = 0x4, 730 [PWRAP_DIO_EN] = 0x8, 731 [PWRAP_SIDLY] = 0xC, 732 [PWRAP_RDDMY] = 0x10, 733 [PWRAP_CSHEXT_WRITE] = 0x18, 734 [PWRAP_CSHEXT_READ] = 0x1C, 735 [PWRAP_CSLEXT_START] = 0x20, 736 [PWRAP_CSLEXT_END] = 0x24, 737 [PWRAP_STAUPD_PRD] = 0x28, 738 [PWRAP_HARB_HPRIO] = 0x50, 739 [PWRAP_HIPRIO_ARB_EN] = 0x54, 740 [PWRAP_MAN_EN] = 0x60, 741 [PWRAP_MAN_CMD] = 0x64, 742 [PWRAP_WACS0_EN] = 0x70, 743 [PWRAP_WACS1_EN] = 0x84, 744 [PWRAP_WACS2_EN] = 0x98, 745 [PWRAP_INIT_DONE2] = 0x9C, 746 [PWRAP_WACS2_CMD] = 0xA0, 747 [PWRAP_WACS2_RDATA] = 0xA4, 748 [PWRAP_WACS2_VLDCLR] = 0xA8, 749 [PWRAP_INT_EN] = 0xC0, 750 [PWRAP_INT_FLG_RAW] = 0xC4, 751 [PWRAP_INT_FLG] = 0xC8, 752 [PWRAP_INT_CLR] = 0xCC, 753 [PWRAP_TIMER_EN] = 0xF4, 754 [PWRAP_WDT_UNIT] = 0xFC, 755 [PWRAP_WDT_SRC_EN] = 0x100, 756 [PWRAP_DCM_EN] = 0x1CC, 757 [PWRAP_DCM_DBC_PRD] = 0x1D4, 758 }; 759 760 static int mt6873_regs[] = { 761 [PWRAP_INIT_DONE2] = 0x0, 762 [PWRAP_TIMER_EN] = 0x3E0, 763 [PWRAP_INT_EN] = 0x448, 764 [PWRAP_WACS2_CMD] = 0xC80, 765 [PWRAP_SWINF_2_WDATA_31_0] = 0xC84, 766 [PWRAP_SWINF_2_RDATA_31_0] = 0xC94, 767 [PWRAP_WACS2_VLDCLR] = 0xCA4, 768 [PWRAP_WACS2_RDATA] = 0xCA8, 769 }; 770 771 static int mt7622_regs[] = { 772 [PWRAP_MUX_SEL] = 0x0, 773 [PWRAP_WRAP_EN] = 0x4, 774 [PWRAP_DIO_EN] = 0x8, 775 [PWRAP_SIDLY] = 0xC, 776 [PWRAP_RDDMY] = 0x10, 777 [PWRAP_SI_CK_CON] = 0x14, 778 [PWRAP_CSHEXT_WRITE] = 0x18, 779 [PWRAP_CSHEXT_READ] = 0x1C, 780 [PWRAP_CSLEXT_START] = 0x20, 781 [PWRAP_CSLEXT_END] = 0x24, 782 [PWRAP_STAUPD_PRD] = 0x28, 783 [PWRAP_STAUPD_GRPEN] = 0x2C, 784 [PWRAP_EINT_STA0_ADR] = 0x30, 785 [PWRAP_EINT_STA1_ADR] = 0x34, 786 [PWRAP_STA] = 0x38, 787 [PWRAP_CLR] = 0x3C, 788 [PWRAP_STAUPD_MAN_TRIG] = 0x40, 789 [PWRAP_STAUPD_STA] = 0x44, 790 [PWRAP_WRAP_STA] = 0x48, 791 [PWRAP_HARB_INIT] = 0x4C, 792 [PWRAP_HARB_HPRIO] = 0x50, 793 [PWRAP_HIPRIO_ARB_EN] = 0x54, 794 [PWRAP_HARB_STA0] = 0x58, 795 [PWRAP_HARB_STA1] = 0x5C, 796 [PWRAP_MAN_EN] = 0x60, 797 [PWRAP_MAN_CMD] = 0x64, 798 [PWRAP_MAN_RDATA] = 0x68, 799 [PWRAP_MAN_VLDCLR] = 0x6C, 800 [PWRAP_WACS0_EN] = 0x70, 801 [PWRAP_INIT_DONE0] = 0x74, 802 [PWRAP_WACS0_CMD] = 0x78, 803 [PWRAP_WACS0_RDATA] = 0x7C, 804 [PWRAP_WACS0_VLDCLR] = 0x80, 805 [PWRAP_WACS1_EN] = 0x84, 806 [PWRAP_INIT_DONE1] = 0x88, 807 [PWRAP_WACS1_CMD] = 0x8C, 808 [PWRAP_WACS1_RDATA] = 0x90, 809 [PWRAP_WACS1_VLDCLR] = 0x94, 810 [PWRAP_WACS2_EN] = 0x98, 811 [PWRAP_INIT_DONE2] = 0x9C, 812 [PWRAP_WACS2_CMD] = 0xA0, 813 [PWRAP_WACS2_RDATA] = 0xA4, 814 [PWRAP_WACS2_VLDCLR] = 0xA8, 815 [PWRAP_INT_EN] = 0xAC, 816 [PWRAP_INT_FLG_RAW] = 0xB0, 817 [PWRAP_INT_FLG] = 0xB4, 818 [PWRAP_INT_CLR] = 0xB8, 819 [PWRAP_SIG_ADR] = 0xBC, 820 [PWRAP_SIG_MODE] = 0xC0, 821 [PWRAP_SIG_VALUE] = 0xC4, 822 [PWRAP_SIG_ERRVAL] = 0xC8, 823 [PWRAP_CRC_EN] = 0xCC, 824 [PWRAP_TIMER_EN] = 0xD0, 825 [PWRAP_TIMER_STA] = 0xD4, 826 [PWRAP_WDT_UNIT] = 0xD8, 827 [PWRAP_WDT_SRC_EN] = 0xDC, 828 [PWRAP_WDT_FLG] = 0xE0, 829 [PWRAP_DEBUG_INT_SEL] = 0xE4, 830 [PWRAP_DVFS_ADR0] = 0xE8, 831 [PWRAP_DVFS_WDATA0] = 0xEC, 832 [PWRAP_DVFS_ADR1] = 0xF0, 833 [PWRAP_DVFS_WDATA1] = 0xF4, 834 [PWRAP_DVFS_ADR2] = 0xF8, 835 [PWRAP_DVFS_WDATA2] = 0xFC, 836 [PWRAP_DVFS_ADR3] = 0x100, 837 [PWRAP_DVFS_WDATA3] = 0x104, 838 [PWRAP_DVFS_ADR4] = 0x108, 839 [PWRAP_DVFS_WDATA4] = 0x10C, 840 [PWRAP_DVFS_ADR5] = 0x110, 841 [PWRAP_DVFS_WDATA5] = 0x114, 842 [PWRAP_DVFS_ADR6] = 0x118, 843 [PWRAP_DVFS_WDATA6] = 0x11C, 844 [PWRAP_DVFS_ADR7] = 0x120, 845 [PWRAP_DVFS_WDATA7] = 0x124, 846 [PWRAP_DVFS_ADR8] = 0x128, 847 [PWRAP_DVFS_WDATA8] = 0x12C, 848 [PWRAP_DVFS_ADR9] = 0x130, 849 [PWRAP_DVFS_WDATA9] = 0x134, 850 [PWRAP_DVFS_ADR10] = 0x138, 851 [PWRAP_DVFS_WDATA10] = 0x13C, 852 [PWRAP_DVFS_ADR11] = 0x140, 853 [PWRAP_DVFS_WDATA11] = 0x144, 854 [PWRAP_DVFS_ADR12] = 0x148, 855 [PWRAP_DVFS_WDATA12] = 0x14C, 856 [PWRAP_DVFS_ADR13] = 0x150, 857 [PWRAP_DVFS_WDATA13] = 0x154, 858 [PWRAP_DVFS_ADR14] = 0x158, 859 [PWRAP_DVFS_WDATA14] = 0x15C, 860 [PWRAP_DVFS_ADR15] = 0x160, 861 [PWRAP_DVFS_WDATA15] = 0x164, 862 [PWRAP_SPMINF_STA] = 0x168, 863 [PWRAP_CIPHER_KEY_SEL] = 0x16C, 864 [PWRAP_CIPHER_IV_SEL] = 0x170, 865 [PWRAP_CIPHER_EN] = 0x174, 866 [PWRAP_CIPHER_RDY] = 0x178, 867 [PWRAP_CIPHER_MODE] = 0x17C, 868 [PWRAP_CIPHER_SWRST] = 0x180, 869 [PWRAP_DCM_EN] = 0x184, 870 [PWRAP_DCM_DBC_PRD] = 0x188, 871 [PWRAP_EXT_CK] = 0x18C, 872 [PWRAP_ADC_CMD_ADDR] = 0x190, 873 [PWRAP_PWRAP_ADC_CMD] = 0x194, 874 [PWRAP_ADC_RDATA_ADDR] = 0x198, 875 [PWRAP_GPS_STA] = 0x19C, 876 [PWRAP_SW_RST] = 0x1A0, 877 [PWRAP_DVFS_STEP_CTRL0] = 0x238, 878 [PWRAP_DVFS_STEP_CTRL1] = 0x23C, 879 [PWRAP_DVFS_STEP_CTRL2] = 0x240, 880 [PWRAP_SPI2_CTRL] = 0x244, 881 }; 882 883 static int mt8135_regs[] = { 884 [PWRAP_MUX_SEL] = 0x0, 885 [PWRAP_WRAP_EN] = 0x4, 886 [PWRAP_DIO_EN] = 0x8, 887 [PWRAP_SIDLY] = 0xc, 888 [PWRAP_CSHEXT] = 0x10, 889 [PWRAP_CSHEXT_WRITE] = 0x14, 890 [PWRAP_CSHEXT_READ] = 0x18, 891 [PWRAP_CSLEXT_START] = 0x1c, 892 [PWRAP_CSLEXT_END] = 0x20, 893 [PWRAP_STAUPD_PRD] = 0x24, 894 [PWRAP_STAUPD_GRPEN] = 0x28, 895 [PWRAP_STAUPD_MAN_TRIG] = 0x2c, 896 [PWRAP_STAUPD_STA] = 0x30, 897 [PWRAP_EVENT_IN_EN] = 0x34, 898 [PWRAP_EVENT_DST_EN] = 0x38, 899 [PWRAP_WRAP_STA] = 0x3c, 900 [PWRAP_RRARB_INIT] = 0x40, 901 [PWRAP_RRARB_EN] = 0x44, 902 [PWRAP_RRARB_STA0] = 0x48, 903 [PWRAP_RRARB_STA1] = 0x4c, 904 [PWRAP_HARB_INIT] = 0x50, 905 [PWRAP_HARB_HPRIO] = 0x54, 906 [PWRAP_HIPRIO_ARB_EN] = 0x58, 907 [PWRAP_HARB_STA0] = 0x5c, 908 [PWRAP_HARB_STA1] = 0x60, 909 [PWRAP_MAN_EN] = 0x64, 910 [PWRAP_MAN_CMD] = 0x68, 911 [PWRAP_MAN_RDATA] = 0x6c, 912 [PWRAP_MAN_VLDCLR] = 0x70, 913 [PWRAP_WACS0_EN] = 0x74, 914 [PWRAP_INIT_DONE0] = 0x78, 915 [PWRAP_WACS0_CMD] = 0x7c, 916 [PWRAP_WACS0_RDATA] = 0x80, 917 [PWRAP_WACS0_VLDCLR] = 0x84, 918 [PWRAP_WACS1_EN] = 0x88, 919 [PWRAP_INIT_DONE1] = 0x8c, 920 [PWRAP_WACS1_CMD] = 0x90, 921 [PWRAP_WACS1_RDATA] = 0x94, 922 [PWRAP_WACS1_VLDCLR] = 0x98, 923 [PWRAP_WACS2_EN] = 0x9c, 924 [PWRAP_INIT_DONE2] = 0xa0, 925 [PWRAP_WACS2_CMD] = 0xa4, 926 [PWRAP_WACS2_RDATA] = 0xa8, 927 [PWRAP_WACS2_VLDCLR] = 0xac, 928 [PWRAP_INT_EN] = 0xb0, 929 [PWRAP_INT_FLG_RAW] = 0xb4, 930 [PWRAP_INT_FLG] = 0xb8, 931 [PWRAP_INT_CLR] = 0xbc, 932 [PWRAP_SIG_ADR] = 0xc0, 933 [PWRAP_SIG_MODE] = 0xc4, 934 [PWRAP_SIG_VALUE] = 0xc8, 935 [PWRAP_SIG_ERRVAL] = 0xcc, 936 [PWRAP_CRC_EN] = 0xd0, 937 [PWRAP_EVENT_STA] = 0xd4, 938 [PWRAP_EVENT_STACLR] = 0xd8, 939 [PWRAP_TIMER_EN] = 0xdc, 940 [PWRAP_TIMER_STA] = 0xe0, 941 [PWRAP_WDT_UNIT] = 0xe4, 942 [PWRAP_WDT_SRC_EN] = 0xe8, 943 [PWRAP_WDT_FLG] = 0xec, 944 [PWRAP_DEBUG_INT_SEL] = 0xf0, 945 [PWRAP_CIPHER_KEY_SEL] = 0x134, 946 [PWRAP_CIPHER_IV_SEL] = 0x138, 947 [PWRAP_CIPHER_LOAD] = 0x13c, 948 [PWRAP_CIPHER_START] = 0x140, 949 [PWRAP_CIPHER_RDY] = 0x144, 950 [PWRAP_CIPHER_MODE] = 0x148, 951 [PWRAP_CIPHER_SWRST] = 0x14c, 952 [PWRAP_DCM_EN] = 0x15c, 953 [PWRAP_DCM_DBC_PRD] = 0x160, 954 }; 955 956 static int mt8173_regs[] = { 957 [PWRAP_MUX_SEL] = 0x0, 958 [PWRAP_WRAP_EN] = 0x4, 959 [PWRAP_DIO_EN] = 0x8, 960 [PWRAP_SIDLY] = 0xc, 961 [PWRAP_RDDMY] = 0x10, 962 [PWRAP_SI_CK_CON] = 0x14, 963 [PWRAP_CSHEXT_WRITE] = 0x18, 964 [PWRAP_CSHEXT_READ] = 0x1c, 965 [PWRAP_CSLEXT_START] = 0x20, 966 [PWRAP_CSLEXT_END] = 0x24, 967 [PWRAP_STAUPD_PRD] = 0x28, 968 [PWRAP_STAUPD_GRPEN] = 0x2c, 969 [PWRAP_STAUPD_MAN_TRIG] = 0x40, 970 [PWRAP_STAUPD_STA] = 0x44, 971 [PWRAP_WRAP_STA] = 0x48, 972 [PWRAP_HARB_INIT] = 0x4c, 973 [PWRAP_HARB_HPRIO] = 0x50, 974 [PWRAP_HIPRIO_ARB_EN] = 0x54, 975 [PWRAP_HARB_STA0] = 0x58, 976 [PWRAP_HARB_STA1] = 0x5c, 977 [PWRAP_MAN_EN] = 0x60, 978 [PWRAP_MAN_CMD] = 0x64, 979 [PWRAP_MAN_RDATA] = 0x68, 980 [PWRAP_MAN_VLDCLR] = 0x6c, 981 [PWRAP_WACS0_EN] = 0x70, 982 [PWRAP_INIT_DONE0] = 0x74, 983 [PWRAP_WACS0_CMD] = 0x78, 984 [PWRAP_WACS0_RDATA] = 0x7c, 985 [PWRAP_WACS0_VLDCLR] = 0x80, 986 [PWRAP_WACS1_EN] = 0x84, 987 [PWRAP_INIT_DONE1] = 0x88, 988 [PWRAP_WACS1_CMD] = 0x8c, 989 [PWRAP_WACS1_RDATA] = 0x90, 990 [PWRAP_WACS1_VLDCLR] = 0x94, 991 [PWRAP_WACS2_EN] = 0x98, 992 [PWRAP_INIT_DONE2] = 0x9c, 993 [PWRAP_WACS2_CMD] = 0xa0, 994 [PWRAP_WACS2_RDATA] = 0xa4, 995 [PWRAP_WACS2_VLDCLR] = 0xa8, 996 [PWRAP_INT_EN] = 0xac, 997 [PWRAP_INT_FLG_RAW] = 0xb0, 998 [PWRAP_INT_FLG] = 0xb4, 999 [PWRAP_INT_CLR] = 0xb8, 1000 [PWRAP_SIG_ADR] = 0xbc, 1001 [PWRAP_SIG_MODE] = 0xc0, 1002 [PWRAP_SIG_VALUE] = 0xc4, 1003 [PWRAP_SIG_ERRVAL] = 0xc8, 1004 [PWRAP_CRC_EN] = 0xcc, 1005 [PWRAP_TIMER_EN] = 0xd0, 1006 [PWRAP_TIMER_STA] = 0xd4, 1007 [PWRAP_WDT_UNIT] = 0xd8, 1008 [PWRAP_WDT_SRC_EN] = 0xdc, 1009 [PWRAP_WDT_FLG] = 0xe0, 1010 [PWRAP_DEBUG_INT_SEL] = 0xe4, 1011 [PWRAP_DVFS_ADR0] = 0xe8, 1012 [PWRAP_DVFS_WDATA0] = 0xec, 1013 [PWRAP_DVFS_ADR1] = 0xf0, 1014 [PWRAP_DVFS_WDATA1] = 0xf4, 1015 [PWRAP_DVFS_ADR2] = 0xf8, 1016 [PWRAP_DVFS_WDATA2] = 0xfc, 1017 [PWRAP_DVFS_ADR3] = 0x100, 1018 [PWRAP_DVFS_WDATA3] = 0x104, 1019 [PWRAP_DVFS_ADR4] = 0x108, 1020 [PWRAP_DVFS_WDATA4] = 0x10c, 1021 [PWRAP_DVFS_ADR5] = 0x110, 1022 [PWRAP_DVFS_WDATA5] = 0x114, 1023 [PWRAP_DVFS_ADR6] = 0x118, 1024 [PWRAP_DVFS_WDATA6] = 0x11c, 1025 [PWRAP_DVFS_ADR7] = 0x120, 1026 [PWRAP_DVFS_WDATA7] = 0x124, 1027 [PWRAP_SPMINF_STA] = 0x128, 1028 [PWRAP_CIPHER_KEY_SEL] = 0x12c, 1029 [PWRAP_CIPHER_IV_SEL] = 0x130, 1030 [PWRAP_CIPHER_EN] = 0x134, 1031 [PWRAP_CIPHER_RDY] = 0x138, 1032 [PWRAP_CIPHER_MODE] = 0x13c, 1033 [PWRAP_CIPHER_SWRST] = 0x140, 1034 [PWRAP_DCM_EN] = 0x144, 1035 [PWRAP_DCM_DBC_PRD] = 0x148, 1036 }; 1037 1038 static int mt8183_regs[] = { 1039 [PWRAP_MUX_SEL] = 0x0, 1040 [PWRAP_WRAP_EN] = 0x4, 1041 [PWRAP_DIO_EN] = 0x8, 1042 [PWRAP_SI_SAMPLE_CTRL] = 0xC, 1043 [PWRAP_RDDMY] = 0x14, 1044 [PWRAP_CSHEXT_WRITE] = 0x18, 1045 [PWRAP_CSHEXT_READ] = 0x1C, 1046 [PWRAP_CSLEXT_WRITE] = 0x20, 1047 [PWRAP_CSLEXT_READ] = 0x24, 1048 [PWRAP_EXT_CK_WRITE] = 0x28, 1049 [PWRAP_STAUPD_CTRL] = 0x30, 1050 [PWRAP_STAUPD_GRPEN] = 0x34, 1051 [PWRAP_EINT_STA0_ADR] = 0x38, 1052 [PWRAP_HARB_HPRIO] = 0x5C, 1053 [PWRAP_HIPRIO_ARB_EN] = 0x60, 1054 [PWRAP_MAN_EN] = 0x70, 1055 [PWRAP_MAN_CMD] = 0x74, 1056 [PWRAP_WACS0_EN] = 0x80, 1057 [PWRAP_INIT_DONE0] = 0x84, 1058 [PWRAP_WACS1_EN] = 0x88, 1059 [PWRAP_INIT_DONE1] = 0x8C, 1060 [PWRAP_WACS2_EN] = 0x90, 1061 [PWRAP_INIT_DONE2] = 0x94, 1062 [PWRAP_WACS_P2P_EN] = 0xA0, 1063 [PWRAP_INIT_DONE_P2P] = 0xA4, 1064 [PWRAP_WACS_MD32_EN] = 0xA8, 1065 [PWRAP_INIT_DONE_MD32] = 0xAC, 1066 [PWRAP_INT_EN] = 0xB0, 1067 [PWRAP_INT_FLG] = 0xB8, 1068 [PWRAP_INT_CLR] = 0xBC, 1069 [PWRAP_INT1_EN] = 0xC0, 1070 [PWRAP_INT1_FLG] = 0xC8, 1071 [PWRAP_INT1_CLR] = 0xCC, 1072 [PWRAP_SIG_ADR] = 0xD0, 1073 [PWRAP_CRC_EN] = 0xE0, 1074 [PWRAP_TIMER_EN] = 0xE4, 1075 [PWRAP_WDT_UNIT] = 0xEC, 1076 [PWRAP_WDT_SRC_EN] = 0xF0, 1077 [PWRAP_WDT_SRC_EN_1] = 0xF4, 1078 [PWRAP_INT_GPS_AUXADC_CMD_ADDR] = 0x1DC, 1079 [PWRAP_INT_GPS_AUXADC_CMD] = 0x1E0, 1080 [PWRAP_INT_GPS_AUXADC_RDATA_ADDR] = 0x1E4, 1081 [PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] = 0x1E8, 1082 [PWRAP_GPSINF_0_STA] = 0x1EC, 1083 [PWRAP_GPSINF_1_STA] = 0x1F0, 1084 [PWRAP_WACS2_CMD] = 0xC20, 1085 [PWRAP_WACS2_RDATA] = 0xC24, 1086 [PWRAP_WACS2_VLDCLR] = 0xC28, 1087 }; 1088 1089 static int mt8195_regs[] = { 1090 [PWRAP_INIT_DONE2] = 0x0, 1091 [PWRAP_STAUPD_CTRL] = 0x4C, 1092 [PWRAP_TIMER_EN] = 0x3E4, 1093 [PWRAP_INT_EN] = 0x420, 1094 [PWRAP_INT_FLG] = 0x428, 1095 [PWRAP_INT_CLR] = 0x42C, 1096 [PWRAP_INT1_EN] = 0x450, 1097 [PWRAP_INT1_FLG] = 0x458, 1098 [PWRAP_INT1_CLR] = 0x45C, 1099 [PWRAP_WACS2_CMD] = 0x880, 1100 [PWRAP_SWINF_2_WDATA_31_0] = 0x884, 1101 [PWRAP_SWINF_2_RDATA_31_0] = 0x894, 1102 [PWRAP_WACS2_VLDCLR] = 0x8A4, 1103 [PWRAP_WACS2_RDATA] = 0x8A8, 1104 }; 1105 1106 static int mt8365_regs[] = { 1107 [PWRAP_MUX_SEL] = 0x0, 1108 [PWRAP_WRAP_EN] = 0x4, 1109 [PWRAP_DIO_EN] = 0x8, 1110 [PWRAP_CSHEXT_WRITE] = 0x24, 1111 [PWRAP_CSHEXT_READ] = 0x28, 1112 [PWRAP_STAUPD_PRD] = 0x3c, 1113 [PWRAP_STAUPD_GRPEN] = 0x40, 1114 [PWRAP_STAUPD_MAN_TRIG] = 0x58, 1115 [PWRAP_STAUPD_STA] = 0x5c, 1116 [PWRAP_WRAP_STA] = 0x60, 1117 [PWRAP_HARB_INIT] = 0x64, 1118 [PWRAP_HARB_HPRIO] = 0x68, 1119 [PWRAP_HIPRIO_ARB_EN] = 0x6c, 1120 [PWRAP_HARB_STA0] = 0x70, 1121 [PWRAP_HARB_STA1] = 0x74, 1122 [PWRAP_MAN_EN] = 0x7c, 1123 [PWRAP_MAN_CMD] = 0x80, 1124 [PWRAP_MAN_RDATA] = 0x84, 1125 [PWRAP_MAN_VLDCLR] = 0x88, 1126 [PWRAP_WACS0_EN] = 0x8c, 1127 [PWRAP_INIT_DONE0] = 0x90, 1128 [PWRAP_WACS0_CMD] = 0xc00, 1129 [PWRAP_WACS0_RDATA] = 0xc04, 1130 [PWRAP_WACS0_VLDCLR] = 0xc08, 1131 [PWRAP_WACS1_EN] = 0x94, 1132 [PWRAP_INIT_DONE1] = 0x98, 1133 [PWRAP_WACS2_EN] = 0x9c, 1134 [PWRAP_INIT_DONE2] = 0xa0, 1135 [PWRAP_WACS2_CMD] = 0xc20, 1136 [PWRAP_WACS2_RDATA] = 0xc24, 1137 [PWRAP_WACS2_VLDCLR] = 0xc28, 1138 [PWRAP_INT_EN] = 0xb4, 1139 [PWRAP_INT_FLG_RAW] = 0xb8, 1140 [PWRAP_INT_FLG] = 0xbc, 1141 [PWRAP_INT_CLR] = 0xc0, 1142 [PWRAP_SIG_ADR] = 0xd4, 1143 [PWRAP_SIG_MODE] = 0xd8, 1144 [PWRAP_SIG_VALUE] = 0xdc, 1145 [PWRAP_SIG_ERRVAL] = 0xe0, 1146 [PWRAP_CRC_EN] = 0xe4, 1147 [PWRAP_TIMER_EN] = 0xe8, 1148 [PWRAP_TIMER_STA] = 0xec, 1149 [PWRAP_WDT_UNIT] = 0xf0, 1150 [PWRAP_WDT_SRC_EN] = 0xf4, 1151 [PWRAP_WDT_FLG] = 0xfc, 1152 [PWRAP_DEBUG_INT_SEL] = 0x104, 1153 [PWRAP_CIPHER_KEY_SEL] = 0x1c4, 1154 [PWRAP_CIPHER_IV_SEL] = 0x1c8, 1155 [PWRAP_CIPHER_RDY] = 0x1d0, 1156 [PWRAP_CIPHER_MODE] = 0x1d4, 1157 [PWRAP_CIPHER_SWRST] = 0x1d8, 1158 [PWRAP_DCM_EN] = 0x1dc, 1159 [PWRAP_DCM_DBC_PRD] = 0x1e0, 1160 [PWRAP_EINT_STA0_ADR] = 0x44, 1161 [PWRAP_EINT_STA1_ADR] = 0x48, 1162 [PWRAP_INT1_EN] = 0xc4, 1163 [PWRAP_INT1_FLG] = 0xcc, 1164 [PWRAP_INT1_CLR] = 0xd0, 1165 [PWRAP_WDT_SRC_EN_1] = 0xf8, 1166 }; 1167 1168 static int mt8516_regs[] = { 1169 [PWRAP_MUX_SEL] = 0x0, 1170 [PWRAP_WRAP_EN] = 0x4, 1171 [PWRAP_DIO_EN] = 0x8, 1172 [PWRAP_SIDLY] = 0xc, 1173 [PWRAP_RDDMY] = 0x10, 1174 [PWRAP_SI_CK_CON] = 0x14, 1175 [PWRAP_CSHEXT_WRITE] = 0x18, 1176 [PWRAP_CSHEXT_READ] = 0x1c, 1177 [PWRAP_CSLEXT_START] = 0x20, 1178 [PWRAP_CSLEXT_END] = 0x24, 1179 [PWRAP_STAUPD_PRD] = 0x28, 1180 [PWRAP_STAUPD_GRPEN] = 0x2c, 1181 [PWRAP_STAUPD_MAN_TRIG] = 0x40, 1182 [PWRAP_STAUPD_STA] = 0x44, 1183 [PWRAP_WRAP_STA] = 0x48, 1184 [PWRAP_HARB_INIT] = 0x4c, 1185 [PWRAP_HARB_HPRIO] = 0x50, 1186 [PWRAP_HIPRIO_ARB_EN] = 0x54, 1187 [PWRAP_HARB_STA0] = 0x58, 1188 [PWRAP_HARB_STA1] = 0x5c, 1189 [PWRAP_MAN_EN] = 0x60, 1190 [PWRAP_MAN_CMD] = 0x64, 1191 [PWRAP_MAN_RDATA] = 0x68, 1192 [PWRAP_MAN_VLDCLR] = 0x6c, 1193 [PWRAP_WACS0_EN] = 0x70, 1194 [PWRAP_INIT_DONE0] = 0x74, 1195 [PWRAP_WACS0_CMD] = 0x78, 1196 [PWRAP_WACS0_RDATA] = 0x7c, 1197 [PWRAP_WACS0_VLDCLR] = 0x80, 1198 [PWRAP_WACS1_EN] = 0x84, 1199 [PWRAP_INIT_DONE1] = 0x88, 1200 [PWRAP_WACS1_CMD] = 0x8c, 1201 [PWRAP_WACS1_RDATA] = 0x90, 1202 [PWRAP_WACS1_VLDCLR] = 0x94, 1203 [PWRAP_WACS2_EN] = 0x98, 1204 [PWRAP_INIT_DONE2] = 0x9c, 1205 [PWRAP_WACS2_CMD] = 0xa0, 1206 [PWRAP_WACS2_RDATA] = 0xa4, 1207 [PWRAP_WACS2_VLDCLR] = 0xa8, 1208 [PWRAP_INT_EN] = 0xac, 1209 [PWRAP_INT_FLG_RAW] = 0xb0, 1210 [PWRAP_INT_FLG] = 0xb4, 1211 [PWRAP_INT_CLR] = 0xb8, 1212 [PWRAP_SIG_ADR] = 0xbc, 1213 [PWRAP_SIG_MODE] = 0xc0, 1214 [PWRAP_SIG_VALUE] = 0xc4, 1215 [PWRAP_SIG_ERRVAL] = 0xc8, 1216 [PWRAP_CRC_EN] = 0xcc, 1217 [PWRAP_TIMER_EN] = 0xd0, 1218 [PWRAP_TIMER_STA] = 0xd4, 1219 [PWRAP_WDT_UNIT] = 0xd8, 1220 [PWRAP_WDT_SRC_EN] = 0xdc, 1221 [PWRAP_WDT_FLG] = 0xe0, 1222 [PWRAP_DEBUG_INT_SEL] = 0xe4, 1223 [PWRAP_DVFS_ADR0] = 0xe8, 1224 [PWRAP_DVFS_WDATA0] = 0xec, 1225 [PWRAP_DVFS_ADR1] = 0xf0, 1226 [PWRAP_DVFS_WDATA1] = 0xf4, 1227 [PWRAP_DVFS_ADR2] = 0xf8, 1228 [PWRAP_DVFS_WDATA2] = 0xfc, 1229 [PWRAP_DVFS_ADR3] = 0x100, 1230 [PWRAP_DVFS_WDATA3] = 0x104, 1231 [PWRAP_DVFS_ADR4] = 0x108, 1232 [PWRAP_DVFS_WDATA4] = 0x10c, 1233 [PWRAP_DVFS_ADR5] = 0x110, 1234 [PWRAP_DVFS_WDATA5] = 0x114, 1235 [PWRAP_DVFS_ADR6] = 0x118, 1236 [PWRAP_DVFS_WDATA6] = 0x11c, 1237 [PWRAP_DVFS_ADR7] = 0x120, 1238 [PWRAP_DVFS_WDATA7] = 0x124, 1239 [PWRAP_SPMINF_STA] = 0x128, 1240 [PWRAP_CIPHER_KEY_SEL] = 0x12c, 1241 [PWRAP_CIPHER_IV_SEL] = 0x130, 1242 [PWRAP_CIPHER_EN] = 0x134, 1243 [PWRAP_CIPHER_RDY] = 0x138, 1244 [PWRAP_CIPHER_MODE] = 0x13c, 1245 [PWRAP_CIPHER_SWRST] = 0x140, 1246 [PWRAP_DCM_EN] = 0x144, 1247 [PWRAP_DCM_DBC_PRD] = 0x148, 1248 [PWRAP_SW_RST] = 0x168, 1249 [PWRAP_OP_TYPE] = 0x16c, 1250 [PWRAP_MSB_FIRST] = 0x170, 1251 }; 1252 1253 static int mt8186_regs[] = { 1254 [PWRAP_MUX_SEL] = 0x0, 1255 [PWRAP_WRAP_EN] = 0x4, 1256 [PWRAP_DIO_EN] = 0x8, 1257 [PWRAP_RDDMY] = 0x20, 1258 [PWRAP_CSHEXT_WRITE] = 0x24, 1259 [PWRAP_CSHEXT_READ] = 0x28, 1260 [PWRAP_CSLEXT_WRITE] = 0x2C, 1261 [PWRAP_CSLEXT_READ] = 0x30, 1262 [PWRAP_EXT_CK_WRITE] = 0x34, 1263 [PWRAP_STAUPD_CTRL] = 0x3C, 1264 [PWRAP_STAUPD_GRPEN] = 0x40, 1265 [PWRAP_EINT_STA0_ADR] = 0x44, 1266 [PWRAP_EINT_STA1_ADR] = 0x48, 1267 [PWRAP_INT_CLR] = 0xC8, 1268 [PWRAP_INT_FLG] = 0xC4, 1269 [PWRAP_MAN_EN] = 0x7C, 1270 [PWRAP_MAN_CMD] = 0x80, 1271 [PWRAP_WACS0_EN] = 0x8C, 1272 [PWRAP_WACS1_EN] = 0x94, 1273 [PWRAP_WACS2_EN] = 0x9C, 1274 [PWRAP_INIT_DONE0] = 0x90, 1275 [PWRAP_INIT_DONE1] = 0x98, 1276 [PWRAP_INIT_DONE2] = 0xA0, 1277 [PWRAP_INT_EN] = 0xBC, 1278 [PWRAP_INT1_EN] = 0xCC, 1279 [PWRAP_INT1_FLG] = 0xD4, 1280 [PWRAP_INT1_CLR] = 0xD8, 1281 [PWRAP_TIMER_EN] = 0xF0, 1282 [PWRAP_WDT_UNIT] = 0xF8, 1283 [PWRAP_WDT_SRC_EN] = 0xFC, 1284 [PWRAP_WDT_SRC_EN_1] = 0x100, 1285 [PWRAP_WDT_FLG] = 0x104, 1286 [PWRAP_SPMINF_STA] = 0x1B4, 1287 [PWRAP_DCM_EN] = 0x1EC, 1288 [PWRAP_DCM_DBC_PRD] = 0x1F0, 1289 [PWRAP_GPSINF_0_STA] = 0x204, 1290 [PWRAP_GPSINF_1_STA] = 0x208, 1291 [PWRAP_WACS0_CMD] = 0xC00, 1292 [PWRAP_WACS0_RDATA] = 0xC04, 1293 [PWRAP_WACS0_VLDCLR] = 0xC08, 1294 [PWRAP_WACS1_CMD] = 0xC10, 1295 [PWRAP_WACS1_RDATA] = 0xC14, 1296 [PWRAP_WACS1_VLDCLR] = 0xC18, 1297 [PWRAP_WACS2_CMD] = 0xC20, 1298 [PWRAP_WACS2_RDATA] = 0xC24, 1299 [PWRAP_WACS2_VLDCLR] = 0xC28, 1300 }; 1301 1302 enum pmic_type { 1303 PMIC_MT6323, 1304 PMIC_MT6331, 1305 PMIC_MT6332, 1306 PMIC_MT6351, 1307 PMIC_MT6357, 1308 PMIC_MT6358, 1309 PMIC_MT6359, 1310 PMIC_MT6380, 1311 PMIC_MT6397, 1312 }; 1313 1314 enum pwrap_type { 1315 PWRAP_MT2701, 1316 PWRAP_MT6765, 1317 PWRAP_MT6779, 1318 PWRAP_MT6795, 1319 PWRAP_MT6797, 1320 PWRAP_MT6873, 1321 PWRAP_MT7622, 1322 PWRAP_MT8135, 1323 PWRAP_MT8173, 1324 PWRAP_MT8183, 1325 PWRAP_MT8186, 1326 PWRAP_MT8195, 1327 PWRAP_MT8365, 1328 PWRAP_MT8516, 1329 }; 1330 1331 struct pmic_wrapper; 1332 1333 struct pwrap_slv_regops { 1334 const struct regmap_config *regmap; 1335 /* 1336 * pwrap operations are highly associated with the PMIC types, 1337 * so the pointers added increases flexibility allowing determination 1338 * which type is used by the detection through device tree. 1339 */ 1340 int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata); 1341 int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata); 1342 }; 1343 1344 /** 1345 * struct pwrap_slv_type - PMIC device wrapper definitions 1346 * @dew_regs: Device Wrapper (DeW) register offsets 1347 * @type: PMIC Type (model) 1348 * @comp_dew_regs: Device Wrapper (DeW) register offsets for companion device 1349 * @comp_type: Companion PMIC Type (model) 1350 * @regops: Register R/W ops 1351 * @caps: Capability flags for the target device 1352 */ 1353 struct pwrap_slv_type { 1354 const u32 *dew_regs; 1355 enum pmic_type type; 1356 const u32 *comp_dew_regs; 1357 enum pmic_type comp_type; 1358 const struct pwrap_slv_regops *regops; 1359 u32 caps; 1360 }; 1361 1362 struct pmic_wrapper { 1363 struct device *dev; 1364 void __iomem *base; 1365 struct regmap *regmap; 1366 const struct pmic_wrapper_type *master; 1367 const struct pwrap_slv_type *slave; 1368 struct clk *clk_spi; 1369 struct clk *clk_wrap; 1370 struct clk *clk_sys; 1371 struct clk *clk_tmr; 1372 struct reset_control *rstc; 1373 1374 struct reset_control *rstc_bridge; 1375 void __iomem *bridge_base; 1376 }; 1377 1378 struct pmic_wrapper_type { 1379 int *regs; 1380 enum pwrap_type type; 1381 u32 arb_en_all; 1382 u32 int_en_all; 1383 u32 int1_en_all; 1384 u32 spi_w; 1385 u32 wdt_src; 1386 /* Flags indicating the capability for the target pwrap */ 1387 u32 caps; 1388 int (*init_reg_clock)(struct pmic_wrapper *wrp); 1389 int (*init_soc_specific)(struct pmic_wrapper *wrp); 1390 }; 1391 1392 static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg) 1393 { 1394 return readl(wrp->base + wrp->master->regs[reg]); 1395 } 1396 1397 static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg) 1398 { 1399 writel(val, wrp->base + wrp->master->regs[reg]); 1400 } 1401 1402 static u32 pwrap_get_fsm_state(struct pmic_wrapper *wrp) 1403 { 1404 u32 val; 1405 1406 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); 1407 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 1408 return PWRAP_GET_WACS_ARB_FSM(val); 1409 else 1410 return PWRAP_GET_WACS_FSM(val); 1411 } 1412 1413 static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp) 1414 { 1415 return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_IDLE; 1416 } 1417 1418 static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp) 1419 { 1420 return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_WFVLDCLR; 1421 } 1422 1423 /* 1424 * Timeout issue sometimes caused by the last read command 1425 * failed because pmic wrap could not got the FSM_VLDCLR 1426 * in time after finishing WACS2_CMD. It made state machine 1427 * still on FSM_VLDCLR and timeout next time. 1428 * Check the status of FSM and clear the vldclr to recovery the 1429 * error. 1430 */ 1431 static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp) 1432 { 1433 if (pwrap_is_fsm_vldclr(wrp)) 1434 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); 1435 } 1436 1437 static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp) 1438 { 1439 return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0; 1440 } 1441 1442 static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp) 1443 { 1444 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); 1445 1446 return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) && 1447 (val & PWRAP_STATE_SYNC_IDLE0); 1448 } 1449 1450 static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) 1451 { 1452 bool tmp; 1453 int ret; 1454 u32 val; 1455 1456 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp, 1457 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1458 if (ret) { 1459 pwrap_leave_fsm_vldclr(wrp); 1460 return ret; 1461 } 1462 1463 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 1464 val = adr; 1465 else 1466 val = (adr >> 1) << 16; 1467 pwrap_writel(wrp, val, PWRAP_WACS2_CMD); 1468 1469 ret = readx_poll_timeout(pwrap_is_fsm_vldclr, wrp, tmp, tmp, 1470 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1471 if (ret) 1472 return ret; 1473 1474 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 1475 val = pwrap_readl(wrp, PWRAP_SWINF_2_RDATA_31_0); 1476 else 1477 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); 1478 *rdata = PWRAP_GET_WACS_RDATA(val); 1479 1480 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); 1481 1482 return 0; 1483 } 1484 1485 static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) 1486 { 1487 bool tmp; 1488 int ret, msb; 1489 1490 *rdata = 0; 1491 for (msb = 0; msb < 2; msb++) { 1492 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp, 1493 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1494 1495 if (ret) { 1496 pwrap_leave_fsm_vldclr(wrp); 1497 return ret; 1498 } 1499 1500 pwrap_writel(wrp, ((msb << 30) | (adr << 16)), 1501 PWRAP_WACS2_CMD); 1502 1503 ret = readx_poll_timeout(pwrap_is_fsm_vldclr, wrp, tmp, tmp, 1504 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1505 if (ret) 1506 return ret; 1507 1508 *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, 1509 PWRAP_WACS2_RDATA)) << (16 * msb)); 1510 1511 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); 1512 } 1513 1514 return 0; 1515 } 1516 1517 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) 1518 { 1519 return wrp->slave->regops->pwrap_read(wrp, adr, rdata); 1520 } 1521 1522 static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata) 1523 { 1524 bool tmp; 1525 int ret; 1526 1527 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp, 1528 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1529 if (ret) { 1530 pwrap_leave_fsm_vldclr(wrp); 1531 return ret; 1532 } 1533 1534 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) { 1535 pwrap_writel(wrp, wdata, PWRAP_SWINF_2_WDATA_31_0); 1536 pwrap_writel(wrp, BIT(29) | adr, PWRAP_WACS2_CMD); 1537 } else { 1538 pwrap_writel(wrp, BIT(31) | ((adr >> 1) << 16) | wdata, 1539 PWRAP_WACS2_CMD); 1540 } 1541 1542 return 0; 1543 } 1544 1545 static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata) 1546 { 1547 bool tmp; 1548 int ret, msb, rdata; 1549 1550 for (msb = 0; msb < 2; msb++) { 1551 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp, 1552 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1553 if (ret) { 1554 pwrap_leave_fsm_vldclr(wrp); 1555 return ret; 1556 } 1557 1558 pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) | 1559 ((wdata >> (msb * 16)) & 0xffff), 1560 PWRAP_WACS2_CMD); 1561 1562 /* 1563 * The pwrap_read operation is the requirement of hardware used 1564 * for the synchronization between two successive 16-bit 1565 * pwrap_writel operations composing one 32-bit bus writing. 1566 * Otherwise, we'll find the result fails on the lower 16-bit 1567 * pwrap writing. 1568 */ 1569 if (!msb) 1570 pwrap_read(wrp, adr, &rdata); 1571 } 1572 1573 return 0; 1574 } 1575 1576 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata) 1577 { 1578 return wrp->slave->regops->pwrap_write(wrp, adr, wdata); 1579 } 1580 1581 static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata) 1582 { 1583 return pwrap_read(context, adr, rdata); 1584 } 1585 1586 static int pwrap_regmap_write(void *context, u32 adr, u32 wdata) 1587 { 1588 return pwrap_write(context, adr, wdata); 1589 } 1590 1591 static bool pwrap_pmic_read_test(struct pmic_wrapper *wrp, const u32 *dew_regs, 1592 u16 read_test_val) 1593 { 1594 bool is_success; 1595 u32 rdata; 1596 1597 pwrap_read(wrp, dew_regs[PWRAP_DEW_READ_TEST], &rdata); 1598 is_success = ((rdata & U16_MAX) == read_test_val); 1599 1600 return is_success; 1601 } 1602 1603 static int pwrap_reset_spislave(struct pmic_wrapper *wrp) 1604 { 1605 bool tmp; 1606 int ret, i; 1607 1608 pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN); 1609 pwrap_writel(wrp, 0, PWRAP_WRAP_EN); 1610 pwrap_writel(wrp, 1, PWRAP_MUX_SEL); 1611 pwrap_writel(wrp, 1, PWRAP_MAN_EN); 1612 pwrap_writel(wrp, 0, PWRAP_DIO_EN); 1613 1614 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL, 1615 PWRAP_MAN_CMD); 1616 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS, 1617 PWRAP_MAN_CMD); 1618 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH, 1619 PWRAP_MAN_CMD); 1620 1621 for (i = 0; i < 4; i++) 1622 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS, 1623 PWRAP_MAN_CMD); 1624 1625 ret = readx_poll_timeout(pwrap_is_sync_idle, wrp, tmp, tmp, 1626 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1627 if (ret) { 1628 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); 1629 return ret; 1630 } 1631 1632 pwrap_writel(wrp, 0, PWRAP_MAN_EN); 1633 pwrap_writel(wrp, 0, PWRAP_MUX_SEL); 1634 1635 return 0; 1636 } 1637 1638 /* 1639 * pwrap_init_sidly - configure serial input delay 1640 * 1641 * This configures the serial input delay. We can configure 0, 2, 4 or 6ns 1642 * delay. Do a read test with all possible values and chose the best delay. 1643 */ 1644 static int pwrap_init_sidly(struct pmic_wrapper *wrp) 1645 { 1646 u32 i; 1647 u32 pass = 0; 1648 bool read_ok; 1649 signed char dly[16] = { 1650 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1 1651 }; 1652 1653 for (i = 0; i < 4; i++) { 1654 pwrap_writel(wrp, i, PWRAP_SIDLY); 1655 read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, 1656 PWRAP_DEW_READ_TEST_VAL); 1657 if (read_ok) { 1658 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i); 1659 pass |= 1 << i; 1660 } 1661 } 1662 1663 if (dly[pass] < 0) { 1664 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n", 1665 pass); 1666 return -EIO; 1667 } 1668 1669 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY); 1670 1671 return 0; 1672 } 1673 1674 static int pwrap_init_dual_io(struct pmic_wrapper *wrp) 1675 { 1676 int ret; 1677 bool read_ok, tmp; 1678 bool comp_read_ok = true; 1679 1680 /* Enable dual IO mode */ 1681 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1); 1682 if (wrp->slave->comp_dew_regs) 1683 pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_DIO_EN], 1); 1684 1685 /* Check IDLE & INIT_DONE in advance */ 1686 ret = readx_poll_timeout(pwrap_is_fsm_idle_and_sync_idle, wrp, tmp, tmp, 1687 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1688 if (ret) { 1689 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); 1690 return ret; 1691 } 1692 1693 pwrap_writel(wrp, 1, PWRAP_DIO_EN); 1694 1695 /* Read Test */ 1696 read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, PWRAP_DEW_READ_TEST_VAL); 1697 if (wrp->slave->comp_dew_regs) 1698 comp_read_ok = pwrap_pmic_read_test(wrp, wrp->slave->comp_dew_regs, 1699 PWRAP_DEW_COMP_READ_TEST_VAL); 1700 if (!read_ok || !comp_read_ok) { 1701 dev_err(wrp->dev, "Read failed on DIO mode. Main PMIC %s%s\n", 1702 !read_ok ? "fail" : "success", 1703 wrp->slave->comp_dew_regs && !comp_read_ok ? 1704 ", Companion PMIC fail" : ""); 1705 return -EFAULT; 1706 } 1707 1708 return 0; 1709 } 1710 1711 /* 1712 * pwrap_init_chip_select_ext is used to configure CS extension time for each 1713 * phase during data transactions on the pwrap bus. 1714 */ 1715 static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write, 1716 u8 hext_read, u8 lext_start, 1717 u8 lext_end) 1718 { 1719 /* 1720 * After finishing a write and read transaction, extends CS high time 1721 * to be at least xT of BUS CLK as hext_write and hext_read specifies 1722 * respectively. 1723 */ 1724 pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE); 1725 pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ); 1726 1727 /* 1728 * Extends CS low time after CSL and before CSH command to be at 1729 * least xT of BUS CLK as lext_start and lext_end specifies 1730 * respectively. 1731 */ 1732 pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START); 1733 pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END); 1734 } 1735 1736 static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp) 1737 { 1738 switch (wrp->master->type) { 1739 case PWRAP_MT6795: 1740 if (wrp->slave->type == PMIC_MT6331) { 1741 const u32 *dew_regs = wrp->slave->dew_regs; 1742 1743 pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8); 1744 1745 if (wrp->slave->comp_type == PMIC_MT6332) { 1746 dew_regs = wrp->slave->comp_dew_regs; 1747 pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8); 1748 } 1749 } 1750 pwrap_writel(wrp, 0x88, PWRAP_RDDMY); 1751 pwrap_init_chip_select_ext(wrp, 15, 15, 15, 15); 1752 break; 1753 case PWRAP_MT8173: 1754 pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2); 1755 break; 1756 case PWRAP_MT8135: 1757 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT); 1758 pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0); 1759 break; 1760 default: 1761 break; 1762 } 1763 1764 return 0; 1765 } 1766 1767 static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp) 1768 { 1769 switch (wrp->slave->type) { 1770 case PMIC_MT6397: 1771 pwrap_writel(wrp, 0xc, PWRAP_RDDMY); 1772 pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2); 1773 break; 1774 1775 case PMIC_MT6323: 1776 pwrap_writel(wrp, 0x8, PWRAP_RDDMY); 1777 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO], 1778 0x8); 1779 pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2); 1780 break; 1781 default: 1782 break; 1783 } 1784 1785 return 0; 1786 } 1787 1788 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp) 1789 { 1790 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1; 1791 } 1792 1793 static bool __pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp, const u32 *dew_regs) 1794 { 1795 u32 rdata; 1796 int ret; 1797 1798 ret = pwrap_read(wrp, dew_regs[PWRAP_DEW_CIPHER_RDY], &rdata); 1799 if (ret) 1800 return false; 1801 1802 return rdata == 1; 1803 } 1804 1805 1806 static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp) 1807 { 1808 bool ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->dew_regs); 1809 1810 if (!ret) 1811 return ret; 1812 1813 /* If there's any companion, wait for it to be ready too */ 1814 if (wrp->slave->comp_dew_regs) 1815 ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->comp_dew_regs); 1816 1817 return ret; 1818 } 1819 1820 static void pwrap_config_cipher(struct pmic_wrapper *wrp, const u32 *dew_regs) 1821 { 1822 pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1); 1823 pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0); 1824 pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1); 1825 pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2); 1826 } 1827 1828 static int pwrap_init_cipher(struct pmic_wrapper *wrp) 1829 { 1830 int ret; 1831 bool tmp; 1832 u32 rdata = 0; 1833 1834 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST); 1835 pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST); 1836 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL); 1837 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL); 1838 1839 switch (wrp->master->type) { 1840 case PWRAP_MT8135: 1841 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD); 1842 pwrap_writel(wrp, 1, PWRAP_CIPHER_START); 1843 break; 1844 case PWRAP_MT2701: 1845 case PWRAP_MT6765: 1846 case PWRAP_MT6779: 1847 case PWRAP_MT6795: 1848 case PWRAP_MT6797: 1849 case PWRAP_MT8173: 1850 case PWRAP_MT8186: 1851 case PWRAP_MT8365: 1852 case PWRAP_MT8516: 1853 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN); 1854 break; 1855 case PWRAP_MT7622: 1856 pwrap_writel(wrp, 0, PWRAP_CIPHER_EN); 1857 break; 1858 case PWRAP_MT6873: 1859 case PWRAP_MT8183: 1860 case PWRAP_MT8195: 1861 break; 1862 } 1863 1864 /* Config cipher mode @PMIC */ 1865 pwrap_config_cipher(wrp, wrp->slave->dew_regs); 1866 1867 /* If there is any companion PMIC, configure cipher mode there too */ 1868 if (wrp->slave->comp_type > 0) 1869 pwrap_config_cipher(wrp, wrp->slave->comp_dew_regs); 1870 1871 switch (wrp->slave->type) { 1872 case PMIC_MT6397: 1873 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 1874 0x1); 1875 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START], 1876 0x1); 1877 break; 1878 case PMIC_MT6323: 1879 case PMIC_MT6351: 1880 case PMIC_MT6357: 1881 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN], 1882 0x1); 1883 break; 1884 default: 1885 break; 1886 } 1887 1888 /* wait for cipher data ready@AP */ 1889 ret = readx_poll_timeout(pwrap_is_cipher_ready, wrp, tmp, tmp, 1890 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1891 if (ret) { 1892 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret); 1893 return ret; 1894 } 1895 1896 /* wait for cipher data ready@PMIC */ 1897 ret = readx_poll_timeout(pwrap_is_pmic_cipher_ready, wrp, tmp, tmp, 1898 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1899 if (ret) { 1900 dev_err(wrp->dev, 1901 "timeout waiting for cipher data ready@PMIC\n"); 1902 return ret; 1903 } 1904 1905 /* wait for cipher mode idle */ 1906 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1); 1907 ret = readx_poll_timeout(pwrap_is_fsm_idle_and_sync_idle, wrp, tmp, tmp, 1908 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US); 1909 if (ret) { 1910 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret); 1911 return ret; 1912 } 1913 1914 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE); 1915 1916 /* Write Test */ 1917 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST], 1918 PWRAP_DEW_WRITE_TEST_VAL) || 1919 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST], 1920 &rdata) || 1921 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) { 1922 dev_err(wrp->dev, "rdata=0x%04X\n", rdata); 1923 return -EFAULT; 1924 } 1925 1926 return 0; 1927 } 1928 1929 static int pwrap_init_security(struct pmic_wrapper *wrp) 1930 { 1931 u32 crc_val; 1932 int ret; 1933 1934 /* Enable encryption */ 1935 ret = pwrap_init_cipher(wrp); 1936 if (ret) 1937 return ret; 1938 1939 /* Signature checking - using CRC */ 1940 ret = pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1); 1941 if (ret == 0 && wrp->slave->comp_dew_regs) 1942 ret = pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_EN], 0x1); 1943 1944 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN); 1945 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE); 1946 1947 /* CRC value */ 1948 crc_val = wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL]; 1949 if (wrp->slave->comp_dew_regs) 1950 crc_val |= wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_VAL] << 16; 1951 1952 pwrap_writel(wrp, crc_val, PWRAP_SIG_ADR); 1953 1954 /* PMIC Wrapper Arbiter priority */ 1955 pwrap_writel(wrp, 1956 wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); 1957 1958 return 0; 1959 } 1960 1961 static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp) 1962 { 1963 /* enable pwrap events and pwrap bridge in AP side */ 1964 pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN); 1965 pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN); 1966 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN); 1967 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN); 1968 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN); 1969 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT); 1970 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN); 1971 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN); 1972 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN); 1973 1974 /* enable PMIC event out and sources */ 1975 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN], 1976 0x1) || 1977 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN], 1978 0xffff)) { 1979 dev_err(wrp->dev, "enable dewrap fail\n"); 1980 return -EFAULT; 1981 } 1982 1983 return 0; 1984 } 1985 1986 static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp) 1987 { 1988 /* PMIC_DEWRAP enables */ 1989 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN], 1990 0x1) || 1991 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN], 1992 0xffff)) { 1993 dev_err(wrp->dev, "enable dewrap fail\n"); 1994 return -EFAULT; 1995 } 1996 1997 return 0; 1998 } 1999 2000 static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp) 2001 { 2002 /* GPS_INTF initialization */ 2003 switch (wrp->slave->type) { 2004 case PMIC_MT6323: 2005 pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR); 2006 pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD); 2007 pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR); 2008 pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1); 2009 pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2); 2010 break; 2011 default: 2012 break; 2013 } 2014 2015 return 0; 2016 } 2017 2018 static int pwrap_mt6795_init_soc_specific(struct pmic_wrapper *wrp) 2019 { 2020 pwrap_writel(wrp, 0xf, PWRAP_STAUPD_GRPEN); 2021 2022 if (wrp->slave->type == PMIC_MT6331) 2023 pwrap_writel(wrp, 0x1b4, PWRAP_EINT_STA0_ADR); 2024 2025 if (wrp->slave->comp_type == PMIC_MT6332) 2026 pwrap_writel(wrp, 0x8112, PWRAP_EINT_STA1_ADR); 2027 2028 return 0; 2029 } 2030 2031 static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp) 2032 { 2033 pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD); 2034 /* enable 2wire SPI master */ 2035 pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL); 2036 2037 return 0; 2038 } 2039 2040 static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp) 2041 { 2042 pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN); 2043 2044 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1); 2045 pwrap_writel(wrp, 1, PWRAP_CRC_EN); 2046 pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR); 2047 pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR); 2048 2049 pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN); 2050 pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN); 2051 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P); 2052 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32); 2053 2054 return 0; 2055 } 2056 2057 static int pwrap_init(struct pmic_wrapper *wrp) 2058 { 2059 int ret; 2060 2061 if (wrp->rstc) 2062 reset_control_reset(wrp->rstc); 2063 if (wrp->rstc_bridge) 2064 reset_control_reset(wrp->rstc_bridge); 2065 2066 switch (wrp->master->type) { 2067 case PWRAP_MT6795: 2068 fallthrough; 2069 case PWRAP_MT8173: 2070 /* Enable DCM */ 2071 pwrap_writel(wrp, 3, PWRAP_DCM_EN); 2072 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); 2073 break; 2074 default: 2075 break; 2076 } 2077 2078 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { 2079 /* Reset SPI slave */ 2080 ret = pwrap_reset_spislave(wrp); 2081 if (ret) 2082 return ret; 2083 } 2084 2085 pwrap_writel(wrp, 1, PWRAP_WRAP_EN); 2086 2087 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); 2088 2089 pwrap_writel(wrp, 1, PWRAP_WACS2_EN); 2090 2091 ret = wrp->master->init_reg_clock(wrp); 2092 if (ret) 2093 return ret; 2094 2095 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { 2096 /* Setup serial input delay */ 2097 ret = pwrap_init_sidly(wrp); 2098 if (ret) 2099 return ret; 2100 } 2101 2102 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) { 2103 /* Enable dual I/O mode */ 2104 ret = pwrap_init_dual_io(wrp); 2105 if (ret) 2106 return ret; 2107 } 2108 2109 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) { 2110 /* Enable security on bus */ 2111 ret = pwrap_init_security(wrp); 2112 if (ret) 2113 return ret; 2114 } 2115 2116 if (wrp->master->type == PWRAP_MT8135) 2117 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN); 2118 2119 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN); 2120 pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN); 2121 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN); 2122 pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD); 2123 pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN); 2124 2125 if (wrp->master->init_soc_specific) { 2126 ret = wrp->master->init_soc_specific(wrp); 2127 if (ret) 2128 return ret; 2129 } 2130 2131 /* Setup the init done registers */ 2132 pwrap_writel(wrp, 1, PWRAP_INIT_DONE2); 2133 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0); 2134 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1); 2135 2136 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) { 2137 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3); 2138 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4); 2139 } 2140 2141 return 0; 2142 } 2143 2144 static irqreturn_t pwrap_interrupt(int irqno, void *dev_id) 2145 { 2146 u32 rdata; 2147 struct pmic_wrapper *wrp = dev_id; 2148 2149 rdata = pwrap_readl(wrp, PWRAP_INT_FLG); 2150 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata); 2151 pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR); 2152 2153 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) { 2154 rdata = pwrap_readl(wrp, PWRAP_INT1_FLG); 2155 dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata); 2156 pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR); 2157 } 2158 2159 return IRQ_HANDLED; 2160 } 2161 2162 static const struct regmap_config pwrap_regmap_config16 = { 2163 .reg_bits = 16, 2164 .val_bits = 16, 2165 .reg_stride = 2, 2166 .reg_read = pwrap_regmap_read, 2167 .reg_write = pwrap_regmap_write, 2168 .max_register = 0xffff, 2169 }; 2170 2171 static const struct regmap_config pwrap_regmap_config32 = { 2172 .reg_bits = 32, 2173 .val_bits = 32, 2174 .reg_stride = 4, 2175 .reg_read = pwrap_regmap_read, 2176 .reg_write = pwrap_regmap_write, 2177 .max_register = 0xffff, 2178 }; 2179 2180 static const struct pwrap_slv_regops pwrap_regops16 = { 2181 .pwrap_read = pwrap_read16, 2182 .pwrap_write = pwrap_write16, 2183 .regmap = &pwrap_regmap_config16, 2184 }; 2185 2186 static const struct pwrap_slv_regops pwrap_regops32 = { 2187 .pwrap_read = pwrap_read32, 2188 .pwrap_write = pwrap_write32, 2189 .regmap = &pwrap_regmap_config32, 2190 }; 2191 2192 static const struct pwrap_slv_type pmic_mt6323 = { 2193 .dew_regs = mt6323_regs, 2194 .type = PMIC_MT6323, 2195 .regops = &pwrap_regops16, 2196 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | 2197 PWRAP_SLV_CAP_SECURITY, 2198 }; 2199 2200 static const struct pwrap_slv_type pmic_mt6331 = { 2201 .dew_regs = mt6331_regs, 2202 .type = PMIC_MT6331, 2203 .comp_dew_regs = mt6332_regs, 2204 .comp_type = PMIC_MT6332, 2205 .regops = &pwrap_regops16, 2206 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | 2207 PWRAP_SLV_CAP_SECURITY, 2208 }; 2209 2210 static const struct pwrap_slv_type pmic_mt6351 = { 2211 .dew_regs = mt6351_regs, 2212 .type = PMIC_MT6351, 2213 .regops = &pwrap_regops16, 2214 .caps = 0, 2215 }; 2216 2217 static const struct pwrap_slv_type pmic_mt6357 = { 2218 .dew_regs = mt6357_regs, 2219 .type = PMIC_MT6357, 2220 .regops = &pwrap_regops16, 2221 .caps = 0, 2222 }; 2223 2224 static const struct pwrap_slv_type pmic_mt6358 = { 2225 .dew_regs = mt6358_regs, 2226 .type = PMIC_MT6358, 2227 .regops = &pwrap_regops16, 2228 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO, 2229 }; 2230 2231 static const struct pwrap_slv_type pmic_mt6359 = { 2232 .dew_regs = mt6359_regs, 2233 .type = PMIC_MT6359, 2234 .regops = &pwrap_regops16, 2235 .caps = PWRAP_SLV_CAP_DUALIO, 2236 }; 2237 2238 static const struct pwrap_slv_type pmic_mt6380 = { 2239 .dew_regs = NULL, 2240 .type = PMIC_MT6380, 2241 .regops = &pwrap_regops32, 2242 .caps = 0, 2243 }; 2244 2245 static const struct pwrap_slv_type pmic_mt6397 = { 2246 .dew_regs = mt6397_regs, 2247 .type = PMIC_MT6397, 2248 .regops = &pwrap_regops16, 2249 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | 2250 PWRAP_SLV_CAP_SECURITY, 2251 }; 2252 2253 static const struct of_device_id of_slave_match_tbl[] = { 2254 { .compatible = "mediatek,mt6323", .data = &pmic_mt6323 }, 2255 { .compatible = "mediatek,mt6331", .data = &pmic_mt6331 }, 2256 { .compatible = "mediatek,mt6351", .data = &pmic_mt6351 }, 2257 { .compatible = "mediatek,mt6357", .data = &pmic_mt6357 }, 2258 { .compatible = "mediatek,mt6358", .data = &pmic_mt6358 }, 2259 { .compatible = "mediatek,mt6359", .data = &pmic_mt6359 }, 2260 2261 /* The MT6380 PMIC only implements a regulator, so we bind it 2262 * directly instead of using a MFD. 2263 */ 2264 { .compatible = "mediatek,mt6380-regulator", .data = &pmic_mt6380 }, 2265 { .compatible = "mediatek,mt6397", .data = &pmic_mt6397 }, 2266 { /* sentinel */ } 2267 }; 2268 MODULE_DEVICE_TABLE(of, of_slave_match_tbl); 2269 2270 static const struct pmic_wrapper_type pwrap_mt2701 = { 2271 .regs = mt2701_regs, 2272 .type = PWRAP_MT2701, 2273 .arb_en_all = 0x3f, 2274 .int_en_all = ~(u32)(BIT(31) | BIT(2)), 2275 .int1_en_all = 0, 2276 .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW, 2277 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2278 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2279 .init_reg_clock = pwrap_mt2701_init_reg_clock, 2280 .init_soc_specific = pwrap_mt2701_init_soc_specific, 2281 }; 2282 2283 static const struct pmic_wrapper_type pwrap_mt6765 = { 2284 .regs = mt6765_regs, 2285 .type = PWRAP_MT6765, 2286 .arb_en_all = 0x3fd35, 2287 .int_en_all = 0xffffffff, 2288 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2289 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2290 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2291 .init_reg_clock = pwrap_common_init_reg_clock, 2292 .init_soc_specific = NULL, 2293 }; 2294 2295 static const struct pmic_wrapper_type pwrap_mt6779 = { 2296 .regs = mt6779_regs, 2297 .type = PWRAP_MT6779, 2298 .arb_en_all = 0xfbb7f, 2299 .int_en_all = 0xfffffffe, 2300 .int1_en_all = 0, 2301 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2302 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2303 .caps = 0, 2304 .init_reg_clock = pwrap_common_init_reg_clock, 2305 .init_soc_specific = NULL, 2306 }; 2307 2308 static const struct pmic_wrapper_type pwrap_mt6795 = { 2309 .regs = mt6795_regs, 2310 .type = PWRAP_MT6795, 2311 .arb_en_all = 0x3f, 2312 .int_en_all = ~(u32)(BIT(31) | BIT(2) | BIT(1)), 2313 .int1_en_all = 0, 2314 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2315 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD, 2316 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2317 .init_reg_clock = pwrap_common_init_reg_clock, 2318 .init_soc_specific = pwrap_mt6795_init_soc_specific, 2319 }; 2320 2321 static const struct pmic_wrapper_type pwrap_mt6797 = { 2322 .regs = mt6797_regs, 2323 .type = PWRAP_MT6797, 2324 .arb_en_all = 0x01fff, 2325 .int_en_all = 0xffffffc6, 2326 .int1_en_all = 0, 2327 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2328 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2329 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2330 .init_reg_clock = pwrap_common_init_reg_clock, 2331 .init_soc_specific = NULL, 2332 }; 2333 2334 static const struct pmic_wrapper_type pwrap_mt6873 = { 2335 .regs = mt6873_regs, 2336 .type = PWRAP_MT6873, 2337 .arb_en_all = 0x777f, 2338 .int_en_all = BIT(4) | BIT(5), 2339 .int1_en_all = 0, 2340 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2341 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2342 .caps = PWRAP_CAP_ARB, 2343 .init_reg_clock = pwrap_common_init_reg_clock, 2344 .init_soc_specific = NULL, 2345 }; 2346 2347 static const struct pmic_wrapper_type pwrap_mt7622 = { 2348 .regs = mt7622_regs, 2349 .type = PWRAP_MT7622, 2350 .arb_en_all = 0xff, 2351 .int_en_all = ~(u32)BIT(31), 2352 .int1_en_all = 0, 2353 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2354 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2355 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2356 .init_reg_clock = pwrap_common_init_reg_clock, 2357 .init_soc_specific = pwrap_mt7622_init_soc_specific, 2358 }; 2359 2360 static const struct pmic_wrapper_type pwrap_mt8135 = { 2361 .regs = mt8135_regs, 2362 .type = PWRAP_MT8135, 2363 .arb_en_all = 0x1ff, 2364 .int_en_all = ~(u32)(BIT(31) | BIT(1)), 2365 .int1_en_all = 0, 2366 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2367 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2368 .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2369 .init_reg_clock = pwrap_common_init_reg_clock, 2370 .init_soc_specific = pwrap_mt8135_init_soc_specific, 2371 }; 2372 2373 static const struct pmic_wrapper_type pwrap_mt8173 = { 2374 .regs = mt8173_regs, 2375 .type = PWRAP_MT8173, 2376 .arb_en_all = 0x3f, 2377 .int_en_all = ~(u32)(BIT(31) | BIT(1)), 2378 .int1_en_all = 0, 2379 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2380 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD, 2381 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 2382 .init_reg_clock = pwrap_common_init_reg_clock, 2383 .init_soc_specific = pwrap_mt8173_init_soc_specific, 2384 }; 2385 2386 static const struct pmic_wrapper_type pwrap_mt8183 = { 2387 .regs = mt8183_regs, 2388 .type = PWRAP_MT8183, 2389 .arb_en_all = 0x3fa75, 2390 .int_en_all = 0xffffffff, 2391 .int1_en_all = 0xeef7ffff, 2392 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2393 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2394 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1, 2395 .init_reg_clock = pwrap_common_init_reg_clock, 2396 .init_soc_specific = pwrap_mt8183_init_soc_specific, 2397 }; 2398 2399 static struct pmic_wrapper_type pwrap_mt8195 = { 2400 .regs = mt8195_regs, 2401 .type = PWRAP_MT8195, 2402 .arb_en_all = 0x777f, /* NEED CONFIRM */ 2403 .int_en_all = 0x180000, /* NEED CONFIRM */ 2404 .int1_en_all = 0, 2405 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2406 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2407 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB, 2408 .init_reg_clock = pwrap_common_init_reg_clock, 2409 .init_soc_specific = NULL, 2410 }; 2411 2412 static const struct pmic_wrapper_type pwrap_mt8365 = { 2413 .regs = mt8365_regs, 2414 .type = PWRAP_MT8365, 2415 .arb_en_all = 0x3ffff, 2416 .int_en_all = 0x7f1fffff, 2417 .int1_en_all = 0x0, 2418 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2419 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2420 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1, 2421 .init_reg_clock = pwrap_common_init_reg_clock, 2422 .init_soc_specific = NULL, 2423 }; 2424 2425 static struct pmic_wrapper_type pwrap_mt8516 = { 2426 .regs = mt8516_regs, 2427 .type = PWRAP_MT8516, 2428 .arb_en_all = 0xff, 2429 .int_en_all = ~(u32)(BIT(31) | BIT(2)), 2430 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2431 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2432 .caps = PWRAP_CAP_DCM, 2433 .init_reg_clock = pwrap_mt2701_init_reg_clock, 2434 .init_soc_specific = NULL, 2435 }; 2436 2437 static struct pmic_wrapper_type pwrap_mt8186 = { 2438 .regs = mt8186_regs, 2439 .type = PWRAP_MT8186, 2440 .arb_en_all = 0xfb27f, 2441 .int_en_all = 0xfffffffe, /* disable WatchDog Timeout for bit 1 */ 2442 .int1_en_all = 0x000017ff, /* disable Matching interrupt for bit 13 */ 2443 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 2444 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 2445 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB_MT8186, 2446 .init_reg_clock = pwrap_common_init_reg_clock, 2447 .init_soc_specific = NULL, 2448 }; 2449 2450 static const struct of_device_id of_pwrap_match_tbl[] = { 2451 { .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701 }, 2452 { .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765 }, 2453 { .compatible = "mediatek,mt6779-pwrap", .data = &pwrap_mt6779 }, 2454 { .compatible = "mediatek,mt6795-pwrap", .data = &pwrap_mt6795 }, 2455 { .compatible = "mediatek,mt6797-pwrap", .data = &pwrap_mt6797 }, 2456 { .compatible = "mediatek,mt6873-pwrap", .data = &pwrap_mt6873 }, 2457 { .compatible = "mediatek,mt7622-pwrap", .data = &pwrap_mt7622 }, 2458 { .compatible = "mediatek,mt8135-pwrap", .data = &pwrap_mt8135 }, 2459 { .compatible = "mediatek,mt8173-pwrap", .data = &pwrap_mt8173 }, 2460 { .compatible = "mediatek,mt8183-pwrap", .data = &pwrap_mt8183 }, 2461 { .compatible = "mediatek,mt8186-pwrap", .data = &pwrap_mt8186 }, 2462 { .compatible = "mediatek,mt8195-pwrap", .data = &pwrap_mt8195 }, 2463 { .compatible = "mediatek,mt8365-pwrap", .data = &pwrap_mt8365 }, 2464 { .compatible = "mediatek,mt8516-pwrap", .data = &pwrap_mt8516 }, 2465 { /* sentinel */ } 2466 }; 2467 MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl); 2468 2469 static int pwrap_probe(struct platform_device *pdev) 2470 { 2471 int ret, irq; 2472 u32 mask_done; 2473 struct pmic_wrapper *wrp; 2474 struct device_node *np = pdev->dev.of_node; 2475 const struct of_device_id *of_slave_id = NULL; 2476 2477 if (np->child) 2478 of_slave_id = of_match_node(of_slave_match_tbl, np->child); 2479 2480 if (!of_slave_id) { 2481 dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n"); 2482 return -EINVAL; 2483 } 2484 2485 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL); 2486 if (!wrp) 2487 return -ENOMEM; 2488 2489 platform_set_drvdata(pdev, wrp); 2490 2491 wrp->master = of_device_get_match_data(&pdev->dev); 2492 wrp->slave = of_slave_id->data; 2493 wrp->dev = &pdev->dev; 2494 2495 wrp->base = devm_platform_ioremap_resource_byname(pdev, "pwrap"); 2496 if (IS_ERR(wrp->base)) 2497 return PTR_ERR(wrp->base); 2498 2499 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) { 2500 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap"); 2501 if (IS_ERR(wrp->rstc)) { 2502 ret = PTR_ERR(wrp->rstc); 2503 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret); 2504 return ret; 2505 } 2506 } 2507 2508 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) { 2509 wrp->bridge_base = devm_platform_ioremap_resource_byname(pdev, "pwrap-bridge"); 2510 if (IS_ERR(wrp->bridge_base)) 2511 return PTR_ERR(wrp->bridge_base); 2512 2513 wrp->rstc_bridge = devm_reset_control_get(wrp->dev, 2514 "pwrap-bridge"); 2515 if (IS_ERR(wrp->rstc_bridge)) { 2516 ret = PTR_ERR(wrp->rstc_bridge); 2517 dev_dbg(wrp->dev, 2518 "cannot get pwrap-bridge reset: %d\n", ret); 2519 return ret; 2520 } 2521 } 2522 2523 wrp->clk_spi = devm_clk_get(wrp->dev, "spi"); 2524 if (IS_ERR(wrp->clk_spi)) { 2525 dev_dbg(wrp->dev, "failed to get clock: %ld\n", 2526 PTR_ERR(wrp->clk_spi)); 2527 return PTR_ERR(wrp->clk_spi); 2528 } 2529 2530 wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap"); 2531 if (IS_ERR(wrp->clk_wrap)) { 2532 dev_dbg(wrp->dev, "failed to get clock: %ld\n", 2533 PTR_ERR(wrp->clk_wrap)); 2534 return PTR_ERR(wrp->clk_wrap); 2535 } 2536 2537 wrp->clk_sys = devm_clk_get_optional(wrp->dev, "sys"); 2538 if (IS_ERR(wrp->clk_sys)) { 2539 return dev_err_probe(wrp->dev, PTR_ERR(wrp->clk_sys), 2540 "failed to get clock: %pe\n", 2541 wrp->clk_sys); 2542 } 2543 2544 wrp->clk_tmr = devm_clk_get_optional(wrp->dev, "tmr"); 2545 if (IS_ERR(wrp->clk_tmr)) { 2546 return dev_err_probe(wrp->dev, PTR_ERR(wrp->clk_tmr), 2547 "failed to get clock: %pe\n", 2548 wrp->clk_tmr); 2549 } 2550 2551 ret = clk_prepare_enable(wrp->clk_spi); 2552 if (ret) 2553 return ret; 2554 2555 ret = clk_prepare_enable(wrp->clk_wrap); 2556 if (ret) 2557 goto err_out1; 2558 2559 ret = clk_prepare_enable(wrp->clk_sys); 2560 if (ret) 2561 goto err_out2; 2562 2563 ret = clk_prepare_enable(wrp->clk_tmr); 2564 if (ret) 2565 goto err_out3; 2566 2567 /* Enable internal dynamic clock */ 2568 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) { 2569 pwrap_writel(wrp, 1, PWRAP_DCM_EN); 2570 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); 2571 } 2572 2573 /* 2574 * The PMIC could already be initialized by the bootloader. 2575 * Skip initialization here in this case. 2576 */ 2577 if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) { 2578 ret = pwrap_init(wrp); 2579 if (ret) { 2580 dev_dbg(wrp->dev, "init failed with %d\n", ret); 2581 goto err_out4; 2582 } 2583 } 2584 2585 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 2586 mask_done = PWRAP_STATE_INIT_DONE1; 2587 else if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB_MT8186)) 2588 mask_done = PWRAP_STATE_INIT_DONE0_MT8186; 2589 else 2590 mask_done = PWRAP_STATE_INIT_DONE0; 2591 2592 if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & mask_done)) { 2593 dev_dbg(wrp->dev, "initialization isn't finished\n"); 2594 ret = -ENODEV; 2595 goto err_out4; 2596 } 2597 2598 /* Initialize watchdog, may not be done by the bootloader */ 2599 if (!HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 2600 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT); 2601 2602 /* 2603 * Since STAUPD was not used on mt8173 platform, 2604 * so STAUPD of WDT_SRC which should be turned off 2605 */ 2606 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN); 2607 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1)) 2608 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1); 2609 2610 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) 2611 pwrap_writel(wrp, 0x3, PWRAP_TIMER_EN); 2612 else 2613 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN); 2614 2615 pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN); 2616 /* 2617 * We add INT1 interrupt to handle starvation and request exception 2618 * If we support it, we should enable it here. 2619 */ 2620 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) 2621 pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN); 2622 2623 irq = platform_get_irq(pdev, 0); 2624 if (irq < 0) { 2625 ret = irq; 2626 goto err_out2; 2627 } 2628 2629 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, 2630 IRQF_TRIGGER_HIGH, 2631 "mt-pmic-pwrap", wrp); 2632 if (ret) 2633 goto err_out4; 2634 2635 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regops->regmap); 2636 if (IS_ERR(wrp->regmap)) { 2637 ret = PTR_ERR(wrp->regmap); 2638 goto err_out2; 2639 } 2640 2641 ret = of_platform_populate(np, NULL, NULL, wrp->dev); 2642 if (ret) { 2643 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n", 2644 np); 2645 goto err_out4; 2646 } 2647 2648 return 0; 2649 2650 err_out4: 2651 clk_disable_unprepare(wrp->clk_tmr); 2652 err_out3: 2653 clk_disable_unprepare(wrp->clk_sys); 2654 err_out2: 2655 clk_disable_unprepare(wrp->clk_wrap); 2656 err_out1: 2657 clk_disable_unprepare(wrp->clk_spi); 2658 2659 return ret; 2660 } 2661 2662 static struct platform_driver pwrap_drv = { 2663 .driver = { 2664 .name = "mt-pmic-pwrap", 2665 .of_match_table = of_pwrap_match_tbl, 2666 }, 2667 .probe = pwrap_probe, 2668 }; 2669 2670 module_platform_driver(pwrap_drv); 2671 2672 MODULE_AUTHOR("Flora Fu, MediaTek"); 2673 MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver"); 2674 MODULE_LICENSE("GPL v2"); 2675