1 /*
2  * Copyright (c) 2014 MediaTek Inc.
3  * Author: Flora Fu, MediaTek
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  */
14 #include <linux/clk.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23 
24 #define PWRAP_MT8135_BRIDGE_IORD_ARB_EN		0x4
25 #define PWRAP_MT8135_BRIDGE_WACS3_EN		0x10
26 #define PWRAP_MT8135_BRIDGE_INIT_DONE3		0x14
27 #define PWRAP_MT8135_BRIDGE_WACS4_EN		0x24
28 #define PWRAP_MT8135_BRIDGE_INIT_DONE4		0x28
29 #define PWRAP_MT8135_BRIDGE_INT_EN		0x38
30 #define PWRAP_MT8135_BRIDGE_TIMER_EN		0x48
31 #define PWRAP_MT8135_BRIDGE_WDT_UNIT		0x50
32 #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN		0x54
33 
34 /* macro for wrapper status */
35 #define PWRAP_GET_WACS_RDATA(x)		(((x) >> 0) & 0x0000ffff)
36 #define PWRAP_GET_WACS_FSM(x)		(((x) >> 16) & 0x00000007)
37 #define PWRAP_GET_WACS_REQ(x)		(((x) >> 19) & 0x00000001)
38 #define PWRAP_STATE_SYNC_IDLE0		(1 << 20)
39 #define PWRAP_STATE_INIT_DONE0		(1 << 21)
40 
41 /* macro for WACS FSM */
42 #define PWRAP_WACS_FSM_IDLE		0x00
43 #define PWRAP_WACS_FSM_REQ		0x02
44 #define PWRAP_WACS_FSM_WFDLE		0x04
45 #define PWRAP_WACS_FSM_WFVLDCLR		0x06
46 #define PWRAP_WACS_INIT_DONE		0x01
47 #define PWRAP_WACS_WACS_SYNC_IDLE	0x01
48 #define PWRAP_WACS_SYNC_BUSY		0x00
49 
50 /* macro for device wrapper default value */
51 #define PWRAP_DEW_READ_TEST_VAL		0x5aa5
52 #define PWRAP_DEW_WRITE_TEST_VAL	0xa55a
53 
54 /* macro for manual command */
55 #define PWRAP_MAN_CMD_SPI_WRITE		(1 << 13)
56 #define PWRAP_MAN_CMD_OP_CSH		(0x0 << 8)
57 #define PWRAP_MAN_CMD_OP_CSL		(0x1 << 8)
58 #define PWRAP_MAN_CMD_OP_CK		(0x2 << 8)
59 #define PWRAP_MAN_CMD_OP_OUTS		(0x8 << 8)
60 #define PWRAP_MAN_CMD_OP_OUTD		(0x9 << 8)
61 #define PWRAP_MAN_CMD_OP_OUTQ		(0xa << 8)
62 
63 /* macro for slave device wrapper registers */
64 #define PWRAP_DEW_BASE			0xbc00
65 #define PWRAP_DEW_EVENT_OUT_EN		(PWRAP_DEW_BASE + 0x0)
66 #define PWRAP_DEW_DIO_EN		(PWRAP_DEW_BASE + 0x2)
67 #define PWRAP_DEW_EVENT_SRC_EN		(PWRAP_DEW_BASE + 0x4)
68 #define PWRAP_DEW_EVENT_SRC		(PWRAP_DEW_BASE + 0x6)
69 #define PWRAP_DEW_EVENT_FLAG		(PWRAP_DEW_BASE + 0x8)
70 #define PWRAP_DEW_READ_TEST		(PWRAP_DEW_BASE + 0xa)
71 #define PWRAP_DEW_WRITE_TEST		(PWRAP_DEW_BASE + 0xc)
72 #define PWRAP_DEW_CRC_EN		(PWRAP_DEW_BASE + 0xe)
73 #define PWRAP_DEW_CRC_VAL		(PWRAP_DEW_BASE + 0x10)
74 #define PWRAP_DEW_MON_GRP_SEL		(PWRAP_DEW_BASE + 0x12)
75 #define PWRAP_DEW_MON_FLAG_SEL		(PWRAP_DEW_BASE + 0x14)
76 #define PWRAP_DEW_EVENT_TEST		(PWRAP_DEW_BASE + 0x16)
77 #define PWRAP_DEW_CIPHER_KEY_SEL	(PWRAP_DEW_BASE + 0x18)
78 #define PWRAP_DEW_CIPHER_IV_SEL		(PWRAP_DEW_BASE + 0x1a)
79 #define PWRAP_DEW_CIPHER_LOAD		(PWRAP_DEW_BASE + 0x1c)
80 #define PWRAP_DEW_CIPHER_START		(PWRAP_DEW_BASE + 0x1e)
81 #define PWRAP_DEW_CIPHER_RDY		(PWRAP_DEW_BASE + 0x20)
82 #define PWRAP_DEW_CIPHER_MODE		(PWRAP_DEW_BASE + 0x22)
83 #define PWRAP_DEW_CIPHER_SWRST		(PWRAP_DEW_BASE + 0x24)
84 #define PWRAP_MT8173_DEW_CIPHER_IV0	(PWRAP_DEW_BASE + 0x26)
85 #define PWRAP_MT8173_DEW_CIPHER_IV1	(PWRAP_DEW_BASE + 0x28)
86 #define PWRAP_MT8173_DEW_CIPHER_IV2	(PWRAP_DEW_BASE + 0x2a)
87 #define PWRAP_MT8173_DEW_CIPHER_IV3	(PWRAP_DEW_BASE + 0x2c)
88 #define PWRAP_MT8173_DEW_CIPHER_IV4	(PWRAP_DEW_BASE + 0x2e)
89 #define PWRAP_MT8173_DEW_CIPHER_IV5	(PWRAP_DEW_BASE + 0x30)
90 
91 enum pwrap_regs {
92 	PWRAP_MUX_SEL,
93 	PWRAP_WRAP_EN,
94 	PWRAP_DIO_EN,
95 	PWRAP_SIDLY,
96 	PWRAP_CSHEXT_WRITE,
97 	PWRAP_CSHEXT_READ,
98 	PWRAP_CSLEXT_START,
99 	PWRAP_CSLEXT_END,
100 	PWRAP_STAUPD_PRD,
101 	PWRAP_STAUPD_GRPEN,
102 	PWRAP_STAUPD_MAN_TRIG,
103 	PWRAP_STAUPD_STA,
104 	PWRAP_WRAP_STA,
105 	PWRAP_HARB_INIT,
106 	PWRAP_HARB_HPRIO,
107 	PWRAP_HIPRIO_ARB_EN,
108 	PWRAP_HARB_STA0,
109 	PWRAP_HARB_STA1,
110 	PWRAP_MAN_EN,
111 	PWRAP_MAN_CMD,
112 	PWRAP_MAN_RDATA,
113 	PWRAP_MAN_VLDCLR,
114 	PWRAP_WACS0_EN,
115 	PWRAP_INIT_DONE0,
116 	PWRAP_WACS0_CMD,
117 	PWRAP_WACS0_RDATA,
118 	PWRAP_WACS0_VLDCLR,
119 	PWRAP_WACS1_EN,
120 	PWRAP_INIT_DONE1,
121 	PWRAP_WACS1_CMD,
122 	PWRAP_WACS1_RDATA,
123 	PWRAP_WACS1_VLDCLR,
124 	PWRAP_WACS2_EN,
125 	PWRAP_INIT_DONE2,
126 	PWRAP_WACS2_CMD,
127 	PWRAP_WACS2_RDATA,
128 	PWRAP_WACS2_VLDCLR,
129 	PWRAP_INT_EN,
130 	PWRAP_INT_FLG_RAW,
131 	PWRAP_INT_FLG,
132 	PWRAP_INT_CLR,
133 	PWRAP_SIG_ADR,
134 	PWRAP_SIG_MODE,
135 	PWRAP_SIG_VALUE,
136 	PWRAP_SIG_ERRVAL,
137 	PWRAP_CRC_EN,
138 	PWRAP_TIMER_EN,
139 	PWRAP_TIMER_STA,
140 	PWRAP_WDT_UNIT,
141 	PWRAP_WDT_SRC_EN,
142 	PWRAP_WDT_FLG,
143 	PWRAP_DEBUG_INT_SEL,
144 	PWRAP_CIPHER_KEY_SEL,
145 	PWRAP_CIPHER_IV_SEL,
146 	PWRAP_CIPHER_RDY,
147 	PWRAP_CIPHER_MODE,
148 	PWRAP_CIPHER_SWRST,
149 	PWRAP_DCM_EN,
150 	PWRAP_DCM_DBC_PRD,
151 
152 	/* MT8135 only regs */
153 	PWRAP_CSHEXT,
154 	PWRAP_EVENT_IN_EN,
155 	PWRAP_EVENT_DST_EN,
156 	PWRAP_RRARB_INIT,
157 	PWRAP_RRARB_EN,
158 	PWRAP_RRARB_STA0,
159 	PWRAP_RRARB_STA1,
160 	PWRAP_EVENT_STA,
161 	PWRAP_EVENT_STACLR,
162 	PWRAP_CIPHER_LOAD,
163 	PWRAP_CIPHER_START,
164 
165 	/* MT8173 only regs */
166 	PWRAP_RDDMY,
167 	PWRAP_SI_CK_CON,
168 	PWRAP_DVFS_ADR0,
169 	PWRAP_DVFS_WDATA0,
170 	PWRAP_DVFS_ADR1,
171 	PWRAP_DVFS_WDATA1,
172 	PWRAP_DVFS_ADR2,
173 	PWRAP_DVFS_WDATA2,
174 	PWRAP_DVFS_ADR3,
175 	PWRAP_DVFS_WDATA3,
176 	PWRAP_DVFS_ADR4,
177 	PWRAP_DVFS_WDATA4,
178 	PWRAP_DVFS_ADR5,
179 	PWRAP_DVFS_WDATA5,
180 	PWRAP_DVFS_ADR6,
181 	PWRAP_DVFS_WDATA6,
182 	PWRAP_DVFS_ADR7,
183 	PWRAP_DVFS_WDATA7,
184 	PWRAP_SPMINF_STA,
185 	PWRAP_CIPHER_EN,
186 };
187 
188 static int mt8173_regs[] = {
189 	[PWRAP_MUX_SEL] =		0x0,
190 	[PWRAP_WRAP_EN] =		0x4,
191 	[PWRAP_DIO_EN] =		0x8,
192 	[PWRAP_SIDLY] =			0xc,
193 	[PWRAP_RDDMY] =			0x10,
194 	[PWRAP_SI_CK_CON] =		0x14,
195 	[PWRAP_CSHEXT_WRITE] =		0x18,
196 	[PWRAP_CSHEXT_READ] =		0x1c,
197 	[PWRAP_CSLEXT_START] =		0x20,
198 	[PWRAP_CSLEXT_END] =		0x24,
199 	[PWRAP_STAUPD_PRD] =		0x28,
200 	[PWRAP_STAUPD_GRPEN] =		0x2c,
201 	[PWRAP_STAUPD_MAN_TRIG] =	0x40,
202 	[PWRAP_STAUPD_STA] =		0x44,
203 	[PWRAP_WRAP_STA] =		0x48,
204 	[PWRAP_HARB_INIT] =		0x4c,
205 	[PWRAP_HARB_HPRIO] =		0x50,
206 	[PWRAP_HIPRIO_ARB_EN] =		0x54,
207 	[PWRAP_HARB_STA0] =		0x58,
208 	[PWRAP_HARB_STA1] =		0x5c,
209 	[PWRAP_MAN_EN] =		0x60,
210 	[PWRAP_MAN_CMD] =		0x64,
211 	[PWRAP_MAN_RDATA] =		0x68,
212 	[PWRAP_MAN_VLDCLR] =		0x6c,
213 	[PWRAP_WACS0_EN] =		0x70,
214 	[PWRAP_INIT_DONE0] =		0x74,
215 	[PWRAP_WACS0_CMD] =		0x78,
216 	[PWRAP_WACS0_RDATA] =		0x7c,
217 	[PWRAP_WACS0_VLDCLR] =		0x80,
218 	[PWRAP_WACS1_EN] =		0x84,
219 	[PWRAP_INIT_DONE1] =		0x88,
220 	[PWRAP_WACS1_CMD] =		0x8c,
221 	[PWRAP_WACS1_RDATA] =		0x90,
222 	[PWRAP_WACS1_VLDCLR] =		0x94,
223 	[PWRAP_WACS2_EN] =		0x98,
224 	[PWRAP_INIT_DONE2] =		0x9c,
225 	[PWRAP_WACS2_CMD] =		0xa0,
226 	[PWRAP_WACS2_RDATA] =		0xa4,
227 	[PWRAP_WACS2_VLDCLR] =		0xa8,
228 	[PWRAP_INT_EN] =		0xac,
229 	[PWRAP_INT_FLG_RAW] =		0xb0,
230 	[PWRAP_INT_FLG] =		0xb4,
231 	[PWRAP_INT_CLR] =		0xb8,
232 	[PWRAP_SIG_ADR] =		0xbc,
233 	[PWRAP_SIG_MODE] =		0xc0,
234 	[PWRAP_SIG_VALUE] =		0xc4,
235 	[PWRAP_SIG_ERRVAL] =		0xc8,
236 	[PWRAP_CRC_EN] =		0xcc,
237 	[PWRAP_TIMER_EN] =		0xd0,
238 	[PWRAP_TIMER_STA] =		0xd4,
239 	[PWRAP_WDT_UNIT] =		0xd8,
240 	[PWRAP_WDT_SRC_EN] =		0xdc,
241 	[PWRAP_WDT_FLG] =		0xe0,
242 	[PWRAP_DEBUG_INT_SEL] =		0xe4,
243 	[PWRAP_DVFS_ADR0] =		0xe8,
244 	[PWRAP_DVFS_WDATA0] =		0xec,
245 	[PWRAP_DVFS_ADR1] =		0xf0,
246 	[PWRAP_DVFS_WDATA1] =		0xf4,
247 	[PWRAP_DVFS_ADR2] =		0xf8,
248 	[PWRAP_DVFS_WDATA2] =		0xfc,
249 	[PWRAP_DVFS_ADR3] =		0x100,
250 	[PWRAP_DVFS_WDATA3] =		0x104,
251 	[PWRAP_DVFS_ADR4] =		0x108,
252 	[PWRAP_DVFS_WDATA4] =		0x10c,
253 	[PWRAP_DVFS_ADR5] =		0x110,
254 	[PWRAP_DVFS_WDATA5] =		0x114,
255 	[PWRAP_DVFS_ADR6] =		0x118,
256 	[PWRAP_DVFS_WDATA6] =		0x11c,
257 	[PWRAP_DVFS_ADR7] =		0x120,
258 	[PWRAP_DVFS_WDATA7] =		0x124,
259 	[PWRAP_SPMINF_STA] =		0x128,
260 	[PWRAP_CIPHER_KEY_SEL] =	0x12c,
261 	[PWRAP_CIPHER_IV_SEL] =		0x130,
262 	[PWRAP_CIPHER_EN] =		0x134,
263 	[PWRAP_CIPHER_RDY] =		0x138,
264 	[PWRAP_CIPHER_MODE] =		0x13c,
265 	[PWRAP_CIPHER_SWRST] =		0x140,
266 	[PWRAP_DCM_EN] =		0x144,
267 	[PWRAP_DCM_DBC_PRD] =		0x148,
268 };
269 
270 static int mt8135_regs[] = {
271 	[PWRAP_MUX_SEL] =		0x0,
272 	[PWRAP_WRAP_EN] =		0x4,
273 	[PWRAP_DIO_EN] =		0x8,
274 	[PWRAP_SIDLY] =			0xc,
275 	[PWRAP_CSHEXT] =		0x10,
276 	[PWRAP_CSHEXT_WRITE] =		0x14,
277 	[PWRAP_CSHEXT_READ] =		0x18,
278 	[PWRAP_CSLEXT_START] =		0x1c,
279 	[PWRAP_CSLEXT_END] =		0x20,
280 	[PWRAP_STAUPD_PRD] =		0x24,
281 	[PWRAP_STAUPD_GRPEN] =		0x28,
282 	[PWRAP_STAUPD_MAN_TRIG] =	0x2c,
283 	[PWRAP_STAUPD_STA] =		0x30,
284 	[PWRAP_EVENT_IN_EN] =		0x34,
285 	[PWRAP_EVENT_DST_EN] =		0x38,
286 	[PWRAP_WRAP_STA] =		0x3c,
287 	[PWRAP_RRARB_INIT] =		0x40,
288 	[PWRAP_RRARB_EN] =		0x44,
289 	[PWRAP_RRARB_STA0] =		0x48,
290 	[PWRAP_RRARB_STA1] =		0x4c,
291 	[PWRAP_HARB_INIT] =		0x50,
292 	[PWRAP_HARB_HPRIO] =		0x54,
293 	[PWRAP_HIPRIO_ARB_EN] =		0x58,
294 	[PWRAP_HARB_STA0] =		0x5c,
295 	[PWRAP_HARB_STA1] =		0x60,
296 	[PWRAP_MAN_EN] =		0x64,
297 	[PWRAP_MAN_CMD] =		0x68,
298 	[PWRAP_MAN_RDATA] =		0x6c,
299 	[PWRAP_MAN_VLDCLR] =		0x70,
300 	[PWRAP_WACS0_EN] =		0x74,
301 	[PWRAP_INIT_DONE0] =		0x78,
302 	[PWRAP_WACS0_CMD] =		0x7c,
303 	[PWRAP_WACS0_RDATA] =		0x80,
304 	[PWRAP_WACS0_VLDCLR] =		0x84,
305 	[PWRAP_WACS1_EN] =		0x88,
306 	[PWRAP_INIT_DONE1] =		0x8c,
307 	[PWRAP_WACS1_CMD] =		0x90,
308 	[PWRAP_WACS1_RDATA] =		0x94,
309 	[PWRAP_WACS1_VLDCLR] =		0x98,
310 	[PWRAP_WACS2_EN] =		0x9c,
311 	[PWRAP_INIT_DONE2] =		0xa0,
312 	[PWRAP_WACS2_CMD] =		0xa4,
313 	[PWRAP_WACS2_RDATA] =		0xa8,
314 	[PWRAP_WACS2_VLDCLR] =		0xac,
315 	[PWRAP_INT_EN] =		0xb0,
316 	[PWRAP_INT_FLG_RAW] =		0xb4,
317 	[PWRAP_INT_FLG] =		0xb8,
318 	[PWRAP_INT_CLR] =		0xbc,
319 	[PWRAP_SIG_ADR] =		0xc0,
320 	[PWRAP_SIG_MODE] =		0xc4,
321 	[PWRAP_SIG_VALUE] =		0xc8,
322 	[PWRAP_SIG_ERRVAL] =		0xcc,
323 	[PWRAP_CRC_EN] =		0xd0,
324 	[PWRAP_EVENT_STA] =		0xd4,
325 	[PWRAP_EVENT_STACLR] =		0xd8,
326 	[PWRAP_TIMER_EN] =		0xdc,
327 	[PWRAP_TIMER_STA] =		0xe0,
328 	[PWRAP_WDT_UNIT] =		0xe4,
329 	[PWRAP_WDT_SRC_EN] =		0xe8,
330 	[PWRAP_WDT_FLG] =		0xec,
331 	[PWRAP_DEBUG_INT_SEL] =		0xf0,
332 	[PWRAP_CIPHER_KEY_SEL] =	0x134,
333 	[PWRAP_CIPHER_IV_SEL] =		0x138,
334 	[PWRAP_CIPHER_LOAD] =		0x13c,
335 	[PWRAP_CIPHER_START] =		0x140,
336 	[PWRAP_CIPHER_RDY] =		0x144,
337 	[PWRAP_CIPHER_MODE] =		0x148,
338 	[PWRAP_CIPHER_SWRST] =		0x14c,
339 	[PWRAP_DCM_EN] =		0x15c,
340 	[PWRAP_DCM_DBC_PRD] =		0x160,
341 };
342 
343 enum pwrap_type {
344 	PWRAP_MT8135,
345 	PWRAP_MT8173,
346 };
347 
348 struct pmic_wrapper_type {
349 	int *regs;
350 	enum pwrap_type type;
351 	u32 arb_en_all;
352 };
353 
354 static struct pmic_wrapper_type pwrap_mt8135 = {
355 	.regs = mt8135_regs,
356 	.type = PWRAP_MT8135,
357 	.arb_en_all = 0x1ff,
358 };
359 
360 static struct pmic_wrapper_type pwrap_mt8173 = {
361 	.regs = mt8173_regs,
362 	.type = PWRAP_MT8173,
363 	.arb_en_all = 0x3f,
364 };
365 
366 struct pmic_wrapper {
367 	struct device *dev;
368 	void __iomem *base;
369 	struct regmap *regmap;
370 	int *regs;
371 	enum pwrap_type type;
372 	u32 arb_en_all;
373 	struct clk *clk_spi;
374 	struct clk *clk_wrap;
375 	struct reset_control *rstc;
376 
377 	struct reset_control *rstc_bridge;
378 	void __iomem *bridge_base;
379 };
380 
381 static inline int pwrap_is_mt8135(struct pmic_wrapper *wrp)
382 {
383 	return wrp->type == PWRAP_MT8135;
384 }
385 
386 static inline int pwrap_is_mt8173(struct pmic_wrapper *wrp)
387 {
388 	return wrp->type == PWRAP_MT8173;
389 }
390 
391 static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
392 {
393 	return readl(wrp->base + wrp->regs[reg]);
394 }
395 
396 static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
397 {
398 	writel(val, wrp->base + wrp->regs[reg]);
399 }
400 
401 static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
402 {
403 	u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
404 
405 	return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE;
406 }
407 
408 static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
409 {
410 	u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
411 
412 	return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
413 }
414 
415 static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
416 {
417 	return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
418 }
419 
420 static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
421 {
422 	u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
423 
424 	return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&
425 		(val & PWRAP_STATE_SYNC_IDLE0);
426 }
427 
428 static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
429 		bool (*fp)(struct pmic_wrapper *))
430 {
431 	unsigned long timeout;
432 
433 	timeout = jiffies + usecs_to_jiffies(255);
434 
435 	do {
436 		if (time_after(jiffies, timeout))
437 			return fp(wrp) ? 0 : -ETIMEDOUT;
438 		if (fp(wrp))
439 			return 0;
440 	} while (1);
441 }
442 
443 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
444 {
445 	int ret;
446 
447 	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
448 	if (ret)
449 		return ret;
450 
451 	pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
452 			PWRAP_WACS2_CMD);
453 
454 	return 0;
455 }
456 
457 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
458 {
459 	int ret;
460 
461 	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
462 	if (ret)
463 		return ret;
464 
465 	pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
466 
467 	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
468 	if (ret)
469 		return ret;
470 
471 	*rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
472 
473 	pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
474 
475 	return 0;
476 }
477 
478 static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
479 {
480 	return pwrap_read(context, adr, rdata);
481 }
482 
483 static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
484 {
485 	return pwrap_write(context, adr, wdata);
486 }
487 
488 static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
489 {
490 	int ret, i;
491 
492 	pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
493 	pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
494 	pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
495 	pwrap_writel(wrp, 1, PWRAP_MAN_EN);
496 	pwrap_writel(wrp, 0, PWRAP_DIO_EN);
497 
498 	pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_CSL,
499 			PWRAP_MAN_CMD);
500 	pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_OUTS,
501 			PWRAP_MAN_CMD);
502 	pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_CSH,
503 			PWRAP_MAN_CMD);
504 
505 	for (i = 0; i < 4; i++)
506 		pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_OUTS,
507 				PWRAP_MAN_CMD);
508 
509 	ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
510 	if (ret) {
511 		dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
512 		return ret;
513 	}
514 
515 	pwrap_writel(wrp, 0, PWRAP_MAN_EN);
516 	pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
517 
518 	return 0;
519 }
520 
521 /*
522  * pwrap_init_sidly - configure serial input delay
523  *
524  * This configures the serial input delay. We can configure 0, 2, 4 or 6ns
525  * delay. Do a read test with all possible values and chose the best delay.
526  */
527 static int pwrap_init_sidly(struct pmic_wrapper *wrp)
528 {
529 	u32 rdata;
530 	u32 i;
531 	u32 pass = 0;
532 	signed char dly[16] = {
533 		-1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
534 	};
535 
536 	for (i = 0; i < 4; i++) {
537 		pwrap_writel(wrp, i, PWRAP_SIDLY);
538 		pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
539 		if (rdata == PWRAP_DEW_READ_TEST_VAL) {
540 			dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
541 			pass |= 1 << i;
542 		}
543 	}
544 
545 	if (dly[pass] < 0) {
546 		dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
547 				pass);
548 		return -EIO;
549 	}
550 
551 	pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
552 
553 	return 0;
554 }
555 
556 static int pwrap_init_reg_clock(struct pmic_wrapper *wrp)
557 {
558 	if (pwrap_is_mt8135(wrp)) {
559 		pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
560 		pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
561 		pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
562 		pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
563 		pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
564 	} else {
565 		pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
566 		pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
567 		pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
568 		pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
569 	}
570 
571 	return 0;
572 }
573 
574 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
575 {
576 	return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
577 }
578 
579 static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
580 {
581 	u32 rdata;
582 	int ret;
583 
584 	ret = pwrap_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
585 	if (ret)
586 		return 0;
587 
588 	return rdata == 1;
589 }
590 
591 static int pwrap_init_cipher(struct pmic_wrapper *wrp)
592 {
593 	int ret;
594 	u32 rdata;
595 
596 	pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
597 	pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
598 	pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
599 	pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
600 
601 	if (pwrap_is_mt8135(wrp)) {
602 		pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
603 		pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
604 	} else {
605 		pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
606 	}
607 
608 	/* Config cipher mode @PMIC */
609 	pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
610 	pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
611 	pwrap_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
612 	pwrap_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
613 	pwrap_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
614 	pwrap_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
615 
616 	/* wait for cipher data ready@AP */
617 	ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
618 	if (ret) {
619 		dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
620 		return ret;
621 	}
622 
623 	/* wait for cipher data ready@PMIC */
624 	ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
625 	if (ret) {
626 		dev_err(wrp->dev, "timeout waiting for cipher data ready@PMIC\n");
627 		return ret;
628 	}
629 
630 	/* wait for cipher mode idle */
631 	pwrap_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
632 	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
633 	if (ret) {
634 		dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
635 		return ret;
636 	}
637 
638 	pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
639 
640 	/* Write Test */
641 	if (pwrap_write(wrp, PWRAP_DEW_WRITE_TEST, PWRAP_DEW_WRITE_TEST_VAL) ||
642 	    pwrap_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
643 			(rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
644 		dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
645 		return -EFAULT;
646 	}
647 
648 	return 0;
649 }
650 
651 static int pwrap_init(struct pmic_wrapper *wrp)
652 {
653 	int ret;
654 	u32 rdata;
655 
656 	reset_control_reset(wrp->rstc);
657 	if (wrp->rstc_bridge)
658 		reset_control_reset(wrp->rstc_bridge);
659 
660 	if (pwrap_is_mt8173(wrp)) {
661 		/* Enable DCM */
662 		pwrap_writel(wrp, 3, PWRAP_DCM_EN);
663 		pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
664 	}
665 
666 	/* Reset SPI slave */
667 	ret = pwrap_reset_spislave(wrp);
668 	if (ret)
669 		return ret;
670 
671 	pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
672 
673 	pwrap_writel(wrp, wrp->arb_en_all, PWRAP_HIPRIO_ARB_EN);
674 
675 	pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
676 
677 	ret = pwrap_init_reg_clock(wrp);
678 	if (ret)
679 		return ret;
680 
681 	/* Setup serial input delay */
682 	ret = pwrap_init_sidly(wrp);
683 	if (ret)
684 		return ret;
685 
686 	/* Enable dual IO mode */
687 	pwrap_write(wrp, PWRAP_DEW_DIO_EN, 1);
688 
689 	/* Check IDLE & INIT_DONE in advance */
690 	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
691 	if (ret) {
692 		dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
693 		return ret;
694 	}
695 
696 	pwrap_writel(wrp, 1, PWRAP_DIO_EN);
697 
698 	/* Read Test */
699 	pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
700 	if (rdata != PWRAP_DEW_READ_TEST_VAL) {
701 		dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
702 				PWRAP_DEW_READ_TEST_VAL, rdata);
703 		return -EFAULT;
704 	}
705 
706 	/* Enable encryption */
707 	ret = pwrap_init_cipher(wrp);
708 	if (ret)
709 		return ret;
710 
711 	/* Signature checking - using CRC */
712 	if (pwrap_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
713 		return -EFAULT;
714 
715 	pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
716 	pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
717 	pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
718 	pwrap_writel(wrp, wrp->arb_en_all, PWRAP_HIPRIO_ARB_EN);
719 
720 	if (pwrap_is_mt8135(wrp))
721 		pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
722 
723 	pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
724 	pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
725 	pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
726 	pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
727 	pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
728 
729 	if (pwrap_is_mt8135(wrp)) {
730 		/* enable pwrap events and pwrap bridge in AP side */
731 		pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
732 		pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
733 		writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
734 		writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
735 		writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
736 		writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
737 		writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
738 		writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
739 		writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
740 
741 		/* enable PMIC event out and sources */
742 		if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
743 				pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
744 			dev_err(wrp->dev, "enable dewrap fail\n");
745 			return -EFAULT;
746 		}
747 	} else {
748 		/* PMIC_DEWRAP enables */
749 		if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
750 				pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
751 			dev_err(wrp->dev, "enable dewrap fail\n");
752 			return -EFAULT;
753 		}
754 	}
755 
756 	/* Setup the init done registers */
757 	pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
758 	pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
759 	pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
760 
761 	if (pwrap_is_mt8135(wrp)) {
762 		writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
763 		writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
764 	}
765 
766 	return 0;
767 }
768 
769 static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
770 {
771 	u32 rdata;
772 	struct pmic_wrapper *wrp = dev_id;
773 
774 	rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
775 
776 	dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
777 
778 	pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
779 
780 	return IRQ_HANDLED;
781 }
782 
783 static const struct regmap_config pwrap_regmap_config = {
784 	.reg_bits = 16,
785 	.val_bits = 16,
786 	.reg_stride = 2,
787 	.reg_read = pwrap_regmap_read,
788 	.reg_write = pwrap_regmap_write,
789 	.max_register = 0xffff,
790 };
791 
792 static struct of_device_id of_pwrap_match_tbl[] = {
793 	{
794 		.compatible = "mediatek,mt8135-pwrap",
795 		.data = &pwrap_mt8135,
796 	}, {
797 		.compatible = "mediatek,mt8173-pwrap",
798 		.data = &pwrap_mt8173,
799 	}, {
800 		/* sentinel */
801 	}
802 };
803 MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
804 
805 static int pwrap_probe(struct platform_device *pdev)
806 {
807 	int ret, irq;
808 	struct pmic_wrapper *wrp;
809 	struct device_node *np = pdev->dev.of_node;
810 	const struct of_device_id *of_id =
811 		of_match_device(of_pwrap_match_tbl, &pdev->dev);
812 	const struct pmic_wrapper_type *type;
813 	struct resource *res;
814 
815 	wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
816 	if (!wrp)
817 		return -ENOMEM;
818 
819 	platform_set_drvdata(pdev, wrp);
820 
821 	type = of_id->data;
822 	wrp->regs = type->regs;
823 	wrp->type = type->type;
824 	wrp->arb_en_all = type->arb_en_all;
825 	wrp->dev = &pdev->dev;
826 
827 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
828 	wrp->base = devm_ioremap_resource(wrp->dev, res);
829 	if (IS_ERR(wrp->base))
830 		return PTR_ERR(wrp->base);
831 
832 	wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
833 	if (IS_ERR(wrp->rstc)) {
834 		ret = PTR_ERR(wrp->rstc);
835 		dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
836 		return ret;
837 	}
838 
839 	if (pwrap_is_mt8135(wrp)) {
840 		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
841 				"pwrap-bridge");
842 		wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
843 		if (IS_ERR(wrp->bridge_base))
844 			return PTR_ERR(wrp->bridge_base);
845 
846 		wrp->rstc_bridge = devm_reset_control_get(wrp->dev, "pwrap-bridge");
847 		if (IS_ERR(wrp->rstc_bridge)) {
848 			ret = PTR_ERR(wrp->rstc_bridge);
849 			dev_dbg(wrp->dev, "cannot get pwrap-bridge reset: %d\n", ret);
850 			return ret;
851 		}
852 	}
853 
854 	wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
855 	if (IS_ERR(wrp->clk_spi)) {
856 		dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_spi));
857 		return PTR_ERR(wrp->clk_spi);
858 	}
859 
860 	wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
861 	if (IS_ERR(wrp->clk_wrap)) {
862 		dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_wrap));
863 		return PTR_ERR(wrp->clk_wrap);
864 	}
865 
866 	ret = clk_prepare_enable(wrp->clk_spi);
867 	if (ret)
868 		return ret;
869 
870 	ret = clk_prepare_enable(wrp->clk_wrap);
871 	if (ret)
872 		goto err_out1;
873 
874 	/* Enable internal dynamic clock */
875 	pwrap_writel(wrp, 1, PWRAP_DCM_EN);
876 	pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
877 
878 	/*
879 	 * The PMIC could already be initialized by the bootloader.
880 	 * Skip initialization here in this case.
881 	 */
882 	if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
883 		ret = pwrap_init(wrp);
884 		if (ret) {
885 			dev_dbg(wrp->dev, "init failed with %d\n", ret);
886 			goto err_out2;
887 		}
888 	}
889 
890 	if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) {
891 		dev_dbg(wrp->dev, "initialization isn't finished\n");
892 		return -ENODEV;
893 	}
894 
895 	/* Initialize watchdog, may not be done by the bootloader */
896 	pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
897 	pwrap_writel(wrp, 0xffffffff, PWRAP_WDT_SRC_EN);
898 	pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
899 	pwrap_writel(wrp, ~((1 << 31) | (1 << 1)), PWRAP_INT_EN);
900 
901 	irq = platform_get_irq(pdev, 0);
902 	ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, IRQF_TRIGGER_HIGH,
903 			"mt-pmic-pwrap", wrp);
904 	if (ret)
905 		goto err_out2;
906 
907 	wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, &pwrap_regmap_config);
908 	if (IS_ERR(wrp->regmap))
909 		return PTR_ERR(wrp->regmap);
910 
911 	ret = of_platform_populate(np, NULL, NULL, wrp->dev);
912 	if (ret) {
913 		dev_dbg(wrp->dev, "failed to create child devices at %s\n",
914 				np->full_name);
915 		goto err_out2;
916 	}
917 
918 	return 0;
919 
920 err_out2:
921 	clk_disable_unprepare(wrp->clk_wrap);
922 err_out1:
923 	clk_disable_unprepare(wrp->clk_spi);
924 
925 	return ret;
926 }
927 
928 static struct platform_driver pwrap_drv = {
929 	.driver = {
930 		.name = "mt-pmic-pwrap",
931 		.of_match_table = of_match_ptr(of_pwrap_match_tbl),
932 	},
933 	.probe = pwrap_probe,
934 };
935 
936 module_platform_driver(pwrap_drv);
937 
938 MODULE_AUTHOR("Flora Fu, MediaTek");
939 MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");
940 MODULE_LICENSE("GPL v2");
941