1 /* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Flora Fu, MediaTek 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 #include <linux/clk.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 #include <linux/reset.h> 23 24 #define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4 25 #define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10 26 #define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14 27 #define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24 28 #define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28 29 #define PWRAP_MT8135_BRIDGE_INT_EN 0x38 30 #define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48 31 #define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50 32 #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54 33 34 /* macro for wrapper status */ 35 #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff) 36 #define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007) 37 #define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001) 38 #define PWRAP_STATE_SYNC_IDLE0 (1 << 20) 39 #define PWRAP_STATE_INIT_DONE0 (1 << 21) 40 41 /* macro for WACS FSM */ 42 #define PWRAP_WACS_FSM_IDLE 0x00 43 #define PWRAP_WACS_FSM_REQ 0x02 44 #define PWRAP_WACS_FSM_WFDLE 0x04 45 #define PWRAP_WACS_FSM_WFVLDCLR 0x06 46 #define PWRAP_WACS_INIT_DONE 0x01 47 #define PWRAP_WACS_WACS_SYNC_IDLE 0x01 48 #define PWRAP_WACS_SYNC_BUSY 0x00 49 50 /* macro for device wrapper default value */ 51 #define PWRAP_DEW_READ_TEST_VAL 0x5aa5 52 #define PWRAP_DEW_WRITE_TEST_VAL 0xa55a 53 54 /* macro for manual command */ 55 #define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14) 56 #define PWRAP_MAN_CMD_SPI_WRITE (1 << 13) 57 #define PWRAP_MAN_CMD_OP_CSH (0x0 << 8) 58 #define PWRAP_MAN_CMD_OP_CSL (0x1 << 8) 59 #define PWRAP_MAN_CMD_OP_CK (0x2 << 8) 60 #define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8) 61 #define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8) 62 #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8) 63 64 /* macro for Watch Dog Timer Source */ 65 #define PWRAP_WDT_SRC_EN_STAUPD_TRIG (1 << 25) 66 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE (1 << 20) 67 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE (1 << 6) 68 #define PWRAP_WDT_SRC_MASK_ALL 0xffffffff 69 #define PWRAP_WDT_SRC_MASK_NO_STAUPD ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \ 70 PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \ 71 PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE) 72 73 /* Group of bits used for shown slave capability */ 74 #define PWRAP_SLV_CAP_SPI BIT(0) 75 #define PWRAP_SLV_CAP_DUALIO BIT(1) 76 #define PWRAP_SLV_CAP_SECURITY BIT(2) 77 #define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x)) 78 79 /* Group of bits used for shown pwrap capability */ 80 #define PWRAP_CAP_BRIDGE BIT(0) 81 #define PWRAP_CAP_RESET BIT(1) 82 #define PWRAP_CAP_DCM BIT(2) 83 #define PWRAP_CAP_INT1_EN BIT(3) 84 #define PWRAP_CAP_WDT_SRC1 BIT(4) 85 86 /* defines for slave device wrapper registers */ 87 enum dew_regs { 88 PWRAP_DEW_BASE, 89 PWRAP_DEW_DIO_EN, 90 PWRAP_DEW_READ_TEST, 91 PWRAP_DEW_WRITE_TEST, 92 PWRAP_DEW_CRC_EN, 93 PWRAP_DEW_CRC_VAL, 94 PWRAP_DEW_MON_GRP_SEL, 95 PWRAP_DEW_CIPHER_KEY_SEL, 96 PWRAP_DEW_CIPHER_IV_SEL, 97 PWRAP_DEW_CIPHER_RDY, 98 PWRAP_DEW_CIPHER_MODE, 99 PWRAP_DEW_CIPHER_SWRST, 100 101 /* MT6323 only regs */ 102 PWRAP_DEW_CIPHER_EN, 103 PWRAP_DEW_RDDMY_NO, 104 105 /* MT6358 only regs */ 106 PWRAP_SMT_CON1, 107 PWRAP_DRV_CON1, 108 PWRAP_FILTER_CON0, 109 PWRAP_GPIO_PULLEN0_CLR, 110 PWRAP_RG_SPI_CON0, 111 PWRAP_RG_SPI_RECORD0, 112 PWRAP_RG_SPI_CON2, 113 PWRAP_RG_SPI_CON3, 114 PWRAP_RG_SPI_CON4, 115 PWRAP_RG_SPI_CON5, 116 PWRAP_RG_SPI_CON6, 117 PWRAP_RG_SPI_CON7, 118 PWRAP_RG_SPI_CON8, 119 PWRAP_RG_SPI_CON13, 120 PWRAP_SPISLV_KEY, 121 122 /* MT6397 only regs */ 123 PWRAP_DEW_EVENT_OUT_EN, 124 PWRAP_DEW_EVENT_SRC_EN, 125 PWRAP_DEW_EVENT_SRC, 126 PWRAP_DEW_EVENT_FLAG, 127 PWRAP_DEW_MON_FLAG_SEL, 128 PWRAP_DEW_EVENT_TEST, 129 PWRAP_DEW_CIPHER_LOAD, 130 PWRAP_DEW_CIPHER_START, 131 }; 132 133 static const u32 mt6323_regs[] = { 134 [PWRAP_DEW_BASE] = 0x0000, 135 [PWRAP_DEW_DIO_EN] = 0x018a, 136 [PWRAP_DEW_READ_TEST] = 0x018c, 137 [PWRAP_DEW_WRITE_TEST] = 0x018e, 138 [PWRAP_DEW_CRC_EN] = 0x0192, 139 [PWRAP_DEW_CRC_VAL] = 0x0194, 140 [PWRAP_DEW_MON_GRP_SEL] = 0x0196, 141 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0198, 142 [PWRAP_DEW_CIPHER_IV_SEL] = 0x019a, 143 [PWRAP_DEW_CIPHER_EN] = 0x019c, 144 [PWRAP_DEW_CIPHER_RDY] = 0x019e, 145 [PWRAP_DEW_CIPHER_MODE] = 0x01a0, 146 [PWRAP_DEW_CIPHER_SWRST] = 0x01a2, 147 [PWRAP_DEW_RDDMY_NO] = 0x01a4, 148 }; 149 150 static const u32 mt6351_regs[] = { 151 [PWRAP_DEW_DIO_EN] = 0x02F2, 152 [PWRAP_DEW_READ_TEST] = 0x02F4, 153 [PWRAP_DEW_WRITE_TEST] = 0x02F6, 154 [PWRAP_DEW_CRC_EN] = 0x02FA, 155 [PWRAP_DEW_CRC_VAL] = 0x02FC, 156 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0300, 157 [PWRAP_DEW_CIPHER_IV_SEL] = 0x0302, 158 [PWRAP_DEW_CIPHER_EN] = 0x0304, 159 [PWRAP_DEW_CIPHER_RDY] = 0x0306, 160 [PWRAP_DEW_CIPHER_MODE] = 0x0308, 161 [PWRAP_DEW_CIPHER_SWRST] = 0x030A, 162 [PWRAP_DEW_RDDMY_NO] = 0x030C, 163 }; 164 165 static const u32 mt6357_regs[] = { 166 [PWRAP_DEW_DIO_EN] = 0x040A, 167 [PWRAP_DEW_READ_TEST] = 0x040C, 168 [PWRAP_DEW_WRITE_TEST] = 0x040E, 169 [PWRAP_DEW_CRC_EN] = 0x0412, 170 [PWRAP_DEW_CRC_VAL] = 0x0414, 171 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418, 172 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041A, 173 [PWRAP_DEW_CIPHER_EN] = 0x041C, 174 [PWRAP_DEW_CIPHER_RDY] = 0x041E, 175 [PWRAP_DEW_CIPHER_MODE] = 0x0420, 176 [PWRAP_DEW_CIPHER_SWRST] = 0x0422, 177 [PWRAP_DEW_RDDMY_NO] = 0x0424, 178 }; 179 180 static const u32 mt6358_regs[] = { 181 [PWRAP_SMT_CON1] = 0x0030, 182 [PWRAP_DRV_CON1] = 0x0038, 183 [PWRAP_FILTER_CON0] = 0x0040, 184 [PWRAP_GPIO_PULLEN0_CLR] = 0x0098, 185 [PWRAP_RG_SPI_CON0] = 0x0408, 186 [PWRAP_RG_SPI_RECORD0] = 0x040a, 187 [PWRAP_DEW_DIO_EN] = 0x040c, 188 [PWRAP_DEW_READ_TEST] = 0x040e, 189 [PWRAP_DEW_WRITE_TEST] = 0x0410, 190 [PWRAP_DEW_CRC_EN] = 0x0414, 191 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x041a, 192 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041c, 193 [PWRAP_DEW_CIPHER_EN] = 0x041e, 194 [PWRAP_DEW_CIPHER_RDY] = 0x0420, 195 [PWRAP_DEW_CIPHER_MODE] = 0x0422, 196 [PWRAP_DEW_CIPHER_SWRST] = 0x0424, 197 [PWRAP_RG_SPI_CON2] = 0x0432, 198 [PWRAP_RG_SPI_CON3] = 0x0434, 199 [PWRAP_RG_SPI_CON4] = 0x0436, 200 [PWRAP_RG_SPI_CON5] = 0x0438, 201 [PWRAP_RG_SPI_CON6] = 0x043a, 202 [PWRAP_RG_SPI_CON7] = 0x043c, 203 [PWRAP_RG_SPI_CON8] = 0x043e, 204 [PWRAP_RG_SPI_CON13] = 0x0448, 205 [PWRAP_SPISLV_KEY] = 0x044a, 206 }; 207 208 static const u32 mt6397_regs[] = { 209 [PWRAP_DEW_BASE] = 0xbc00, 210 [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00, 211 [PWRAP_DEW_DIO_EN] = 0xbc02, 212 [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04, 213 [PWRAP_DEW_EVENT_SRC] = 0xbc06, 214 [PWRAP_DEW_EVENT_FLAG] = 0xbc08, 215 [PWRAP_DEW_READ_TEST] = 0xbc0a, 216 [PWRAP_DEW_WRITE_TEST] = 0xbc0c, 217 [PWRAP_DEW_CRC_EN] = 0xbc0e, 218 [PWRAP_DEW_CRC_VAL] = 0xbc10, 219 [PWRAP_DEW_MON_GRP_SEL] = 0xbc12, 220 [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14, 221 [PWRAP_DEW_EVENT_TEST] = 0xbc16, 222 [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18, 223 [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a, 224 [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c, 225 [PWRAP_DEW_CIPHER_START] = 0xbc1e, 226 [PWRAP_DEW_CIPHER_RDY] = 0xbc20, 227 [PWRAP_DEW_CIPHER_MODE] = 0xbc22, 228 [PWRAP_DEW_CIPHER_SWRST] = 0xbc24, 229 }; 230 231 enum pwrap_regs { 232 PWRAP_MUX_SEL, 233 PWRAP_WRAP_EN, 234 PWRAP_DIO_EN, 235 PWRAP_SIDLY, 236 PWRAP_CSHEXT_WRITE, 237 PWRAP_CSHEXT_READ, 238 PWRAP_CSLEXT_START, 239 PWRAP_CSLEXT_END, 240 PWRAP_STAUPD_PRD, 241 PWRAP_STAUPD_GRPEN, 242 PWRAP_STAUPD_MAN_TRIG, 243 PWRAP_STAUPD_STA, 244 PWRAP_WRAP_STA, 245 PWRAP_HARB_INIT, 246 PWRAP_HARB_HPRIO, 247 PWRAP_HIPRIO_ARB_EN, 248 PWRAP_HARB_STA0, 249 PWRAP_HARB_STA1, 250 PWRAP_MAN_EN, 251 PWRAP_MAN_CMD, 252 PWRAP_MAN_RDATA, 253 PWRAP_MAN_VLDCLR, 254 PWRAP_WACS0_EN, 255 PWRAP_INIT_DONE0, 256 PWRAP_WACS0_CMD, 257 PWRAP_WACS0_RDATA, 258 PWRAP_WACS0_VLDCLR, 259 PWRAP_WACS1_EN, 260 PWRAP_INIT_DONE1, 261 PWRAP_WACS1_CMD, 262 PWRAP_WACS1_RDATA, 263 PWRAP_WACS1_VLDCLR, 264 PWRAP_WACS2_EN, 265 PWRAP_INIT_DONE2, 266 PWRAP_WACS2_CMD, 267 PWRAP_WACS2_RDATA, 268 PWRAP_WACS2_VLDCLR, 269 PWRAP_INT_EN, 270 PWRAP_INT_FLG_RAW, 271 PWRAP_INT_FLG, 272 PWRAP_INT_CLR, 273 PWRAP_SIG_ADR, 274 PWRAP_SIG_MODE, 275 PWRAP_SIG_VALUE, 276 PWRAP_SIG_ERRVAL, 277 PWRAP_CRC_EN, 278 PWRAP_TIMER_EN, 279 PWRAP_TIMER_STA, 280 PWRAP_WDT_UNIT, 281 PWRAP_WDT_SRC_EN, 282 PWRAP_WDT_FLG, 283 PWRAP_DEBUG_INT_SEL, 284 PWRAP_CIPHER_KEY_SEL, 285 PWRAP_CIPHER_IV_SEL, 286 PWRAP_CIPHER_RDY, 287 PWRAP_CIPHER_MODE, 288 PWRAP_CIPHER_SWRST, 289 PWRAP_DCM_EN, 290 PWRAP_DCM_DBC_PRD, 291 PWRAP_EINT_STA0_ADR, 292 PWRAP_EINT_STA1_ADR, 293 294 /* MT2701 only regs */ 295 PWRAP_ADC_CMD_ADDR, 296 PWRAP_PWRAP_ADC_CMD, 297 PWRAP_ADC_RDY_ADDR, 298 PWRAP_ADC_RDATA_ADDR1, 299 PWRAP_ADC_RDATA_ADDR2, 300 301 /* MT7622 only regs */ 302 PWRAP_STA, 303 PWRAP_CLR, 304 PWRAP_DVFS_ADR8, 305 PWRAP_DVFS_WDATA8, 306 PWRAP_DVFS_ADR9, 307 PWRAP_DVFS_WDATA9, 308 PWRAP_DVFS_ADR10, 309 PWRAP_DVFS_WDATA10, 310 PWRAP_DVFS_ADR11, 311 PWRAP_DVFS_WDATA11, 312 PWRAP_DVFS_ADR12, 313 PWRAP_DVFS_WDATA12, 314 PWRAP_DVFS_ADR13, 315 PWRAP_DVFS_WDATA13, 316 PWRAP_DVFS_ADR14, 317 PWRAP_DVFS_WDATA14, 318 PWRAP_DVFS_ADR15, 319 PWRAP_DVFS_WDATA15, 320 PWRAP_EXT_CK, 321 PWRAP_ADC_RDATA_ADDR, 322 PWRAP_GPS_STA, 323 PWRAP_SW_RST, 324 PWRAP_DVFS_STEP_CTRL0, 325 PWRAP_DVFS_STEP_CTRL1, 326 PWRAP_DVFS_STEP_CTRL2, 327 PWRAP_SPI2_CTRL, 328 329 /* MT8135 only regs */ 330 PWRAP_CSHEXT, 331 PWRAP_EVENT_IN_EN, 332 PWRAP_EVENT_DST_EN, 333 PWRAP_RRARB_INIT, 334 PWRAP_RRARB_EN, 335 PWRAP_RRARB_STA0, 336 PWRAP_RRARB_STA1, 337 PWRAP_EVENT_STA, 338 PWRAP_EVENT_STACLR, 339 PWRAP_CIPHER_LOAD, 340 PWRAP_CIPHER_START, 341 342 /* MT8173 only regs */ 343 PWRAP_RDDMY, 344 PWRAP_SI_CK_CON, 345 PWRAP_DVFS_ADR0, 346 PWRAP_DVFS_WDATA0, 347 PWRAP_DVFS_ADR1, 348 PWRAP_DVFS_WDATA1, 349 PWRAP_DVFS_ADR2, 350 PWRAP_DVFS_WDATA2, 351 PWRAP_DVFS_ADR3, 352 PWRAP_DVFS_WDATA3, 353 PWRAP_DVFS_ADR4, 354 PWRAP_DVFS_WDATA4, 355 PWRAP_DVFS_ADR5, 356 PWRAP_DVFS_WDATA5, 357 PWRAP_DVFS_ADR6, 358 PWRAP_DVFS_WDATA6, 359 PWRAP_DVFS_ADR7, 360 PWRAP_DVFS_WDATA7, 361 PWRAP_SPMINF_STA, 362 PWRAP_CIPHER_EN, 363 364 /* MT8183 only regs */ 365 PWRAP_SI_SAMPLE_CTRL, 366 PWRAP_CSLEXT_WRITE, 367 PWRAP_CSLEXT_READ, 368 PWRAP_EXT_CK_WRITE, 369 PWRAP_STAUPD_CTRL, 370 PWRAP_WACS_P2P_EN, 371 PWRAP_INIT_DONE_P2P, 372 PWRAP_WACS_MD32_EN, 373 PWRAP_INIT_DONE_MD32, 374 PWRAP_INT1_EN, 375 PWRAP_INT1_FLG, 376 PWRAP_INT1_CLR, 377 PWRAP_WDT_SRC_EN_1, 378 PWRAP_INT_GPS_AUXADC_CMD_ADDR, 379 PWRAP_INT_GPS_AUXADC_CMD, 380 PWRAP_INT_GPS_AUXADC_RDATA_ADDR, 381 PWRAP_EXT_GPS_AUXADC_RDATA_ADDR, 382 PWRAP_GPSINF_0_STA, 383 PWRAP_GPSINF_1_STA, 384 385 /* MT8516 only regs */ 386 PWRAP_OP_TYPE, 387 PWRAP_MSB_FIRST, 388 }; 389 390 static int mt2701_regs[] = { 391 [PWRAP_MUX_SEL] = 0x0, 392 [PWRAP_WRAP_EN] = 0x4, 393 [PWRAP_DIO_EN] = 0x8, 394 [PWRAP_SIDLY] = 0xc, 395 [PWRAP_RDDMY] = 0x18, 396 [PWRAP_SI_CK_CON] = 0x1c, 397 [PWRAP_CSHEXT_WRITE] = 0x20, 398 [PWRAP_CSHEXT_READ] = 0x24, 399 [PWRAP_CSLEXT_START] = 0x28, 400 [PWRAP_CSLEXT_END] = 0x2c, 401 [PWRAP_STAUPD_PRD] = 0x30, 402 [PWRAP_STAUPD_GRPEN] = 0x34, 403 [PWRAP_STAUPD_MAN_TRIG] = 0x38, 404 [PWRAP_STAUPD_STA] = 0x3c, 405 [PWRAP_WRAP_STA] = 0x44, 406 [PWRAP_HARB_INIT] = 0x48, 407 [PWRAP_HARB_HPRIO] = 0x4c, 408 [PWRAP_HIPRIO_ARB_EN] = 0x50, 409 [PWRAP_HARB_STA0] = 0x54, 410 [PWRAP_HARB_STA1] = 0x58, 411 [PWRAP_MAN_EN] = 0x5c, 412 [PWRAP_MAN_CMD] = 0x60, 413 [PWRAP_MAN_RDATA] = 0x64, 414 [PWRAP_MAN_VLDCLR] = 0x68, 415 [PWRAP_WACS0_EN] = 0x6c, 416 [PWRAP_INIT_DONE0] = 0x70, 417 [PWRAP_WACS0_CMD] = 0x74, 418 [PWRAP_WACS0_RDATA] = 0x78, 419 [PWRAP_WACS0_VLDCLR] = 0x7c, 420 [PWRAP_WACS1_EN] = 0x80, 421 [PWRAP_INIT_DONE1] = 0x84, 422 [PWRAP_WACS1_CMD] = 0x88, 423 [PWRAP_WACS1_RDATA] = 0x8c, 424 [PWRAP_WACS1_VLDCLR] = 0x90, 425 [PWRAP_WACS2_EN] = 0x94, 426 [PWRAP_INIT_DONE2] = 0x98, 427 [PWRAP_WACS2_CMD] = 0x9c, 428 [PWRAP_WACS2_RDATA] = 0xa0, 429 [PWRAP_WACS2_VLDCLR] = 0xa4, 430 [PWRAP_INT_EN] = 0xa8, 431 [PWRAP_INT_FLG_RAW] = 0xac, 432 [PWRAP_INT_FLG] = 0xb0, 433 [PWRAP_INT_CLR] = 0xb4, 434 [PWRAP_SIG_ADR] = 0xb8, 435 [PWRAP_SIG_MODE] = 0xbc, 436 [PWRAP_SIG_VALUE] = 0xc0, 437 [PWRAP_SIG_ERRVAL] = 0xc4, 438 [PWRAP_CRC_EN] = 0xc8, 439 [PWRAP_TIMER_EN] = 0xcc, 440 [PWRAP_TIMER_STA] = 0xd0, 441 [PWRAP_WDT_UNIT] = 0xd4, 442 [PWRAP_WDT_SRC_EN] = 0xd8, 443 [PWRAP_WDT_FLG] = 0xdc, 444 [PWRAP_DEBUG_INT_SEL] = 0xe0, 445 [PWRAP_DVFS_ADR0] = 0xe4, 446 [PWRAP_DVFS_WDATA0] = 0xe8, 447 [PWRAP_DVFS_ADR1] = 0xec, 448 [PWRAP_DVFS_WDATA1] = 0xf0, 449 [PWRAP_DVFS_ADR2] = 0xf4, 450 [PWRAP_DVFS_WDATA2] = 0xf8, 451 [PWRAP_DVFS_ADR3] = 0xfc, 452 [PWRAP_DVFS_WDATA3] = 0x100, 453 [PWRAP_DVFS_ADR4] = 0x104, 454 [PWRAP_DVFS_WDATA4] = 0x108, 455 [PWRAP_DVFS_ADR5] = 0x10c, 456 [PWRAP_DVFS_WDATA5] = 0x110, 457 [PWRAP_DVFS_ADR6] = 0x114, 458 [PWRAP_DVFS_WDATA6] = 0x118, 459 [PWRAP_DVFS_ADR7] = 0x11c, 460 [PWRAP_DVFS_WDATA7] = 0x120, 461 [PWRAP_CIPHER_KEY_SEL] = 0x124, 462 [PWRAP_CIPHER_IV_SEL] = 0x128, 463 [PWRAP_CIPHER_EN] = 0x12c, 464 [PWRAP_CIPHER_RDY] = 0x130, 465 [PWRAP_CIPHER_MODE] = 0x134, 466 [PWRAP_CIPHER_SWRST] = 0x138, 467 [PWRAP_DCM_EN] = 0x13c, 468 [PWRAP_DCM_DBC_PRD] = 0x140, 469 [PWRAP_ADC_CMD_ADDR] = 0x144, 470 [PWRAP_PWRAP_ADC_CMD] = 0x148, 471 [PWRAP_ADC_RDY_ADDR] = 0x14c, 472 [PWRAP_ADC_RDATA_ADDR1] = 0x150, 473 [PWRAP_ADC_RDATA_ADDR2] = 0x154, 474 }; 475 476 static int mt6765_regs[] = { 477 [PWRAP_MUX_SEL] = 0x0, 478 [PWRAP_WRAP_EN] = 0x4, 479 [PWRAP_DIO_EN] = 0x8, 480 [PWRAP_RDDMY] = 0x20, 481 [PWRAP_CSHEXT_WRITE] = 0x24, 482 [PWRAP_CSHEXT_READ] = 0x28, 483 [PWRAP_CSLEXT_START] = 0x2C, 484 [PWRAP_CSLEXT_END] = 0x30, 485 [PWRAP_STAUPD_PRD] = 0x3C, 486 [PWRAP_HARB_HPRIO] = 0x68, 487 [PWRAP_HIPRIO_ARB_EN] = 0x6C, 488 [PWRAP_MAN_EN] = 0x7C, 489 [PWRAP_MAN_CMD] = 0x80, 490 [PWRAP_WACS0_EN] = 0x8C, 491 [PWRAP_WACS1_EN] = 0x94, 492 [PWRAP_WACS2_EN] = 0x9C, 493 [PWRAP_INIT_DONE2] = 0xA0, 494 [PWRAP_WACS2_CMD] = 0xC20, 495 [PWRAP_WACS2_RDATA] = 0xC24, 496 [PWRAP_WACS2_VLDCLR] = 0xC28, 497 [PWRAP_INT_EN] = 0xB4, 498 [PWRAP_INT_FLG_RAW] = 0xB8, 499 [PWRAP_INT_FLG] = 0xBC, 500 [PWRAP_INT_CLR] = 0xC0, 501 [PWRAP_TIMER_EN] = 0xE8, 502 [PWRAP_WDT_UNIT] = 0xF0, 503 [PWRAP_WDT_SRC_EN] = 0xF4, 504 [PWRAP_DCM_EN] = 0x1DC, 505 [PWRAP_DCM_DBC_PRD] = 0x1E0, 506 }; 507 508 static int mt6797_regs[] = { 509 [PWRAP_MUX_SEL] = 0x0, 510 [PWRAP_WRAP_EN] = 0x4, 511 [PWRAP_DIO_EN] = 0x8, 512 [PWRAP_SIDLY] = 0xC, 513 [PWRAP_RDDMY] = 0x10, 514 [PWRAP_CSHEXT_WRITE] = 0x18, 515 [PWRAP_CSHEXT_READ] = 0x1C, 516 [PWRAP_CSLEXT_START] = 0x20, 517 [PWRAP_CSLEXT_END] = 0x24, 518 [PWRAP_STAUPD_PRD] = 0x28, 519 [PWRAP_HARB_HPRIO] = 0x50, 520 [PWRAP_HIPRIO_ARB_EN] = 0x54, 521 [PWRAP_MAN_EN] = 0x60, 522 [PWRAP_MAN_CMD] = 0x64, 523 [PWRAP_WACS0_EN] = 0x70, 524 [PWRAP_WACS1_EN] = 0x84, 525 [PWRAP_WACS2_EN] = 0x98, 526 [PWRAP_INIT_DONE2] = 0x9C, 527 [PWRAP_WACS2_CMD] = 0xA0, 528 [PWRAP_WACS2_RDATA] = 0xA4, 529 [PWRAP_WACS2_VLDCLR] = 0xA8, 530 [PWRAP_INT_EN] = 0xC0, 531 [PWRAP_INT_FLG_RAW] = 0xC4, 532 [PWRAP_INT_FLG] = 0xC8, 533 [PWRAP_INT_CLR] = 0xCC, 534 [PWRAP_TIMER_EN] = 0xF4, 535 [PWRAP_WDT_UNIT] = 0xFC, 536 [PWRAP_WDT_SRC_EN] = 0x100, 537 [PWRAP_DCM_EN] = 0x1CC, 538 [PWRAP_DCM_DBC_PRD] = 0x1D4, 539 }; 540 541 static int mt7622_regs[] = { 542 [PWRAP_MUX_SEL] = 0x0, 543 [PWRAP_WRAP_EN] = 0x4, 544 [PWRAP_DIO_EN] = 0x8, 545 [PWRAP_SIDLY] = 0xC, 546 [PWRAP_RDDMY] = 0x10, 547 [PWRAP_SI_CK_CON] = 0x14, 548 [PWRAP_CSHEXT_WRITE] = 0x18, 549 [PWRAP_CSHEXT_READ] = 0x1C, 550 [PWRAP_CSLEXT_START] = 0x20, 551 [PWRAP_CSLEXT_END] = 0x24, 552 [PWRAP_STAUPD_PRD] = 0x28, 553 [PWRAP_STAUPD_GRPEN] = 0x2C, 554 [PWRAP_EINT_STA0_ADR] = 0x30, 555 [PWRAP_EINT_STA1_ADR] = 0x34, 556 [PWRAP_STA] = 0x38, 557 [PWRAP_CLR] = 0x3C, 558 [PWRAP_STAUPD_MAN_TRIG] = 0x40, 559 [PWRAP_STAUPD_STA] = 0x44, 560 [PWRAP_WRAP_STA] = 0x48, 561 [PWRAP_HARB_INIT] = 0x4C, 562 [PWRAP_HARB_HPRIO] = 0x50, 563 [PWRAP_HIPRIO_ARB_EN] = 0x54, 564 [PWRAP_HARB_STA0] = 0x58, 565 [PWRAP_HARB_STA1] = 0x5C, 566 [PWRAP_MAN_EN] = 0x60, 567 [PWRAP_MAN_CMD] = 0x64, 568 [PWRAP_MAN_RDATA] = 0x68, 569 [PWRAP_MAN_VLDCLR] = 0x6C, 570 [PWRAP_WACS0_EN] = 0x70, 571 [PWRAP_INIT_DONE0] = 0x74, 572 [PWRAP_WACS0_CMD] = 0x78, 573 [PWRAP_WACS0_RDATA] = 0x7C, 574 [PWRAP_WACS0_VLDCLR] = 0x80, 575 [PWRAP_WACS1_EN] = 0x84, 576 [PWRAP_INIT_DONE1] = 0x88, 577 [PWRAP_WACS1_CMD] = 0x8C, 578 [PWRAP_WACS1_RDATA] = 0x90, 579 [PWRAP_WACS1_VLDCLR] = 0x94, 580 [PWRAP_WACS2_EN] = 0x98, 581 [PWRAP_INIT_DONE2] = 0x9C, 582 [PWRAP_WACS2_CMD] = 0xA0, 583 [PWRAP_WACS2_RDATA] = 0xA4, 584 [PWRAP_WACS2_VLDCLR] = 0xA8, 585 [PWRAP_INT_EN] = 0xAC, 586 [PWRAP_INT_FLG_RAW] = 0xB0, 587 [PWRAP_INT_FLG] = 0xB4, 588 [PWRAP_INT_CLR] = 0xB8, 589 [PWRAP_SIG_ADR] = 0xBC, 590 [PWRAP_SIG_MODE] = 0xC0, 591 [PWRAP_SIG_VALUE] = 0xC4, 592 [PWRAP_SIG_ERRVAL] = 0xC8, 593 [PWRAP_CRC_EN] = 0xCC, 594 [PWRAP_TIMER_EN] = 0xD0, 595 [PWRAP_TIMER_STA] = 0xD4, 596 [PWRAP_WDT_UNIT] = 0xD8, 597 [PWRAP_WDT_SRC_EN] = 0xDC, 598 [PWRAP_WDT_FLG] = 0xE0, 599 [PWRAP_DEBUG_INT_SEL] = 0xE4, 600 [PWRAP_DVFS_ADR0] = 0xE8, 601 [PWRAP_DVFS_WDATA0] = 0xEC, 602 [PWRAP_DVFS_ADR1] = 0xF0, 603 [PWRAP_DVFS_WDATA1] = 0xF4, 604 [PWRAP_DVFS_ADR2] = 0xF8, 605 [PWRAP_DVFS_WDATA2] = 0xFC, 606 [PWRAP_DVFS_ADR3] = 0x100, 607 [PWRAP_DVFS_WDATA3] = 0x104, 608 [PWRAP_DVFS_ADR4] = 0x108, 609 [PWRAP_DVFS_WDATA4] = 0x10C, 610 [PWRAP_DVFS_ADR5] = 0x110, 611 [PWRAP_DVFS_WDATA5] = 0x114, 612 [PWRAP_DVFS_ADR6] = 0x118, 613 [PWRAP_DVFS_WDATA6] = 0x11C, 614 [PWRAP_DVFS_ADR7] = 0x120, 615 [PWRAP_DVFS_WDATA7] = 0x124, 616 [PWRAP_DVFS_ADR8] = 0x128, 617 [PWRAP_DVFS_WDATA8] = 0x12C, 618 [PWRAP_DVFS_ADR9] = 0x130, 619 [PWRAP_DVFS_WDATA9] = 0x134, 620 [PWRAP_DVFS_ADR10] = 0x138, 621 [PWRAP_DVFS_WDATA10] = 0x13C, 622 [PWRAP_DVFS_ADR11] = 0x140, 623 [PWRAP_DVFS_WDATA11] = 0x144, 624 [PWRAP_DVFS_ADR12] = 0x148, 625 [PWRAP_DVFS_WDATA12] = 0x14C, 626 [PWRAP_DVFS_ADR13] = 0x150, 627 [PWRAP_DVFS_WDATA13] = 0x154, 628 [PWRAP_DVFS_ADR14] = 0x158, 629 [PWRAP_DVFS_WDATA14] = 0x15C, 630 [PWRAP_DVFS_ADR15] = 0x160, 631 [PWRAP_DVFS_WDATA15] = 0x164, 632 [PWRAP_SPMINF_STA] = 0x168, 633 [PWRAP_CIPHER_KEY_SEL] = 0x16C, 634 [PWRAP_CIPHER_IV_SEL] = 0x170, 635 [PWRAP_CIPHER_EN] = 0x174, 636 [PWRAP_CIPHER_RDY] = 0x178, 637 [PWRAP_CIPHER_MODE] = 0x17C, 638 [PWRAP_CIPHER_SWRST] = 0x180, 639 [PWRAP_DCM_EN] = 0x184, 640 [PWRAP_DCM_DBC_PRD] = 0x188, 641 [PWRAP_EXT_CK] = 0x18C, 642 [PWRAP_ADC_CMD_ADDR] = 0x190, 643 [PWRAP_PWRAP_ADC_CMD] = 0x194, 644 [PWRAP_ADC_RDATA_ADDR] = 0x198, 645 [PWRAP_GPS_STA] = 0x19C, 646 [PWRAP_SW_RST] = 0x1A0, 647 [PWRAP_DVFS_STEP_CTRL0] = 0x238, 648 [PWRAP_DVFS_STEP_CTRL1] = 0x23C, 649 [PWRAP_DVFS_STEP_CTRL2] = 0x240, 650 [PWRAP_SPI2_CTRL] = 0x244, 651 }; 652 653 static int mt8135_regs[] = { 654 [PWRAP_MUX_SEL] = 0x0, 655 [PWRAP_WRAP_EN] = 0x4, 656 [PWRAP_DIO_EN] = 0x8, 657 [PWRAP_SIDLY] = 0xc, 658 [PWRAP_CSHEXT] = 0x10, 659 [PWRAP_CSHEXT_WRITE] = 0x14, 660 [PWRAP_CSHEXT_READ] = 0x18, 661 [PWRAP_CSLEXT_START] = 0x1c, 662 [PWRAP_CSLEXT_END] = 0x20, 663 [PWRAP_STAUPD_PRD] = 0x24, 664 [PWRAP_STAUPD_GRPEN] = 0x28, 665 [PWRAP_STAUPD_MAN_TRIG] = 0x2c, 666 [PWRAP_STAUPD_STA] = 0x30, 667 [PWRAP_EVENT_IN_EN] = 0x34, 668 [PWRAP_EVENT_DST_EN] = 0x38, 669 [PWRAP_WRAP_STA] = 0x3c, 670 [PWRAP_RRARB_INIT] = 0x40, 671 [PWRAP_RRARB_EN] = 0x44, 672 [PWRAP_RRARB_STA0] = 0x48, 673 [PWRAP_RRARB_STA1] = 0x4c, 674 [PWRAP_HARB_INIT] = 0x50, 675 [PWRAP_HARB_HPRIO] = 0x54, 676 [PWRAP_HIPRIO_ARB_EN] = 0x58, 677 [PWRAP_HARB_STA0] = 0x5c, 678 [PWRAP_HARB_STA1] = 0x60, 679 [PWRAP_MAN_EN] = 0x64, 680 [PWRAP_MAN_CMD] = 0x68, 681 [PWRAP_MAN_RDATA] = 0x6c, 682 [PWRAP_MAN_VLDCLR] = 0x70, 683 [PWRAP_WACS0_EN] = 0x74, 684 [PWRAP_INIT_DONE0] = 0x78, 685 [PWRAP_WACS0_CMD] = 0x7c, 686 [PWRAP_WACS0_RDATA] = 0x80, 687 [PWRAP_WACS0_VLDCLR] = 0x84, 688 [PWRAP_WACS1_EN] = 0x88, 689 [PWRAP_INIT_DONE1] = 0x8c, 690 [PWRAP_WACS1_CMD] = 0x90, 691 [PWRAP_WACS1_RDATA] = 0x94, 692 [PWRAP_WACS1_VLDCLR] = 0x98, 693 [PWRAP_WACS2_EN] = 0x9c, 694 [PWRAP_INIT_DONE2] = 0xa0, 695 [PWRAP_WACS2_CMD] = 0xa4, 696 [PWRAP_WACS2_RDATA] = 0xa8, 697 [PWRAP_WACS2_VLDCLR] = 0xac, 698 [PWRAP_INT_EN] = 0xb0, 699 [PWRAP_INT_FLG_RAW] = 0xb4, 700 [PWRAP_INT_FLG] = 0xb8, 701 [PWRAP_INT_CLR] = 0xbc, 702 [PWRAP_SIG_ADR] = 0xc0, 703 [PWRAP_SIG_MODE] = 0xc4, 704 [PWRAP_SIG_VALUE] = 0xc8, 705 [PWRAP_SIG_ERRVAL] = 0xcc, 706 [PWRAP_CRC_EN] = 0xd0, 707 [PWRAP_EVENT_STA] = 0xd4, 708 [PWRAP_EVENT_STACLR] = 0xd8, 709 [PWRAP_TIMER_EN] = 0xdc, 710 [PWRAP_TIMER_STA] = 0xe0, 711 [PWRAP_WDT_UNIT] = 0xe4, 712 [PWRAP_WDT_SRC_EN] = 0xe8, 713 [PWRAP_WDT_FLG] = 0xec, 714 [PWRAP_DEBUG_INT_SEL] = 0xf0, 715 [PWRAP_CIPHER_KEY_SEL] = 0x134, 716 [PWRAP_CIPHER_IV_SEL] = 0x138, 717 [PWRAP_CIPHER_LOAD] = 0x13c, 718 [PWRAP_CIPHER_START] = 0x140, 719 [PWRAP_CIPHER_RDY] = 0x144, 720 [PWRAP_CIPHER_MODE] = 0x148, 721 [PWRAP_CIPHER_SWRST] = 0x14c, 722 [PWRAP_DCM_EN] = 0x15c, 723 [PWRAP_DCM_DBC_PRD] = 0x160, 724 }; 725 726 static int mt8173_regs[] = { 727 [PWRAP_MUX_SEL] = 0x0, 728 [PWRAP_WRAP_EN] = 0x4, 729 [PWRAP_DIO_EN] = 0x8, 730 [PWRAP_SIDLY] = 0xc, 731 [PWRAP_RDDMY] = 0x10, 732 [PWRAP_SI_CK_CON] = 0x14, 733 [PWRAP_CSHEXT_WRITE] = 0x18, 734 [PWRAP_CSHEXT_READ] = 0x1c, 735 [PWRAP_CSLEXT_START] = 0x20, 736 [PWRAP_CSLEXT_END] = 0x24, 737 [PWRAP_STAUPD_PRD] = 0x28, 738 [PWRAP_STAUPD_GRPEN] = 0x2c, 739 [PWRAP_STAUPD_MAN_TRIG] = 0x40, 740 [PWRAP_STAUPD_STA] = 0x44, 741 [PWRAP_WRAP_STA] = 0x48, 742 [PWRAP_HARB_INIT] = 0x4c, 743 [PWRAP_HARB_HPRIO] = 0x50, 744 [PWRAP_HIPRIO_ARB_EN] = 0x54, 745 [PWRAP_HARB_STA0] = 0x58, 746 [PWRAP_HARB_STA1] = 0x5c, 747 [PWRAP_MAN_EN] = 0x60, 748 [PWRAP_MAN_CMD] = 0x64, 749 [PWRAP_MAN_RDATA] = 0x68, 750 [PWRAP_MAN_VLDCLR] = 0x6c, 751 [PWRAP_WACS0_EN] = 0x70, 752 [PWRAP_INIT_DONE0] = 0x74, 753 [PWRAP_WACS0_CMD] = 0x78, 754 [PWRAP_WACS0_RDATA] = 0x7c, 755 [PWRAP_WACS0_VLDCLR] = 0x80, 756 [PWRAP_WACS1_EN] = 0x84, 757 [PWRAP_INIT_DONE1] = 0x88, 758 [PWRAP_WACS1_CMD] = 0x8c, 759 [PWRAP_WACS1_RDATA] = 0x90, 760 [PWRAP_WACS1_VLDCLR] = 0x94, 761 [PWRAP_WACS2_EN] = 0x98, 762 [PWRAP_INIT_DONE2] = 0x9c, 763 [PWRAP_WACS2_CMD] = 0xa0, 764 [PWRAP_WACS2_RDATA] = 0xa4, 765 [PWRAP_WACS2_VLDCLR] = 0xa8, 766 [PWRAP_INT_EN] = 0xac, 767 [PWRAP_INT_FLG_RAW] = 0xb0, 768 [PWRAP_INT_FLG] = 0xb4, 769 [PWRAP_INT_CLR] = 0xb8, 770 [PWRAP_SIG_ADR] = 0xbc, 771 [PWRAP_SIG_MODE] = 0xc0, 772 [PWRAP_SIG_VALUE] = 0xc4, 773 [PWRAP_SIG_ERRVAL] = 0xc8, 774 [PWRAP_CRC_EN] = 0xcc, 775 [PWRAP_TIMER_EN] = 0xd0, 776 [PWRAP_TIMER_STA] = 0xd4, 777 [PWRAP_WDT_UNIT] = 0xd8, 778 [PWRAP_WDT_SRC_EN] = 0xdc, 779 [PWRAP_WDT_FLG] = 0xe0, 780 [PWRAP_DEBUG_INT_SEL] = 0xe4, 781 [PWRAP_DVFS_ADR0] = 0xe8, 782 [PWRAP_DVFS_WDATA0] = 0xec, 783 [PWRAP_DVFS_ADR1] = 0xf0, 784 [PWRAP_DVFS_WDATA1] = 0xf4, 785 [PWRAP_DVFS_ADR2] = 0xf8, 786 [PWRAP_DVFS_WDATA2] = 0xfc, 787 [PWRAP_DVFS_ADR3] = 0x100, 788 [PWRAP_DVFS_WDATA3] = 0x104, 789 [PWRAP_DVFS_ADR4] = 0x108, 790 [PWRAP_DVFS_WDATA4] = 0x10c, 791 [PWRAP_DVFS_ADR5] = 0x110, 792 [PWRAP_DVFS_WDATA5] = 0x114, 793 [PWRAP_DVFS_ADR6] = 0x118, 794 [PWRAP_DVFS_WDATA6] = 0x11c, 795 [PWRAP_DVFS_ADR7] = 0x120, 796 [PWRAP_DVFS_WDATA7] = 0x124, 797 [PWRAP_SPMINF_STA] = 0x128, 798 [PWRAP_CIPHER_KEY_SEL] = 0x12c, 799 [PWRAP_CIPHER_IV_SEL] = 0x130, 800 [PWRAP_CIPHER_EN] = 0x134, 801 [PWRAP_CIPHER_RDY] = 0x138, 802 [PWRAP_CIPHER_MODE] = 0x13c, 803 [PWRAP_CIPHER_SWRST] = 0x140, 804 [PWRAP_DCM_EN] = 0x144, 805 [PWRAP_DCM_DBC_PRD] = 0x148, 806 }; 807 808 static int mt8183_regs[] = { 809 [PWRAP_MUX_SEL] = 0x0, 810 [PWRAP_WRAP_EN] = 0x4, 811 [PWRAP_DIO_EN] = 0x8, 812 [PWRAP_SI_SAMPLE_CTRL] = 0xC, 813 [PWRAP_RDDMY] = 0x14, 814 [PWRAP_CSHEXT_WRITE] = 0x18, 815 [PWRAP_CSHEXT_READ] = 0x1C, 816 [PWRAP_CSLEXT_WRITE] = 0x20, 817 [PWRAP_CSLEXT_READ] = 0x24, 818 [PWRAP_EXT_CK_WRITE] = 0x28, 819 [PWRAP_STAUPD_CTRL] = 0x30, 820 [PWRAP_STAUPD_GRPEN] = 0x34, 821 [PWRAP_EINT_STA0_ADR] = 0x38, 822 [PWRAP_HARB_HPRIO] = 0x5C, 823 [PWRAP_HIPRIO_ARB_EN] = 0x60, 824 [PWRAP_MAN_EN] = 0x70, 825 [PWRAP_MAN_CMD] = 0x74, 826 [PWRAP_WACS0_EN] = 0x80, 827 [PWRAP_INIT_DONE0] = 0x84, 828 [PWRAP_WACS1_EN] = 0x88, 829 [PWRAP_INIT_DONE1] = 0x8C, 830 [PWRAP_WACS2_EN] = 0x90, 831 [PWRAP_INIT_DONE2] = 0x94, 832 [PWRAP_WACS_P2P_EN] = 0xA0, 833 [PWRAP_INIT_DONE_P2P] = 0xA4, 834 [PWRAP_WACS_MD32_EN] = 0xA8, 835 [PWRAP_INIT_DONE_MD32] = 0xAC, 836 [PWRAP_INT_EN] = 0xB0, 837 [PWRAP_INT_FLG] = 0xB8, 838 [PWRAP_INT_CLR] = 0xBC, 839 [PWRAP_INT1_EN] = 0xC0, 840 [PWRAP_INT1_FLG] = 0xC8, 841 [PWRAP_INT1_CLR] = 0xCC, 842 [PWRAP_SIG_ADR] = 0xD0, 843 [PWRAP_CRC_EN] = 0xE0, 844 [PWRAP_TIMER_EN] = 0xE4, 845 [PWRAP_WDT_UNIT] = 0xEC, 846 [PWRAP_WDT_SRC_EN] = 0xF0, 847 [PWRAP_WDT_SRC_EN_1] = 0xF4, 848 [PWRAP_INT_GPS_AUXADC_CMD_ADDR] = 0x1DC, 849 [PWRAP_INT_GPS_AUXADC_CMD] = 0x1E0, 850 [PWRAP_INT_GPS_AUXADC_RDATA_ADDR] = 0x1E4, 851 [PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] = 0x1E8, 852 [PWRAP_GPSINF_0_STA] = 0x1EC, 853 [PWRAP_GPSINF_1_STA] = 0x1F0, 854 [PWRAP_WACS2_CMD] = 0xC20, 855 [PWRAP_WACS2_RDATA] = 0xC24, 856 [PWRAP_WACS2_VLDCLR] = 0xC28, 857 }; 858 859 static int mt8516_regs[] = { 860 [PWRAP_MUX_SEL] = 0x0, 861 [PWRAP_WRAP_EN] = 0x4, 862 [PWRAP_DIO_EN] = 0x8, 863 [PWRAP_SIDLY] = 0xc, 864 [PWRAP_RDDMY] = 0x10, 865 [PWRAP_SI_CK_CON] = 0x14, 866 [PWRAP_CSHEXT_WRITE] = 0x18, 867 [PWRAP_CSHEXT_READ] = 0x1c, 868 [PWRAP_CSLEXT_START] = 0x20, 869 [PWRAP_CSLEXT_END] = 0x24, 870 [PWRAP_STAUPD_PRD] = 0x28, 871 [PWRAP_STAUPD_GRPEN] = 0x2c, 872 [PWRAP_STAUPD_MAN_TRIG] = 0x40, 873 [PWRAP_STAUPD_STA] = 0x44, 874 [PWRAP_WRAP_STA] = 0x48, 875 [PWRAP_HARB_INIT] = 0x4c, 876 [PWRAP_HARB_HPRIO] = 0x50, 877 [PWRAP_HIPRIO_ARB_EN] = 0x54, 878 [PWRAP_HARB_STA0] = 0x58, 879 [PWRAP_HARB_STA1] = 0x5c, 880 [PWRAP_MAN_EN] = 0x60, 881 [PWRAP_MAN_CMD] = 0x64, 882 [PWRAP_MAN_RDATA] = 0x68, 883 [PWRAP_MAN_VLDCLR] = 0x6c, 884 [PWRAP_WACS0_EN] = 0x70, 885 [PWRAP_INIT_DONE0] = 0x74, 886 [PWRAP_WACS0_CMD] = 0x78, 887 [PWRAP_WACS0_RDATA] = 0x7c, 888 [PWRAP_WACS0_VLDCLR] = 0x80, 889 [PWRAP_WACS1_EN] = 0x84, 890 [PWRAP_INIT_DONE1] = 0x88, 891 [PWRAP_WACS1_CMD] = 0x8c, 892 [PWRAP_WACS1_RDATA] = 0x90, 893 [PWRAP_WACS1_VLDCLR] = 0x94, 894 [PWRAP_WACS2_EN] = 0x98, 895 [PWRAP_INIT_DONE2] = 0x9c, 896 [PWRAP_WACS2_CMD] = 0xa0, 897 [PWRAP_WACS2_RDATA] = 0xa4, 898 [PWRAP_WACS2_VLDCLR] = 0xa8, 899 [PWRAP_INT_EN] = 0xac, 900 [PWRAP_INT_FLG_RAW] = 0xb0, 901 [PWRAP_INT_FLG] = 0xb4, 902 [PWRAP_INT_CLR] = 0xb8, 903 [PWRAP_SIG_ADR] = 0xbc, 904 [PWRAP_SIG_MODE] = 0xc0, 905 [PWRAP_SIG_VALUE] = 0xc4, 906 [PWRAP_SIG_ERRVAL] = 0xc8, 907 [PWRAP_CRC_EN] = 0xcc, 908 [PWRAP_TIMER_EN] = 0xd0, 909 [PWRAP_TIMER_STA] = 0xd4, 910 [PWRAP_WDT_UNIT] = 0xd8, 911 [PWRAP_WDT_SRC_EN] = 0xdc, 912 [PWRAP_WDT_FLG] = 0xe0, 913 [PWRAP_DEBUG_INT_SEL] = 0xe4, 914 [PWRAP_DVFS_ADR0] = 0xe8, 915 [PWRAP_DVFS_WDATA0] = 0xec, 916 [PWRAP_DVFS_ADR1] = 0xf0, 917 [PWRAP_DVFS_WDATA1] = 0xf4, 918 [PWRAP_DVFS_ADR2] = 0xf8, 919 [PWRAP_DVFS_WDATA2] = 0xfc, 920 [PWRAP_DVFS_ADR3] = 0x100, 921 [PWRAP_DVFS_WDATA3] = 0x104, 922 [PWRAP_DVFS_ADR4] = 0x108, 923 [PWRAP_DVFS_WDATA4] = 0x10c, 924 [PWRAP_DVFS_ADR5] = 0x110, 925 [PWRAP_DVFS_WDATA5] = 0x114, 926 [PWRAP_DVFS_ADR6] = 0x118, 927 [PWRAP_DVFS_WDATA6] = 0x11c, 928 [PWRAP_DVFS_ADR7] = 0x120, 929 [PWRAP_DVFS_WDATA7] = 0x124, 930 [PWRAP_SPMINF_STA] = 0x128, 931 [PWRAP_CIPHER_KEY_SEL] = 0x12c, 932 [PWRAP_CIPHER_IV_SEL] = 0x130, 933 [PWRAP_CIPHER_EN] = 0x134, 934 [PWRAP_CIPHER_RDY] = 0x138, 935 [PWRAP_CIPHER_MODE] = 0x13c, 936 [PWRAP_CIPHER_SWRST] = 0x140, 937 [PWRAP_DCM_EN] = 0x144, 938 [PWRAP_DCM_DBC_PRD] = 0x148, 939 [PWRAP_SW_RST] = 0x168, 940 [PWRAP_OP_TYPE] = 0x16c, 941 [PWRAP_MSB_FIRST] = 0x170, 942 }; 943 944 enum pmic_type { 945 PMIC_MT6323, 946 PMIC_MT6351, 947 PMIC_MT6357, 948 PMIC_MT6358, 949 PMIC_MT6380, 950 PMIC_MT6397, 951 }; 952 953 enum pwrap_type { 954 PWRAP_MT2701, 955 PWRAP_MT6765, 956 PWRAP_MT6797, 957 PWRAP_MT7622, 958 PWRAP_MT8135, 959 PWRAP_MT8173, 960 PWRAP_MT8183, 961 PWRAP_MT8516, 962 }; 963 964 struct pmic_wrapper; 965 struct pwrap_slv_type { 966 const u32 *dew_regs; 967 enum pmic_type type; 968 const struct regmap_config *regmap; 969 /* Flags indicating the capability for the target slave */ 970 u32 caps; 971 /* 972 * pwrap operations are highly associated with the PMIC types, 973 * so the pointers added increases flexibility allowing determination 974 * which type is used by the detection through device tree. 975 */ 976 int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata); 977 int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata); 978 }; 979 980 struct pmic_wrapper { 981 struct device *dev; 982 void __iomem *base; 983 struct regmap *regmap; 984 const struct pmic_wrapper_type *master; 985 const struct pwrap_slv_type *slave; 986 struct clk *clk_spi; 987 struct clk *clk_wrap; 988 struct reset_control *rstc; 989 990 struct reset_control *rstc_bridge; 991 void __iomem *bridge_base; 992 }; 993 994 struct pmic_wrapper_type { 995 int *regs; 996 enum pwrap_type type; 997 u32 arb_en_all; 998 u32 int_en_all; 999 u32 int1_en_all; 1000 u32 spi_w; 1001 u32 wdt_src; 1002 /* Flags indicating the capability for the target pwrap */ 1003 u32 caps; 1004 int (*init_reg_clock)(struct pmic_wrapper *wrp); 1005 int (*init_soc_specific)(struct pmic_wrapper *wrp); 1006 }; 1007 1008 static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg) 1009 { 1010 return readl(wrp->base + wrp->master->regs[reg]); 1011 } 1012 1013 static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg) 1014 { 1015 writel(val, wrp->base + wrp->master->regs[reg]); 1016 } 1017 1018 static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp) 1019 { 1020 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); 1021 1022 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE; 1023 } 1024 1025 static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp) 1026 { 1027 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); 1028 1029 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR; 1030 } 1031 1032 /* 1033 * Timeout issue sometimes caused by the last read command 1034 * failed because pmic wrap could not got the FSM_VLDCLR 1035 * in time after finishing WACS2_CMD. It made state machine 1036 * still on FSM_VLDCLR and timeout next time. 1037 * Check the status of FSM and clear the vldclr to recovery the 1038 * error. 1039 */ 1040 static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp) 1041 { 1042 if (pwrap_is_fsm_vldclr(wrp)) 1043 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); 1044 } 1045 1046 static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp) 1047 { 1048 return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0; 1049 } 1050 1051 static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp) 1052 { 1053 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); 1054 1055 return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) && 1056 (val & PWRAP_STATE_SYNC_IDLE0); 1057 } 1058 1059 static int pwrap_wait_for_state(struct pmic_wrapper *wrp, 1060 bool (*fp)(struct pmic_wrapper *)) 1061 { 1062 unsigned long timeout; 1063 1064 timeout = jiffies + usecs_to_jiffies(10000); 1065 1066 do { 1067 if (time_after(jiffies, timeout)) 1068 return fp(wrp) ? 0 : -ETIMEDOUT; 1069 if (fp(wrp)) 1070 return 0; 1071 } while (1); 1072 } 1073 1074 static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) 1075 { 1076 int ret; 1077 1078 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); 1079 if (ret) { 1080 pwrap_leave_fsm_vldclr(wrp); 1081 return ret; 1082 } 1083 1084 pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD); 1085 1086 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr); 1087 if (ret) 1088 return ret; 1089 1090 *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA)); 1091 1092 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); 1093 1094 return 0; 1095 } 1096 1097 static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) 1098 { 1099 int ret, msb; 1100 1101 *rdata = 0; 1102 for (msb = 0; msb < 2; msb++) { 1103 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); 1104 if (ret) { 1105 pwrap_leave_fsm_vldclr(wrp); 1106 return ret; 1107 } 1108 1109 pwrap_writel(wrp, ((msb << 30) | (adr << 16)), 1110 PWRAP_WACS2_CMD); 1111 1112 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr); 1113 if (ret) 1114 return ret; 1115 1116 *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, 1117 PWRAP_WACS2_RDATA)) << (16 * msb)); 1118 1119 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); 1120 } 1121 1122 return 0; 1123 } 1124 1125 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) 1126 { 1127 return wrp->slave->pwrap_read(wrp, adr, rdata); 1128 } 1129 1130 static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata) 1131 { 1132 int ret; 1133 1134 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); 1135 if (ret) { 1136 pwrap_leave_fsm_vldclr(wrp); 1137 return ret; 1138 } 1139 1140 pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata, 1141 PWRAP_WACS2_CMD); 1142 1143 return 0; 1144 } 1145 1146 static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata) 1147 { 1148 int ret, msb, rdata; 1149 1150 for (msb = 0; msb < 2; msb++) { 1151 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); 1152 if (ret) { 1153 pwrap_leave_fsm_vldclr(wrp); 1154 return ret; 1155 } 1156 1157 pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) | 1158 ((wdata >> (msb * 16)) & 0xffff), 1159 PWRAP_WACS2_CMD); 1160 1161 /* 1162 * The pwrap_read operation is the requirement of hardware used 1163 * for the synchronization between two successive 16-bit 1164 * pwrap_writel operations composing one 32-bit bus writing. 1165 * Otherwise, we'll find the result fails on the lower 16-bit 1166 * pwrap writing. 1167 */ 1168 if (!msb) 1169 pwrap_read(wrp, adr, &rdata); 1170 } 1171 1172 return 0; 1173 } 1174 1175 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata) 1176 { 1177 return wrp->slave->pwrap_write(wrp, adr, wdata); 1178 } 1179 1180 static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata) 1181 { 1182 return pwrap_read(context, adr, rdata); 1183 } 1184 1185 static int pwrap_regmap_write(void *context, u32 adr, u32 wdata) 1186 { 1187 return pwrap_write(context, adr, wdata); 1188 } 1189 1190 static int pwrap_reset_spislave(struct pmic_wrapper *wrp) 1191 { 1192 int ret, i; 1193 1194 pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN); 1195 pwrap_writel(wrp, 0, PWRAP_WRAP_EN); 1196 pwrap_writel(wrp, 1, PWRAP_MUX_SEL); 1197 pwrap_writel(wrp, 1, PWRAP_MAN_EN); 1198 pwrap_writel(wrp, 0, PWRAP_DIO_EN); 1199 1200 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL, 1201 PWRAP_MAN_CMD); 1202 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS, 1203 PWRAP_MAN_CMD); 1204 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH, 1205 PWRAP_MAN_CMD); 1206 1207 for (i = 0; i < 4; i++) 1208 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS, 1209 PWRAP_MAN_CMD); 1210 1211 ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle); 1212 if (ret) { 1213 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); 1214 return ret; 1215 } 1216 1217 pwrap_writel(wrp, 0, PWRAP_MAN_EN); 1218 pwrap_writel(wrp, 0, PWRAP_MUX_SEL); 1219 1220 return 0; 1221 } 1222 1223 /* 1224 * pwrap_init_sidly - configure serial input delay 1225 * 1226 * This configures the serial input delay. We can configure 0, 2, 4 or 6ns 1227 * delay. Do a read test with all possible values and chose the best delay. 1228 */ 1229 static int pwrap_init_sidly(struct pmic_wrapper *wrp) 1230 { 1231 u32 rdata; 1232 u32 i; 1233 u32 pass = 0; 1234 signed char dly[16] = { 1235 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1 1236 }; 1237 1238 for (i = 0; i < 4; i++) { 1239 pwrap_writel(wrp, i, PWRAP_SIDLY); 1240 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], 1241 &rdata); 1242 if (rdata == PWRAP_DEW_READ_TEST_VAL) { 1243 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i); 1244 pass |= 1 << i; 1245 } 1246 } 1247 1248 if (dly[pass] < 0) { 1249 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n", 1250 pass); 1251 return -EIO; 1252 } 1253 1254 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY); 1255 1256 return 0; 1257 } 1258 1259 static int pwrap_init_dual_io(struct pmic_wrapper *wrp) 1260 { 1261 int ret; 1262 u32 rdata; 1263 1264 /* Enable dual IO mode */ 1265 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1); 1266 1267 /* Check IDLE & INIT_DONE in advance */ 1268 ret = pwrap_wait_for_state(wrp, 1269 pwrap_is_fsm_idle_and_sync_idle); 1270 if (ret) { 1271 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); 1272 return ret; 1273 } 1274 1275 pwrap_writel(wrp, 1, PWRAP_DIO_EN); 1276 1277 /* Read Test */ 1278 pwrap_read(wrp, 1279 wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata); 1280 if (rdata != PWRAP_DEW_READ_TEST_VAL) { 1281 dev_err(wrp->dev, 1282 "Read failed on DIO mode: 0x%04x!=0x%04x\n", 1283 PWRAP_DEW_READ_TEST_VAL, rdata); 1284 return -EFAULT; 1285 } 1286 1287 return 0; 1288 } 1289 1290 /* 1291 * pwrap_init_chip_select_ext is used to configure CS extension time for each 1292 * phase during data transactions on the pwrap bus. 1293 */ 1294 static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write, 1295 u8 hext_read, u8 lext_start, 1296 u8 lext_end) 1297 { 1298 /* 1299 * After finishing a write and read transaction, extends CS high time 1300 * to be at least xT of BUS CLK as hext_write and hext_read specifies 1301 * respectively. 1302 */ 1303 pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE); 1304 pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ); 1305 1306 /* 1307 * Extends CS low time after CSL and before CSH command to be at 1308 * least xT of BUS CLK as lext_start and lext_end specifies 1309 * respectively. 1310 */ 1311 pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START); 1312 pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END); 1313 } 1314 1315 static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp) 1316 { 1317 switch (wrp->master->type) { 1318 case PWRAP_MT8173: 1319 pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2); 1320 break; 1321 case PWRAP_MT8135: 1322 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT); 1323 pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0); 1324 break; 1325 default: 1326 break; 1327 } 1328 1329 return 0; 1330 } 1331 1332 static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp) 1333 { 1334 switch (wrp->slave->type) { 1335 case PMIC_MT6397: 1336 pwrap_writel(wrp, 0xc, PWRAP_RDDMY); 1337 pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2); 1338 break; 1339 1340 case PMIC_MT6323: 1341 pwrap_writel(wrp, 0x8, PWRAP_RDDMY); 1342 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO], 1343 0x8); 1344 pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2); 1345 break; 1346 default: 1347 break; 1348 } 1349 1350 return 0; 1351 } 1352 1353 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp) 1354 { 1355 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1; 1356 } 1357 1358 static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp) 1359 { 1360 u32 rdata; 1361 int ret; 1362 1363 ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY], 1364 &rdata); 1365 if (ret) 1366 return false; 1367 1368 return rdata == 1; 1369 } 1370 1371 static int pwrap_init_cipher(struct pmic_wrapper *wrp) 1372 { 1373 int ret; 1374 u32 rdata = 0; 1375 1376 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST); 1377 pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST); 1378 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL); 1379 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL); 1380 1381 switch (wrp->master->type) { 1382 case PWRAP_MT8135: 1383 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD); 1384 pwrap_writel(wrp, 1, PWRAP_CIPHER_START); 1385 break; 1386 case PWRAP_MT2701: 1387 case PWRAP_MT6765: 1388 case PWRAP_MT6797: 1389 case PWRAP_MT8173: 1390 case PWRAP_MT8516: 1391 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN); 1392 break; 1393 case PWRAP_MT7622: 1394 pwrap_writel(wrp, 0, PWRAP_CIPHER_EN); 1395 break; 1396 case PWRAP_MT8183: 1397 break; 1398 } 1399 1400 /* Config cipher mode @PMIC */ 1401 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1); 1402 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0); 1403 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1); 1404 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2); 1405 1406 switch (wrp->slave->type) { 1407 case PMIC_MT6397: 1408 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 1409 0x1); 1410 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START], 1411 0x1); 1412 break; 1413 case PMIC_MT6323: 1414 case PMIC_MT6351: 1415 case PMIC_MT6357: 1416 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN], 1417 0x1); 1418 break; 1419 default: 1420 break; 1421 } 1422 1423 /* wait for cipher data ready@AP */ 1424 ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready); 1425 if (ret) { 1426 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret); 1427 return ret; 1428 } 1429 1430 /* wait for cipher data ready@PMIC */ 1431 ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready); 1432 if (ret) { 1433 dev_err(wrp->dev, 1434 "timeout waiting for cipher data ready@PMIC\n"); 1435 return ret; 1436 } 1437 1438 /* wait for cipher mode idle */ 1439 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1); 1440 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle); 1441 if (ret) { 1442 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret); 1443 return ret; 1444 } 1445 1446 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE); 1447 1448 /* Write Test */ 1449 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST], 1450 PWRAP_DEW_WRITE_TEST_VAL) || 1451 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST], 1452 &rdata) || 1453 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) { 1454 dev_err(wrp->dev, "rdata=0x%04X\n", rdata); 1455 return -EFAULT; 1456 } 1457 1458 return 0; 1459 } 1460 1461 static int pwrap_init_security(struct pmic_wrapper *wrp) 1462 { 1463 int ret; 1464 1465 /* Enable encryption */ 1466 ret = pwrap_init_cipher(wrp); 1467 if (ret) 1468 return ret; 1469 1470 /* Signature checking - using CRC */ 1471 if (pwrap_write(wrp, 1472 wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1)) 1473 return -EFAULT; 1474 1475 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN); 1476 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE); 1477 pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL], 1478 PWRAP_SIG_ADR); 1479 pwrap_writel(wrp, 1480 wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); 1481 1482 return 0; 1483 } 1484 1485 static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp) 1486 { 1487 /* enable pwrap events and pwrap bridge in AP side */ 1488 pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN); 1489 pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN); 1490 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN); 1491 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN); 1492 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN); 1493 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT); 1494 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN); 1495 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN); 1496 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN); 1497 1498 /* enable PMIC event out and sources */ 1499 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN], 1500 0x1) || 1501 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN], 1502 0xffff)) { 1503 dev_err(wrp->dev, "enable dewrap fail\n"); 1504 return -EFAULT; 1505 } 1506 1507 return 0; 1508 } 1509 1510 static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp) 1511 { 1512 /* PMIC_DEWRAP enables */ 1513 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN], 1514 0x1) || 1515 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN], 1516 0xffff)) { 1517 dev_err(wrp->dev, "enable dewrap fail\n"); 1518 return -EFAULT; 1519 } 1520 1521 return 0; 1522 } 1523 1524 static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp) 1525 { 1526 /* GPS_INTF initialization */ 1527 switch (wrp->slave->type) { 1528 case PMIC_MT6323: 1529 pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR); 1530 pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD); 1531 pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR); 1532 pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1); 1533 pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2); 1534 break; 1535 default: 1536 break; 1537 } 1538 1539 return 0; 1540 } 1541 1542 static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp) 1543 { 1544 pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD); 1545 /* enable 2wire SPI master */ 1546 pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL); 1547 1548 return 0; 1549 } 1550 1551 static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp) 1552 { 1553 pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN); 1554 1555 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1); 1556 pwrap_writel(wrp, 1, PWRAP_CRC_EN); 1557 pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR); 1558 pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR); 1559 1560 pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN); 1561 pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN); 1562 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P); 1563 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32); 1564 1565 return 0; 1566 } 1567 1568 static int pwrap_init(struct pmic_wrapper *wrp) 1569 { 1570 int ret; 1571 1572 if (wrp->rstc) 1573 reset_control_reset(wrp->rstc); 1574 if (wrp->rstc_bridge) 1575 reset_control_reset(wrp->rstc_bridge); 1576 1577 if (wrp->master->type == PWRAP_MT8173) { 1578 /* Enable DCM */ 1579 pwrap_writel(wrp, 3, PWRAP_DCM_EN); 1580 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); 1581 } 1582 1583 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { 1584 /* Reset SPI slave */ 1585 ret = pwrap_reset_spislave(wrp); 1586 if (ret) 1587 return ret; 1588 } 1589 1590 pwrap_writel(wrp, 1, PWRAP_WRAP_EN); 1591 1592 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); 1593 1594 pwrap_writel(wrp, 1, PWRAP_WACS2_EN); 1595 1596 ret = wrp->master->init_reg_clock(wrp); 1597 if (ret) 1598 return ret; 1599 1600 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { 1601 /* Setup serial input delay */ 1602 ret = pwrap_init_sidly(wrp); 1603 if (ret) 1604 return ret; 1605 } 1606 1607 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) { 1608 /* Enable dual I/O mode */ 1609 ret = pwrap_init_dual_io(wrp); 1610 if (ret) 1611 return ret; 1612 } 1613 1614 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) { 1615 /* Enable security on bus */ 1616 ret = pwrap_init_security(wrp); 1617 if (ret) 1618 return ret; 1619 } 1620 1621 if (wrp->master->type == PWRAP_MT8135) 1622 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN); 1623 1624 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN); 1625 pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN); 1626 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN); 1627 pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD); 1628 pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN); 1629 1630 if (wrp->master->init_soc_specific) { 1631 ret = wrp->master->init_soc_specific(wrp); 1632 if (ret) 1633 return ret; 1634 } 1635 1636 /* Setup the init done registers */ 1637 pwrap_writel(wrp, 1, PWRAP_INIT_DONE2); 1638 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0); 1639 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1); 1640 1641 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) { 1642 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3); 1643 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4); 1644 } 1645 1646 return 0; 1647 } 1648 1649 static irqreturn_t pwrap_interrupt(int irqno, void *dev_id) 1650 { 1651 u32 rdata; 1652 struct pmic_wrapper *wrp = dev_id; 1653 1654 rdata = pwrap_readl(wrp, PWRAP_INT_FLG); 1655 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata); 1656 pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR); 1657 1658 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) { 1659 rdata = pwrap_readl(wrp, PWRAP_INT1_FLG); 1660 dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata); 1661 pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR); 1662 } 1663 1664 return IRQ_HANDLED; 1665 } 1666 1667 static const struct regmap_config pwrap_regmap_config16 = { 1668 .reg_bits = 16, 1669 .val_bits = 16, 1670 .reg_stride = 2, 1671 .reg_read = pwrap_regmap_read, 1672 .reg_write = pwrap_regmap_write, 1673 .max_register = 0xffff, 1674 }; 1675 1676 static const struct regmap_config pwrap_regmap_config32 = { 1677 .reg_bits = 32, 1678 .val_bits = 32, 1679 .reg_stride = 4, 1680 .reg_read = pwrap_regmap_read, 1681 .reg_write = pwrap_regmap_write, 1682 .max_register = 0xffff, 1683 }; 1684 1685 static const struct pwrap_slv_type pmic_mt6323 = { 1686 .dew_regs = mt6323_regs, 1687 .type = PMIC_MT6323, 1688 .regmap = &pwrap_regmap_config16, 1689 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | 1690 PWRAP_SLV_CAP_SECURITY, 1691 .pwrap_read = pwrap_read16, 1692 .pwrap_write = pwrap_write16, 1693 }; 1694 1695 static const struct pwrap_slv_type pmic_mt6351 = { 1696 .dew_regs = mt6351_regs, 1697 .type = PMIC_MT6351, 1698 .regmap = &pwrap_regmap_config16, 1699 .caps = 0, 1700 .pwrap_read = pwrap_read16, 1701 .pwrap_write = pwrap_write16, 1702 }; 1703 1704 static const struct pwrap_slv_type pmic_mt6357 = { 1705 .dew_regs = mt6357_regs, 1706 .type = PMIC_MT6357, 1707 .regmap = &pwrap_regmap_config16, 1708 .caps = 0, 1709 .pwrap_read = pwrap_read16, 1710 .pwrap_write = pwrap_write16, 1711 }; 1712 1713 static const struct pwrap_slv_type pmic_mt6358 = { 1714 .dew_regs = mt6358_regs, 1715 .type = PMIC_MT6358, 1716 .regmap = &pwrap_regmap_config16, 1717 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO, 1718 .pwrap_read = pwrap_read16, 1719 .pwrap_write = pwrap_write16, 1720 }; 1721 1722 static const struct pwrap_slv_type pmic_mt6380 = { 1723 .dew_regs = NULL, 1724 .type = PMIC_MT6380, 1725 .regmap = &pwrap_regmap_config32, 1726 .caps = 0, 1727 .pwrap_read = pwrap_read32, 1728 .pwrap_write = pwrap_write32, 1729 }; 1730 1731 static const struct pwrap_slv_type pmic_mt6397 = { 1732 .dew_regs = mt6397_regs, 1733 .type = PMIC_MT6397, 1734 .regmap = &pwrap_regmap_config16, 1735 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | 1736 PWRAP_SLV_CAP_SECURITY, 1737 .pwrap_read = pwrap_read16, 1738 .pwrap_write = pwrap_write16, 1739 }; 1740 1741 static const struct of_device_id of_slave_match_tbl[] = { 1742 { 1743 .compatible = "mediatek,mt6323", 1744 .data = &pmic_mt6323, 1745 }, { 1746 .compatible = "mediatek,mt6351", 1747 .data = &pmic_mt6351, 1748 }, { 1749 .compatible = "mediatek,mt6357", 1750 .data = &pmic_mt6357, 1751 }, { 1752 .compatible = "mediatek,mt6358", 1753 .data = &pmic_mt6358, 1754 }, { 1755 /* The MT6380 PMIC only implements a regulator, so we bind it 1756 * directly instead of using a MFD. 1757 */ 1758 .compatible = "mediatek,mt6380-regulator", 1759 .data = &pmic_mt6380, 1760 }, { 1761 .compatible = "mediatek,mt6397", 1762 .data = &pmic_mt6397, 1763 }, { 1764 /* sentinel */ 1765 } 1766 }; 1767 MODULE_DEVICE_TABLE(of, of_slave_match_tbl); 1768 1769 static const struct pmic_wrapper_type pwrap_mt2701 = { 1770 .regs = mt2701_regs, 1771 .type = PWRAP_MT2701, 1772 .arb_en_all = 0x3f, 1773 .int_en_all = ~(u32)(BIT(31) | BIT(2)), 1774 .int1_en_all = 0, 1775 .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW, 1776 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 1777 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 1778 .init_reg_clock = pwrap_mt2701_init_reg_clock, 1779 .init_soc_specific = pwrap_mt2701_init_soc_specific, 1780 }; 1781 1782 static const struct pmic_wrapper_type pwrap_mt6765 = { 1783 .regs = mt6765_regs, 1784 .type = PWRAP_MT6765, 1785 .arb_en_all = 0x3fd35, 1786 .int_en_all = 0xffffffff, 1787 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 1788 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 1789 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 1790 .init_reg_clock = pwrap_common_init_reg_clock, 1791 .init_soc_specific = NULL, 1792 }; 1793 1794 static const struct pmic_wrapper_type pwrap_mt6797 = { 1795 .regs = mt6797_regs, 1796 .type = PWRAP_MT6797, 1797 .arb_en_all = 0x01fff, 1798 .int_en_all = 0xffffffc6, 1799 .int1_en_all = 0, 1800 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 1801 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 1802 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 1803 .init_reg_clock = pwrap_common_init_reg_clock, 1804 .init_soc_specific = NULL, 1805 }; 1806 1807 static const struct pmic_wrapper_type pwrap_mt7622 = { 1808 .regs = mt7622_regs, 1809 .type = PWRAP_MT7622, 1810 .arb_en_all = 0xff, 1811 .int_en_all = ~(u32)BIT(31), 1812 .int1_en_all = 0, 1813 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 1814 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 1815 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 1816 .init_reg_clock = pwrap_common_init_reg_clock, 1817 .init_soc_specific = pwrap_mt7622_init_soc_specific, 1818 }; 1819 1820 static const struct pmic_wrapper_type pwrap_mt8135 = { 1821 .regs = mt8135_regs, 1822 .type = PWRAP_MT8135, 1823 .arb_en_all = 0x1ff, 1824 .int_en_all = ~(u32)(BIT(31) | BIT(1)), 1825 .int1_en_all = 0, 1826 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 1827 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 1828 .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM, 1829 .init_reg_clock = pwrap_common_init_reg_clock, 1830 .init_soc_specific = pwrap_mt8135_init_soc_specific, 1831 }; 1832 1833 static const struct pmic_wrapper_type pwrap_mt8173 = { 1834 .regs = mt8173_regs, 1835 .type = PWRAP_MT8173, 1836 .arb_en_all = 0x3f, 1837 .int_en_all = ~(u32)(BIT(31) | BIT(1)), 1838 .int1_en_all = 0, 1839 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 1840 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD, 1841 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, 1842 .init_reg_clock = pwrap_common_init_reg_clock, 1843 .init_soc_specific = pwrap_mt8173_init_soc_specific, 1844 }; 1845 1846 static const struct pmic_wrapper_type pwrap_mt8183 = { 1847 .regs = mt8183_regs, 1848 .type = PWRAP_MT8183, 1849 .arb_en_all = 0x3fa75, 1850 .int_en_all = 0xffffffff, 1851 .int1_en_all = 0xeef7ffff, 1852 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 1853 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 1854 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1, 1855 .init_reg_clock = pwrap_common_init_reg_clock, 1856 .init_soc_specific = pwrap_mt8183_init_soc_specific, 1857 }; 1858 1859 static struct pmic_wrapper_type pwrap_mt8516 = { 1860 .regs = mt8516_regs, 1861 .type = PWRAP_MT8516, 1862 .arb_en_all = 0xff, 1863 .int_en_all = ~(u32)(BIT(31) | BIT(2)), 1864 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 1865 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 1866 .caps = PWRAP_CAP_DCM, 1867 .init_reg_clock = pwrap_mt2701_init_reg_clock, 1868 .init_soc_specific = NULL, 1869 }; 1870 1871 static const struct of_device_id of_pwrap_match_tbl[] = { 1872 { 1873 .compatible = "mediatek,mt2701-pwrap", 1874 .data = &pwrap_mt2701, 1875 }, { 1876 .compatible = "mediatek,mt6765-pwrap", 1877 .data = &pwrap_mt6765, 1878 }, { 1879 .compatible = "mediatek,mt6797-pwrap", 1880 .data = &pwrap_mt6797, 1881 }, { 1882 .compatible = "mediatek,mt7622-pwrap", 1883 .data = &pwrap_mt7622, 1884 }, { 1885 .compatible = "mediatek,mt8135-pwrap", 1886 .data = &pwrap_mt8135, 1887 }, { 1888 .compatible = "mediatek,mt8173-pwrap", 1889 .data = &pwrap_mt8173, 1890 }, { 1891 .compatible = "mediatek,mt8183-pwrap", 1892 .data = &pwrap_mt8183, 1893 }, { 1894 .compatible = "mediatek,mt8516-pwrap", 1895 .data = &pwrap_mt8516, 1896 }, { 1897 /* sentinel */ 1898 } 1899 }; 1900 MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl); 1901 1902 static int pwrap_probe(struct platform_device *pdev) 1903 { 1904 int ret, irq; 1905 struct pmic_wrapper *wrp; 1906 struct device_node *np = pdev->dev.of_node; 1907 const struct of_device_id *of_slave_id = NULL; 1908 struct resource *res; 1909 1910 if (np->child) 1911 of_slave_id = of_match_node(of_slave_match_tbl, np->child); 1912 1913 if (!of_slave_id) { 1914 dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n"); 1915 return -EINVAL; 1916 } 1917 1918 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL); 1919 if (!wrp) 1920 return -ENOMEM; 1921 1922 platform_set_drvdata(pdev, wrp); 1923 1924 wrp->master = of_device_get_match_data(&pdev->dev); 1925 wrp->slave = of_slave_id->data; 1926 wrp->dev = &pdev->dev; 1927 1928 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap"); 1929 wrp->base = devm_ioremap_resource(wrp->dev, res); 1930 if (IS_ERR(wrp->base)) 1931 return PTR_ERR(wrp->base); 1932 1933 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) { 1934 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap"); 1935 if (IS_ERR(wrp->rstc)) { 1936 ret = PTR_ERR(wrp->rstc); 1937 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret); 1938 return ret; 1939 } 1940 } 1941 1942 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) { 1943 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1944 "pwrap-bridge"); 1945 wrp->bridge_base = devm_ioremap_resource(wrp->dev, res); 1946 if (IS_ERR(wrp->bridge_base)) 1947 return PTR_ERR(wrp->bridge_base); 1948 1949 wrp->rstc_bridge = devm_reset_control_get(wrp->dev, 1950 "pwrap-bridge"); 1951 if (IS_ERR(wrp->rstc_bridge)) { 1952 ret = PTR_ERR(wrp->rstc_bridge); 1953 dev_dbg(wrp->dev, 1954 "cannot get pwrap-bridge reset: %d\n", ret); 1955 return ret; 1956 } 1957 } 1958 1959 wrp->clk_spi = devm_clk_get(wrp->dev, "spi"); 1960 if (IS_ERR(wrp->clk_spi)) { 1961 dev_dbg(wrp->dev, "failed to get clock: %ld\n", 1962 PTR_ERR(wrp->clk_spi)); 1963 return PTR_ERR(wrp->clk_spi); 1964 } 1965 1966 wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap"); 1967 if (IS_ERR(wrp->clk_wrap)) { 1968 dev_dbg(wrp->dev, "failed to get clock: %ld\n", 1969 PTR_ERR(wrp->clk_wrap)); 1970 return PTR_ERR(wrp->clk_wrap); 1971 } 1972 1973 ret = clk_prepare_enable(wrp->clk_spi); 1974 if (ret) 1975 return ret; 1976 1977 ret = clk_prepare_enable(wrp->clk_wrap); 1978 if (ret) 1979 goto err_out1; 1980 1981 /* Enable internal dynamic clock */ 1982 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) { 1983 pwrap_writel(wrp, 1, PWRAP_DCM_EN); 1984 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); 1985 } 1986 1987 /* 1988 * The PMIC could already be initialized by the bootloader. 1989 * Skip initialization here in this case. 1990 */ 1991 if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) { 1992 ret = pwrap_init(wrp); 1993 if (ret) { 1994 dev_dbg(wrp->dev, "init failed with %d\n", ret); 1995 goto err_out2; 1996 } 1997 } 1998 1999 if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) { 2000 dev_dbg(wrp->dev, "initialization isn't finished\n"); 2001 ret = -ENODEV; 2002 goto err_out2; 2003 } 2004 2005 /* Initialize watchdog, may not be done by the bootloader */ 2006 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT); 2007 /* 2008 * Since STAUPD was not used on mt8173 platform, 2009 * so STAUPD of WDT_SRC which should be turned off 2010 */ 2011 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN); 2012 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1)) 2013 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1); 2014 2015 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN); 2016 pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN); 2017 /* 2018 * We add INT1 interrupt to handle starvation and request exception 2019 * If we support it, we should enable it here. 2020 */ 2021 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) 2022 pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN); 2023 2024 irq = platform_get_irq(pdev, 0); 2025 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, 2026 IRQF_TRIGGER_HIGH, 2027 "mt-pmic-pwrap", wrp); 2028 if (ret) 2029 goto err_out2; 2030 2031 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap); 2032 if (IS_ERR(wrp->regmap)) { 2033 ret = PTR_ERR(wrp->regmap); 2034 goto err_out2; 2035 } 2036 2037 ret = of_platform_populate(np, NULL, NULL, wrp->dev); 2038 if (ret) { 2039 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n", 2040 np); 2041 goto err_out2; 2042 } 2043 2044 return 0; 2045 2046 err_out2: 2047 clk_disable_unprepare(wrp->clk_wrap); 2048 err_out1: 2049 clk_disable_unprepare(wrp->clk_spi); 2050 2051 return ret; 2052 } 2053 2054 static struct platform_driver pwrap_drv = { 2055 .driver = { 2056 .name = "mt-pmic-pwrap", 2057 .of_match_table = of_match_ptr(of_pwrap_match_tbl), 2058 }, 2059 .probe = pwrap_probe, 2060 }; 2061 2062 module_platform_driver(pwrap_drv); 2063 2064 MODULE_AUTHOR("Flora Fu, MediaTek"); 2065 MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver"); 2066 MODULE_LICENSE("GPL v2"); 2067