1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/iopoll.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 #include <linux/soc/mediatek/mtk-mmsys.h> 13 #include <linux/soc/mediatek/mtk-mutex.h> 14 #include <linux/soc/mediatek/mtk-cmdq.h> 15 16 #define MTK_MUTEX_MAX_HANDLES 10 17 18 #define MT2701_MUTEX0_MOD0 0x2c 19 #define MT2701_MUTEX0_SOF0 0x30 20 #define MT8183_MUTEX0_MOD0 0x30 21 #define MT8183_MUTEX0_SOF0 0x2c 22 23 #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) 24 #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) 25 #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) 26 #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n)) 27 #define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n) ((mutex_mod_reg) + 0x20 * (n) + 0x4) 28 #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n)) 29 #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) 30 31 #define INT_MUTEX BIT(1) 32 33 #define MT8186_MUTEX_MOD_DISP_OVL0 0 34 #define MT8186_MUTEX_MOD_DISP_OVL0_2L 1 35 #define MT8186_MUTEX_MOD_DISP_RDMA0 2 36 #define MT8186_MUTEX_MOD_DISP_COLOR0 4 37 #define MT8186_MUTEX_MOD_DISP_CCORR0 5 38 #define MT8186_MUTEX_MOD_DISP_AAL0 7 39 #define MT8186_MUTEX_MOD_DISP_GAMMA0 8 40 #define MT8186_MUTEX_MOD_DISP_POSTMASK0 9 41 #define MT8186_MUTEX_MOD_DISP_DITHER0 10 42 #define MT8186_MUTEX_MOD_DISP_RDMA1 17 43 44 #define MT8186_MUTEX_SOF_SINGLE_MODE 0 45 #define MT8186_MUTEX_SOF_DSI0 1 46 #define MT8186_MUTEX_SOF_DPI0 2 47 #define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6) 48 #define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6) 49 50 #define MT8167_MUTEX_MOD_DISP_PWM 1 51 #define MT8167_MUTEX_MOD_DISP_OVL0 6 52 #define MT8167_MUTEX_MOD_DISP_OVL1 7 53 #define MT8167_MUTEX_MOD_DISP_RDMA0 8 54 #define MT8167_MUTEX_MOD_DISP_RDMA1 9 55 #define MT8167_MUTEX_MOD_DISP_WDMA0 10 56 #define MT8167_MUTEX_MOD_DISP_CCORR 11 57 #define MT8167_MUTEX_MOD_DISP_COLOR 12 58 #define MT8167_MUTEX_MOD_DISP_AAL 13 59 #define MT8167_MUTEX_MOD_DISP_GAMMA 14 60 #define MT8167_MUTEX_MOD_DISP_DITHER 15 61 #define MT8167_MUTEX_MOD_DISP_UFOE 16 62 63 #define MT8192_MUTEX_MOD_DISP_OVL0 0 64 #define MT8192_MUTEX_MOD_DISP_OVL0_2L 1 65 #define MT8192_MUTEX_MOD_DISP_RDMA0 2 66 #define MT8192_MUTEX_MOD_DISP_COLOR0 4 67 #define MT8192_MUTEX_MOD_DISP_CCORR0 5 68 #define MT8192_MUTEX_MOD_DISP_AAL0 6 69 #define MT8192_MUTEX_MOD_DISP_GAMMA0 7 70 #define MT8192_MUTEX_MOD_DISP_POSTMASK0 8 71 #define MT8192_MUTEX_MOD_DISP_DITHER0 9 72 #define MT8192_MUTEX_MOD_DISP_OVL2_2L 16 73 #define MT8192_MUTEX_MOD_DISP_RDMA4 17 74 75 #define MT8183_MUTEX_MOD_DISP_RDMA0 0 76 #define MT8183_MUTEX_MOD_DISP_RDMA1 1 77 #define MT8183_MUTEX_MOD_DISP_OVL0 9 78 #define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 79 #define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 80 #define MT8183_MUTEX_MOD_DISP_WDMA0 12 81 #define MT8183_MUTEX_MOD_DISP_COLOR0 13 82 #define MT8183_MUTEX_MOD_DISP_CCORR0 14 83 #define MT8183_MUTEX_MOD_DISP_AAL0 15 84 #define MT8183_MUTEX_MOD_DISP_GAMMA0 16 85 #define MT8183_MUTEX_MOD_DISP_DITHER0 17 86 87 #define MT8183_MUTEX_MOD_MDP_RDMA0 2 88 #define MT8183_MUTEX_MOD_MDP_RSZ0 4 89 #define MT8183_MUTEX_MOD_MDP_RSZ1 5 90 #define MT8183_MUTEX_MOD_MDP_TDSHP0 6 91 #define MT8183_MUTEX_MOD_MDP_WROT0 7 92 #define MT8183_MUTEX_MOD_MDP_WDMA 8 93 #define MT8183_MUTEX_MOD_MDP_AAL0 23 94 #define MT8183_MUTEX_MOD_MDP_CCORR0 24 95 96 #define MT8186_MUTEX_MOD_MDP_RDMA0 0 97 #define MT8186_MUTEX_MOD_MDP_AAL0 2 98 #define MT8186_MUTEX_MOD_MDP_HDR0 4 99 #define MT8186_MUTEX_MOD_MDP_RSZ0 5 100 #define MT8186_MUTEX_MOD_MDP_RSZ1 6 101 #define MT8186_MUTEX_MOD_MDP_WROT0 7 102 #define MT8186_MUTEX_MOD_MDP_TDSHP0 9 103 #define MT8186_MUTEX_MOD_MDP_COLOR0 14 104 105 #define MT8173_MUTEX_MOD_DISP_OVL0 11 106 #define MT8173_MUTEX_MOD_DISP_OVL1 12 107 #define MT8173_MUTEX_MOD_DISP_RDMA0 13 108 #define MT8173_MUTEX_MOD_DISP_RDMA1 14 109 #define MT8173_MUTEX_MOD_DISP_RDMA2 15 110 #define MT8173_MUTEX_MOD_DISP_WDMA0 16 111 #define MT8173_MUTEX_MOD_DISP_WDMA1 17 112 #define MT8173_MUTEX_MOD_DISP_COLOR0 18 113 #define MT8173_MUTEX_MOD_DISP_COLOR1 19 114 #define MT8173_MUTEX_MOD_DISP_AAL 20 115 #define MT8173_MUTEX_MOD_DISP_GAMMA 21 116 #define MT8173_MUTEX_MOD_DISP_UFOE 22 117 #define MT8173_MUTEX_MOD_DISP_PWM0 23 118 #define MT8173_MUTEX_MOD_DISP_PWM1 24 119 #define MT8173_MUTEX_MOD_DISP_OD 25 120 121 #define MT8188_MUTEX_MOD_DISP_OVL0 0 122 #define MT8188_MUTEX_MOD_DISP_WDMA0 1 123 #define MT8188_MUTEX_MOD_DISP_RDMA0 2 124 #define MT8188_MUTEX_MOD_DISP_COLOR0 3 125 #define MT8188_MUTEX_MOD_DISP_CCORR0 4 126 #define MT8188_MUTEX_MOD_DISP_AAL0 5 127 #define MT8188_MUTEX_MOD_DISP_GAMMA0 6 128 #define MT8188_MUTEX_MOD_DISP_DITHER0 7 129 #define MT8188_MUTEX_MOD_DISP_DSI0 8 130 #define MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 131 #define MT8188_MUTEX_MOD_DISP_VPP_MERGE 20 132 #define MT8188_MUTEX_MOD_DISP_DP_INTF0 21 133 #define MT8188_MUTEX_MOD_DISP_POSTMASK0 24 134 #define MT8188_MUTEX_MOD2_DISP_PWM0 33 135 136 #define MT8195_MUTEX_MOD_DISP_OVL0 0 137 #define MT8195_MUTEX_MOD_DISP_WDMA0 1 138 #define MT8195_MUTEX_MOD_DISP_RDMA0 2 139 #define MT8195_MUTEX_MOD_DISP_COLOR0 3 140 #define MT8195_MUTEX_MOD_DISP_CCORR0 4 141 #define MT8195_MUTEX_MOD_DISP_AAL0 5 142 #define MT8195_MUTEX_MOD_DISP_GAMMA0 6 143 #define MT8195_MUTEX_MOD_DISP_DITHER0 7 144 #define MT8195_MUTEX_MOD_DISP_DSI0 8 145 #define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 146 #define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20 147 #define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 148 #define MT8195_MUTEX_MOD_DISP_PWM0 27 149 150 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 0 151 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 1 152 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 2 153 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 3 154 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 4 155 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 5 156 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 6 157 #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 7 158 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 8 159 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 9 160 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 10 161 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 11 162 #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 12 163 #define MT8195_MUTEX_MOD_DISP1_DISP_MIXER 18 164 #define MT8195_MUTEX_MOD_DISP1_DPI0 25 165 #define MT8195_MUTEX_MOD_DISP1_DPI1 26 166 #define MT8195_MUTEX_MOD_DISP1_DP_INTF0 27 167 168 /* VPPSYS0 */ 169 #define MT8195_MUTEX_MOD_MDP_RDMA0 0 170 #define MT8195_MUTEX_MOD_MDP_FG0 1 171 #define MT8195_MUTEX_MOD_MDP_STITCH0 2 172 #define MT8195_MUTEX_MOD_MDP_HDR0 3 173 #define MT8195_MUTEX_MOD_MDP_AAL0 4 174 #define MT8195_MUTEX_MOD_MDP_RSZ0 5 175 #define MT8195_MUTEX_MOD_MDP_TDSHP0 6 176 #define MT8195_MUTEX_MOD_MDP_COLOR0 7 177 #define MT8195_MUTEX_MOD_MDP_OVL0 8 178 #define MT8195_MUTEX_MOD_MDP_PAD0 9 179 #define MT8195_MUTEX_MOD_MDP_TCC0 10 180 #define MT8195_MUTEX_MOD_MDP_WROT0 11 181 182 /* VPPSYS1 */ 183 #define MT8195_MUTEX_MOD_MDP_TCC1 3 184 #define MT8195_MUTEX_MOD_MDP_RDMA1 4 185 #define MT8195_MUTEX_MOD_MDP_RDMA2 5 186 #define MT8195_MUTEX_MOD_MDP_RDMA3 6 187 #define MT8195_MUTEX_MOD_MDP_FG1 7 188 #define MT8195_MUTEX_MOD_MDP_FG2 8 189 #define MT8195_MUTEX_MOD_MDP_FG3 9 190 #define MT8195_MUTEX_MOD_MDP_HDR1 10 191 #define MT8195_MUTEX_MOD_MDP_HDR2 11 192 #define MT8195_MUTEX_MOD_MDP_HDR3 12 193 #define MT8195_MUTEX_MOD_MDP_AAL1 13 194 #define MT8195_MUTEX_MOD_MDP_AAL2 14 195 #define MT8195_MUTEX_MOD_MDP_AAL3 15 196 #define MT8195_MUTEX_MOD_MDP_RSZ1 16 197 #define MT8195_MUTEX_MOD_MDP_RSZ2 17 198 #define MT8195_MUTEX_MOD_MDP_RSZ3 18 199 #define MT8195_MUTEX_MOD_MDP_TDSHP1 19 200 #define MT8195_MUTEX_MOD_MDP_TDSHP2 20 201 #define MT8195_MUTEX_MOD_MDP_TDSHP3 21 202 #define MT8195_MUTEX_MOD_MDP_MERGE2 22 203 #define MT8195_MUTEX_MOD_MDP_MERGE3 23 204 #define MT8195_MUTEX_MOD_MDP_COLOR1 24 205 #define MT8195_MUTEX_MOD_MDP_COLOR2 25 206 #define MT8195_MUTEX_MOD_MDP_COLOR3 26 207 #define MT8195_MUTEX_MOD_MDP_OVL1 27 208 #define MT8195_MUTEX_MOD_MDP_PAD1 28 209 #define MT8195_MUTEX_MOD_MDP_PAD2 29 210 #define MT8195_MUTEX_MOD_MDP_PAD3 30 211 #define MT8195_MUTEX_MOD_MDP_WROT1 31 212 #define MT8195_MUTEX_MOD_MDP_WROT2 32 213 #define MT8195_MUTEX_MOD_MDP_WROT3 33 214 215 #define MT8365_MUTEX_MOD_DISP_OVL0 7 216 #define MT8365_MUTEX_MOD_DISP_OVL0_2L 8 217 #define MT8365_MUTEX_MOD_DISP_RDMA0 9 218 #define MT8365_MUTEX_MOD_DISP_RDMA1 10 219 #define MT8365_MUTEX_MOD_DISP_WDMA0 11 220 #define MT8365_MUTEX_MOD_DISP_COLOR0 12 221 #define MT8365_MUTEX_MOD_DISP_CCORR 13 222 #define MT8365_MUTEX_MOD_DISP_AAL 14 223 #define MT8365_MUTEX_MOD_DISP_GAMMA 15 224 #define MT8365_MUTEX_MOD_DISP_DITHER 16 225 #define MT8365_MUTEX_MOD_DISP_DSI0 17 226 #define MT8365_MUTEX_MOD_DISP_PWM0 20 227 #define MT8365_MUTEX_MOD_DISP_DPI0 22 228 229 #define MT2712_MUTEX_MOD_DISP_PWM2 10 230 #define MT2712_MUTEX_MOD_DISP_OVL0 11 231 #define MT2712_MUTEX_MOD_DISP_OVL1 12 232 #define MT2712_MUTEX_MOD_DISP_RDMA0 13 233 #define MT2712_MUTEX_MOD_DISP_RDMA1 14 234 #define MT2712_MUTEX_MOD_DISP_RDMA2 15 235 #define MT2712_MUTEX_MOD_DISP_WDMA0 16 236 #define MT2712_MUTEX_MOD_DISP_WDMA1 17 237 #define MT2712_MUTEX_MOD_DISP_COLOR0 18 238 #define MT2712_MUTEX_MOD_DISP_COLOR1 19 239 #define MT2712_MUTEX_MOD_DISP_AAL0 20 240 #define MT2712_MUTEX_MOD_DISP_UFOE 22 241 #define MT2712_MUTEX_MOD_DISP_PWM0 23 242 #define MT2712_MUTEX_MOD_DISP_PWM1 24 243 #define MT2712_MUTEX_MOD_DISP_OD0 25 244 #define MT2712_MUTEX_MOD2_DISP_AAL1 33 245 #define MT2712_MUTEX_MOD2_DISP_OD1 34 246 247 #define MT2701_MUTEX_MOD_DISP_OVL 3 248 #define MT2701_MUTEX_MOD_DISP_WDMA 6 249 #define MT2701_MUTEX_MOD_DISP_COLOR 7 250 #define MT2701_MUTEX_MOD_DISP_BLS 9 251 #define MT2701_MUTEX_MOD_DISP_RDMA0 10 252 #define MT2701_MUTEX_MOD_DISP_RDMA1 12 253 254 #define MT2712_MUTEX_SOF_SINGLE_MODE 0 255 #define MT2712_MUTEX_SOF_DSI0 1 256 #define MT2712_MUTEX_SOF_DSI1 2 257 #define MT2712_MUTEX_SOF_DPI0 3 258 #define MT2712_MUTEX_SOF_DPI1 4 259 #define MT2712_MUTEX_SOF_DSI2 5 260 #define MT2712_MUTEX_SOF_DSI3 6 261 #define MT8167_MUTEX_SOF_DPI0 2 262 #define MT8167_MUTEX_SOF_DPI1 3 263 #define MT8183_MUTEX_SOF_DSI0 1 264 #define MT8183_MUTEX_SOF_DPI0 2 265 #define MT8188_MUTEX_SOF_DSI0 1 266 #define MT8188_MUTEX_SOF_DP_INTF0 3 267 #define MT8195_MUTEX_SOF_DSI0 1 268 #define MT8195_MUTEX_SOF_DSI1 2 269 #define MT8195_MUTEX_SOF_DP_INTF0 3 270 #define MT8195_MUTEX_SOF_DP_INTF1 4 271 #define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */ 272 #define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */ 273 274 #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) 275 #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) 276 #define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7) 277 #define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7) 278 #define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7) 279 #define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7) 280 #define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7) 281 #define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7) 282 #define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7) 283 #define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7) 284 285 struct mtk_mutex { 286 u8 id; 287 bool claimed; 288 }; 289 290 enum mtk_mutex_sof_id { 291 MUTEX_SOF_SINGLE_MODE, 292 MUTEX_SOF_DSI0, 293 MUTEX_SOF_DSI1, 294 MUTEX_SOF_DPI0, 295 MUTEX_SOF_DPI1, 296 MUTEX_SOF_DSI2, 297 MUTEX_SOF_DSI3, 298 MUTEX_SOF_DP_INTF0, 299 MUTEX_SOF_DP_INTF1, 300 DDP_MUTEX_SOF_MAX, 301 }; 302 303 struct mtk_mutex_data { 304 const unsigned int *mutex_mod; 305 const unsigned int *mutex_sof; 306 const unsigned int mutex_mod_reg; 307 const unsigned int mutex_sof_reg; 308 const unsigned int *mutex_table_mod; 309 const bool no_clk; 310 }; 311 312 struct mtk_mutex_ctx { 313 struct device *dev; 314 struct clk *clk; 315 void __iomem *regs; 316 struct mtk_mutex mutex[MTK_MUTEX_MAX_HANDLES]; 317 const struct mtk_mutex_data *data; 318 phys_addr_t addr; 319 struct cmdq_client_reg cmdq_reg; 320 }; 321 322 static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { 323 [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, 324 [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, 325 [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, 326 [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0, 327 [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1, 328 [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, 329 }; 330 331 static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { 332 [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, 333 [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, 334 [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, 335 [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, 336 [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, 337 [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, 338 [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, 339 [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, 340 [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, 341 [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, 342 [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, 343 [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, 344 [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, 345 [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, 346 [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, 347 [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, 348 [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, 349 }; 350 351 static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { 352 [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL, 353 [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR, 354 [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR, 355 [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER, 356 [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA, 357 [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0, 358 [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1, 359 [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM, 360 [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0, 361 [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1, 362 [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE, 363 [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0, 364 }; 365 366 static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { 367 [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, 368 [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, 369 [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, 370 [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, 371 [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, 372 [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, 373 [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, 374 [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, 375 [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1, 376 [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0, 377 [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1, 378 [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2, 379 [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE, 380 [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0, 381 [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, 382 }; 383 384 static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { 385 [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, 386 [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, 387 [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, 388 [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0, 389 [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, 390 [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, 391 [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, 392 [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, 393 [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, 394 [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, 395 [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, 396 }; 397 398 static const unsigned int mt8183_mutex_table_mod[MUTEX_MOD_IDX_MAX] = { 399 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0, 400 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0, 401 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1, 402 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0, 403 [MUTEX_MOD_IDX_MDP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0, 404 [MUTEX_MOD_IDX_MDP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA, 405 [MUTEX_MOD_IDX_MDP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0, 406 [MUTEX_MOD_IDX_MDP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0, 407 }; 408 409 static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = { 410 [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0, 411 [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0, 412 [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0, 413 [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0, 414 [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0, 415 [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0, 416 [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L, 417 [DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0, 418 [DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0, 419 [DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1, 420 }; 421 422 static const unsigned int mt8186_mdp_mutex_table_mod[MUTEX_MOD_IDX_MAX] = { 423 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8186_MUTEX_MOD_MDP_RDMA0, 424 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8186_MUTEX_MOD_MDP_RSZ0, 425 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8186_MUTEX_MOD_MDP_RSZ1, 426 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8186_MUTEX_MOD_MDP_TDSHP0, 427 [MUTEX_MOD_IDX_MDP_WROT0] = MT8186_MUTEX_MOD_MDP_WROT0, 428 [MUTEX_MOD_IDX_MDP_HDR0] = MT8186_MUTEX_MOD_MDP_HDR0, 429 [MUTEX_MOD_IDX_MDP_AAL0] = MT8186_MUTEX_MOD_MDP_AAL0, 430 [MUTEX_MOD_IDX_MDP_COLOR0] = MT8186_MUTEX_MOD_MDP_COLOR0, 431 }; 432 433 static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = { 434 [DDP_COMPONENT_OVL0] = MT8188_MUTEX_MOD_DISP_OVL0, 435 [DDP_COMPONENT_WDMA0] = MT8188_MUTEX_MOD_DISP_WDMA0, 436 [DDP_COMPONENT_RDMA0] = MT8188_MUTEX_MOD_DISP_RDMA0, 437 [DDP_COMPONENT_COLOR0] = MT8188_MUTEX_MOD_DISP_COLOR0, 438 [DDP_COMPONENT_CCORR] = MT8188_MUTEX_MOD_DISP_CCORR0, 439 [DDP_COMPONENT_AAL0] = MT8188_MUTEX_MOD_DISP_AAL0, 440 [DDP_COMPONENT_GAMMA] = MT8188_MUTEX_MOD_DISP_GAMMA0, 441 [DDP_COMPONENT_POSTMASK0] = MT8188_MUTEX_MOD_DISP_POSTMASK0, 442 [DDP_COMPONENT_DITHER0] = MT8188_MUTEX_MOD_DISP_DITHER0, 443 [DDP_COMPONENT_MERGE0] = MT8188_MUTEX_MOD_DISP_VPP_MERGE, 444 [DDP_COMPONENT_DSC0] = MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0, 445 [DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0, 446 [DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0, 447 [DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0, 448 }; 449 450 static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { 451 [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0, 452 [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0, 453 [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0, 454 [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0, 455 [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0, 456 [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0, 457 [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0, 458 [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L, 459 [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L, 460 [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0, 461 [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4, 462 }; 463 464 static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { 465 [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0, 466 [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0, 467 [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0, 468 [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0, 469 [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0, 470 [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0, 471 [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0, 472 [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0, 473 [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE, 474 [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0, 475 [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, 476 [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, 477 [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, 478 [DDP_COMPONENT_MDP_RDMA0] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0, 479 [DDP_COMPONENT_MDP_RDMA1] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA1, 480 [DDP_COMPONENT_MDP_RDMA2] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA2, 481 [DDP_COMPONENT_MDP_RDMA3] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA3, 482 [DDP_COMPONENT_MDP_RDMA4] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA4, 483 [DDP_COMPONENT_MDP_RDMA5] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA5, 484 [DDP_COMPONENT_MDP_RDMA6] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA6, 485 [DDP_COMPONENT_MDP_RDMA7] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA7, 486 [DDP_COMPONENT_MERGE1] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE0, 487 [DDP_COMPONENT_MERGE2] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE1, 488 [DDP_COMPONENT_MERGE3] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE2, 489 [DDP_COMPONENT_MERGE4] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE3, 490 [DDP_COMPONENT_ETHDR_MIXER] = MT8195_MUTEX_MOD_DISP1_DISP_MIXER, 491 [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4, 492 [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0, 493 }; 494 495 static const unsigned int mt8195_mutex_table_mod[MUTEX_MOD_IDX_MAX] = { 496 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8195_MUTEX_MOD_MDP_RDMA0, 497 [MUTEX_MOD_IDX_MDP_RDMA1] = MT8195_MUTEX_MOD_MDP_RDMA1, 498 [MUTEX_MOD_IDX_MDP_RDMA2] = MT8195_MUTEX_MOD_MDP_RDMA2, 499 [MUTEX_MOD_IDX_MDP_RDMA3] = MT8195_MUTEX_MOD_MDP_RDMA3, 500 [MUTEX_MOD_IDX_MDP_STITCH0] = MT8195_MUTEX_MOD_MDP_STITCH0, 501 [MUTEX_MOD_IDX_MDP_FG0] = MT8195_MUTEX_MOD_MDP_FG0, 502 [MUTEX_MOD_IDX_MDP_FG1] = MT8195_MUTEX_MOD_MDP_FG1, 503 [MUTEX_MOD_IDX_MDP_FG2] = MT8195_MUTEX_MOD_MDP_FG2, 504 [MUTEX_MOD_IDX_MDP_FG3] = MT8195_MUTEX_MOD_MDP_FG3, 505 [MUTEX_MOD_IDX_MDP_HDR0] = MT8195_MUTEX_MOD_MDP_HDR0, 506 [MUTEX_MOD_IDX_MDP_HDR1] = MT8195_MUTEX_MOD_MDP_HDR1, 507 [MUTEX_MOD_IDX_MDP_HDR2] = MT8195_MUTEX_MOD_MDP_HDR2, 508 [MUTEX_MOD_IDX_MDP_HDR3] = MT8195_MUTEX_MOD_MDP_HDR3, 509 [MUTEX_MOD_IDX_MDP_AAL0] = MT8195_MUTEX_MOD_MDP_AAL0, 510 [MUTEX_MOD_IDX_MDP_AAL1] = MT8195_MUTEX_MOD_MDP_AAL1, 511 [MUTEX_MOD_IDX_MDP_AAL2] = MT8195_MUTEX_MOD_MDP_AAL2, 512 [MUTEX_MOD_IDX_MDP_AAL3] = MT8195_MUTEX_MOD_MDP_AAL3, 513 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8195_MUTEX_MOD_MDP_RSZ0, 514 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8195_MUTEX_MOD_MDP_RSZ1, 515 [MUTEX_MOD_IDX_MDP_RSZ2] = MT8195_MUTEX_MOD_MDP_RSZ2, 516 [MUTEX_MOD_IDX_MDP_RSZ3] = MT8195_MUTEX_MOD_MDP_RSZ3, 517 [MUTEX_MOD_IDX_MDP_MERGE2] = MT8195_MUTEX_MOD_MDP_MERGE2, 518 [MUTEX_MOD_IDX_MDP_MERGE3] = MT8195_MUTEX_MOD_MDP_MERGE3, 519 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8195_MUTEX_MOD_MDP_TDSHP0, 520 [MUTEX_MOD_IDX_MDP_TDSHP1] = MT8195_MUTEX_MOD_MDP_TDSHP1, 521 [MUTEX_MOD_IDX_MDP_TDSHP2] = MT8195_MUTEX_MOD_MDP_TDSHP2, 522 [MUTEX_MOD_IDX_MDP_TDSHP3] = MT8195_MUTEX_MOD_MDP_TDSHP3, 523 [MUTEX_MOD_IDX_MDP_COLOR0] = MT8195_MUTEX_MOD_MDP_COLOR0, 524 [MUTEX_MOD_IDX_MDP_COLOR1] = MT8195_MUTEX_MOD_MDP_COLOR1, 525 [MUTEX_MOD_IDX_MDP_COLOR2] = MT8195_MUTEX_MOD_MDP_COLOR2, 526 [MUTEX_MOD_IDX_MDP_COLOR3] = MT8195_MUTEX_MOD_MDP_COLOR3, 527 [MUTEX_MOD_IDX_MDP_OVL0] = MT8195_MUTEX_MOD_MDP_OVL0, 528 [MUTEX_MOD_IDX_MDP_OVL1] = MT8195_MUTEX_MOD_MDP_OVL1, 529 [MUTEX_MOD_IDX_MDP_PAD0] = MT8195_MUTEX_MOD_MDP_PAD0, 530 [MUTEX_MOD_IDX_MDP_PAD1] = MT8195_MUTEX_MOD_MDP_PAD1, 531 [MUTEX_MOD_IDX_MDP_PAD2] = MT8195_MUTEX_MOD_MDP_PAD2, 532 [MUTEX_MOD_IDX_MDP_PAD3] = MT8195_MUTEX_MOD_MDP_PAD3, 533 [MUTEX_MOD_IDX_MDP_TCC0] = MT8195_MUTEX_MOD_MDP_TCC0, 534 [MUTEX_MOD_IDX_MDP_TCC1] = MT8195_MUTEX_MOD_MDP_TCC1, 535 [MUTEX_MOD_IDX_MDP_WROT0] = MT8195_MUTEX_MOD_MDP_WROT0, 536 [MUTEX_MOD_IDX_MDP_WROT1] = MT8195_MUTEX_MOD_MDP_WROT1, 537 [MUTEX_MOD_IDX_MDP_WROT2] = MT8195_MUTEX_MOD_MDP_WROT2, 538 [MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3, 539 }; 540 541 static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = { 542 [DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL, 543 [DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR, 544 [DDP_COMPONENT_COLOR0] = MT8365_MUTEX_MOD_DISP_COLOR0, 545 [DDP_COMPONENT_DITHER0] = MT8365_MUTEX_MOD_DISP_DITHER, 546 [DDP_COMPONENT_DPI0] = MT8365_MUTEX_MOD_DISP_DPI0, 547 [DDP_COMPONENT_DSI0] = MT8365_MUTEX_MOD_DISP_DSI0, 548 [DDP_COMPONENT_GAMMA] = MT8365_MUTEX_MOD_DISP_GAMMA, 549 [DDP_COMPONENT_OVL0] = MT8365_MUTEX_MOD_DISP_OVL0, 550 [DDP_COMPONENT_OVL_2L0] = MT8365_MUTEX_MOD_DISP_OVL0_2L, 551 [DDP_COMPONENT_PWM0] = MT8365_MUTEX_MOD_DISP_PWM0, 552 [DDP_COMPONENT_RDMA0] = MT8365_MUTEX_MOD_DISP_RDMA0, 553 [DDP_COMPONENT_RDMA1] = MT8365_MUTEX_MOD_DISP_RDMA1, 554 [DDP_COMPONENT_WDMA0] = MT8365_MUTEX_MOD_DISP_WDMA0, 555 }; 556 557 static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { 558 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 559 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, 560 [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, 561 [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, 562 [MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1, 563 [MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2, 564 [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, 565 }; 566 567 static const unsigned int mt6795_mutex_sof[DDP_MUTEX_SOF_MAX] = { 568 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 569 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, 570 [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, 571 [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, 572 }; 573 574 static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = { 575 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 576 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, 577 [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0, 578 [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, 579 }; 580 581 /* Add EOF setting so overlay hardware can receive frame done irq */ 582 static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = { 583 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 584 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, 585 [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, 586 }; 587 588 static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = { 589 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 590 [MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0, 591 [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0, 592 }; 593 594 /* 595 * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should 596 * select the EOF source and configure the EOF plus timing from the 597 * module that provides the timing signal. 598 * So that MUTEX can not only send a STREAM_DONE event to GCE 599 * but also detect the error at end of frame(EAEOF) when EOF signal 600 * arrives. 601 */ 602 static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = { 603 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 604 [MUTEX_SOF_DSI0] = 605 MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0, 606 [MUTEX_SOF_DP_INTF0] = 607 MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0, 608 }; 609 610 static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = { 611 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, 612 [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0, 613 [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1, 614 [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0, 615 [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1, 616 [MUTEX_SOF_DP_INTF0] = 617 MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0, 618 [MUTEX_SOF_DP_INTF1] = 619 MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1, 620 }; 621 622 static const struct mtk_mutex_data mt2701_mutex_driver_data = { 623 .mutex_mod = mt2701_mutex_mod, 624 .mutex_sof = mt2712_mutex_sof, 625 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 626 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 627 }; 628 629 static const struct mtk_mutex_data mt2712_mutex_driver_data = { 630 .mutex_mod = mt2712_mutex_mod, 631 .mutex_sof = mt2712_mutex_sof, 632 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 633 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 634 }; 635 636 static const struct mtk_mutex_data mt6795_mutex_driver_data = { 637 .mutex_mod = mt8173_mutex_mod, 638 .mutex_sof = mt6795_mutex_sof, 639 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 640 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 641 }; 642 643 static const struct mtk_mutex_data mt8167_mutex_driver_data = { 644 .mutex_mod = mt8167_mutex_mod, 645 .mutex_sof = mt8167_mutex_sof, 646 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 647 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 648 .no_clk = true, 649 }; 650 651 static const struct mtk_mutex_data mt8173_mutex_driver_data = { 652 .mutex_mod = mt8173_mutex_mod, 653 .mutex_sof = mt2712_mutex_sof, 654 .mutex_mod_reg = MT2701_MUTEX0_MOD0, 655 .mutex_sof_reg = MT2701_MUTEX0_SOF0, 656 }; 657 658 static const struct mtk_mutex_data mt8183_mutex_driver_data = { 659 .mutex_mod = mt8183_mutex_mod, 660 .mutex_sof = mt8183_mutex_sof, 661 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 662 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 663 .mutex_table_mod = mt8183_mutex_table_mod, 664 .no_clk = true, 665 }; 666 667 static const struct mtk_mutex_data mt8186_mdp_mutex_driver_data = { 668 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 669 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 670 .mutex_table_mod = mt8186_mdp_mutex_table_mod, 671 }; 672 673 static const struct mtk_mutex_data mt8186_mutex_driver_data = { 674 .mutex_mod = mt8186_mutex_mod, 675 .mutex_sof = mt8186_mutex_sof, 676 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 677 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 678 }; 679 680 static const struct mtk_mutex_data mt8188_mutex_driver_data = { 681 .mutex_mod = mt8188_mutex_mod, 682 .mutex_sof = mt8188_mutex_sof, 683 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 684 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 685 }; 686 687 static const struct mtk_mutex_data mt8192_mutex_driver_data = { 688 .mutex_mod = mt8192_mutex_mod, 689 .mutex_sof = mt8183_mutex_sof, 690 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 691 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 692 }; 693 694 static const struct mtk_mutex_data mt8195_mutex_driver_data = { 695 .mutex_mod = mt8195_mutex_mod, 696 .mutex_sof = mt8195_mutex_sof, 697 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 698 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 699 }; 700 701 static const struct mtk_mutex_data mt8195_vpp_mutex_driver_data = { 702 .mutex_sof = mt8195_mutex_sof, 703 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 704 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 705 .mutex_table_mod = mt8195_mutex_table_mod, 706 }; 707 708 static const struct mtk_mutex_data mt8365_mutex_driver_data = { 709 .mutex_mod = mt8365_mutex_mod, 710 .mutex_sof = mt8183_mutex_sof, 711 .mutex_mod_reg = MT8183_MUTEX0_MOD0, 712 .mutex_sof_reg = MT8183_MUTEX0_SOF0, 713 .no_clk = true, 714 }; 715 716 struct mtk_mutex *mtk_mutex_get(struct device *dev) 717 { 718 struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); 719 int i; 720 721 for (i = 0; i < MTK_MUTEX_MAX_HANDLES; i++) 722 if (!mtx->mutex[i].claimed) { 723 mtx->mutex[i].claimed = true; 724 return &mtx->mutex[i]; 725 } 726 727 return ERR_PTR(-EBUSY); 728 } 729 EXPORT_SYMBOL_GPL(mtk_mutex_get); 730 731 void mtk_mutex_put(struct mtk_mutex *mutex) 732 { 733 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 734 mutex[mutex->id]); 735 736 WARN_ON(&mtx->mutex[mutex->id] != mutex); 737 738 mutex->claimed = false; 739 } 740 EXPORT_SYMBOL_GPL(mtk_mutex_put); 741 742 int mtk_mutex_prepare(struct mtk_mutex *mutex) 743 { 744 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 745 mutex[mutex->id]); 746 return clk_prepare_enable(mtx->clk); 747 } 748 EXPORT_SYMBOL_GPL(mtk_mutex_prepare); 749 750 void mtk_mutex_unprepare(struct mtk_mutex *mutex) 751 { 752 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 753 mutex[mutex->id]); 754 clk_disable_unprepare(mtx->clk); 755 } 756 EXPORT_SYMBOL_GPL(mtk_mutex_unprepare); 757 758 void mtk_mutex_add_comp(struct mtk_mutex *mutex, 759 enum mtk_ddp_comp_id id) 760 { 761 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 762 mutex[mutex->id]); 763 unsigned int reg; 764 unsigned int sof_id; 765 unsigned int offset; 766 767 WARN_ON(&mtx->mutex[mutex->id] != mutex); 768 769 switch (id) { 770 case DDP_COMPONENT_DSI0: 771 sof_id = MUTEX_SOF_DSI0; 772 break; 773 case DDP_COMPONENT_DSI1: 774 sof_id = MUTEX_SOF_DSI0; 775 break; 776 case DDP_COMPONENT_DSI2: 777 sof_id = MUTEX_SOF_DSI2; 778 break; 779 case DDP_COMPONENT_DSI3: 780 sof_id = MUTEX_SOF_DSI3; 781 break; 782 case DDP_COMPONENT_DPI0: 783 sof_id = MUTEX_SOF_DPI0; 784 break; 785 case DDP_COMPONENT_DPI1: 786 sof_id = MUTEX_SOF_DPI1; 787 break; 788 case DDP_COMPONENT_DP_INTF0: 789 sof_id = MUTEX_SOF_DP_INTF0; 790 break; 791 case DDP_COMPONENT_DP_INTF1: 792 sof_id = MUTEX_SOF_DP_INTF1; 793 break; 794 default: 795 if (mtx->data->mutex_mod[id] < 32) { 796 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, 797 mutex->id); 798 reg = readl_relaxed(mtx->regs + offset); 799 reg |= 1 << mtx->data->mutex_mod[id]; 800 writel_relaxed(reg, mtx->regs + offset); 801 } else { 802 offset = DISP_REG_MUTEX_MOD2(mutex->id); 803 reg = readl_relaxed(mtx->regs + offset); 804 reg |= 1 << (mtx->data->mutex_mod[id] - 32); 805 writel_relaxed(reg, mtx->regs + offset); 806 } 807 return; 808 } 809 810 writel_relaxed(mtx->data->mutex_sof[sof_id], 811 mtx->regs + 812 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); 813 } 814 EXPORT_SYMBOL_GPL(mtk_mutex_add_comp); 815 816 void mtk_mutex_remove_comp(struct mtk_mutex *mutex, 817 enum mtk_ddp_comp_id id) 818 { 819 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 820 mutex[mutex->id]); 821 unsigned int reg; 822 unsigned int offset; 823 824 WARN_ON(&mtx->mutex[mutex->id] != mutex); 825 826 switch (id) { 827 case DDP_COMPONENT_DSI0: 828 case DDP_COMPONENT_DSI1: 829 case DDP_COMPONENT_DSI2: 830 case DDP_COMPONENT_DSI3: 831 case DDP_COMPONENT_DPI0: 832 case DDP_COMPONENT_DPI1: 833 case DDP_COMPONENT_DP_INTF0: 834 case DDP_COMPONENT_DP_INTF1: 835 writel_relaxed(MUTEX_SOF_SINGLE_MODE, 836 mtx->regs + 837 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, 838 mutex->id)); 839 break; 840 default: 841 if (mtx->data->mutex_mod[id] < 32) { 842 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, 843 mutex->id); 844 reg = readl_relaxed(mtx->regs + offset); 845 reg &= ~(1 << mtx->data->mutex_mod[id]); 846 writel_relaxed(reg, mtx->regs + offset); 847 } else { 848 offset = DISP_REG_MUTEX_MOD2(mutex->id); 849 reg = readl_relaxed(mtx->regs + offset); 850 reg &= ~(1 << (mtx->data->mutex_mod[id] - 32)); 851 writel_relaxed(reg, mtx->regs + offset); 852 } 853 break; 854 } 855 } 856 EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp); 857 858 void mtk_mutex_enable(struct mtk_mutex *mutex) 859 { 860 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 861 mutex[mutex->id]); 862 863 WARN_ON(&mtx->mutex[mutex->id] != mutex); 864 865 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); 866 } 867 EXPORT_SYMBOL_GPL(mtk_mutex_enable); 868 869 int mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex, void *pkt) 870 { 871 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 872 mutex[mutex->id]); 873 struct cmdq_pkt *cmdq_pkt = (struct cmdq_pkt *)pkt; 874 875 WARN_ON(&mtx->mutex[mutex->id] != mutex); 876 877 if (!mtx->cmdq_reg.size) { 878 dev_err(mtx->dev, "mediatek,gce-client-reg hasn't been set"); 879 return -ENODEV; 880 } 881 882 cmdq_pkt_write(cmdq_pkt, mtx->cmdq_reg.subsys, 883 mtx->addr + DISP_REG_MUTEX_EN(mutex->id), 1); 884 return 0; 885 } 886 EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq); 887 888 void mtk_mutex_disable(struct mtk_mutex *mutex) 889 { 890 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 891 mutex[mutex->id]); 892 893 WARN_ON(&mtx->mutex[mutex->id] != mutex); 894 895 writel(0, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); 896 } 897 EXPORT_SYMBOL_GPL(mtk_mutex_disable); 898 899 void mtk_mutex_acquire(struct mtk_mutex *mutex) 900 { 901 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 902 mutex[mutex->id]); 903 u32 tmp; 904 905 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); 906 writel(1, mtx->regs + DISP_REG_MUTEX(mutex->id)); 907 if (readl_poll_timeout_atomic(mtx->regs + DISP_REG_MUTEX(mutex->id), 908 tmp, tmp & INT_MUTEX, 1, 10000)) 909 pr_err("could not acquire mutex %d\n", mutex->id); 910 } 911 EXPORT_SYMBOL_GPL(mtk_mutex_acquire); 912 913 void mtk_mutex_release(struct mtk_mutex *mutex) 914 { 915 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 916 mutex[mutex->id]); 917 918 writel(0, mtx->regs + DISP_REG_MUTEX(mutex->id)); 919 } 920 EXPORT_SYMBOL_GPL(mtk_mutex_release); 921 922 int mtk_mutex_write_mod(struct mtk_mutex *mutex, 923 enum mtk_mutex_mod_index idx, bool clear) 924 { 925 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 926 mutex[mutex->id]); 927 unsigned int reg; 928 u32 reg_offset, id_offset = 0; 929 930 WARN_ON(&mtx->mutex[mutex->id] != mutex); 931 932 if (idx < MUTEX_MOD_IDX_MDP_RDMA0 || 933 idx >= MUTEX_MOD_IDX_MAX) { 934 dev_err(mtx->dev, "Not supported MOD table index : %d", idx); 935 return -EINVAL; 936 } 937 938 /* 939 * Some SoCs may have multiple MUTEX_MOD registers as more than 32 mods 940 * are present, hence requiring multiple 32-bits registers. 941 * 942 * The mutex_table_mod fully represents that by defining the number of 943 * the mod sequentially, later used as a bit number, which can be more 944 * than 0..31. 945 * 946 * In order to retain compatibility with older SoCs, we perform R/W on 947 * the single 32 bits registers, but this requires us to translate the 948 * mutex ID bit accordingly. 949 */ 950 if (mtx->data->mutex_table_mod[idx] < 32) { 951 reg_offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, 952 mutex->id); 953 } else { 954 reg_offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg, 955 mutex->id); 956 id_offset = 32; 957 } 958 959 reg = readl_relaxed(mtx->regs + reg_offset); 960 if (clear) 961 reg &= ~BIT(mtx->data->mutex_table_mod[idx] - id_offset); 962 else 963 reg |= BIT(mtx->data->mutex_table_mod[idx] - id_offset); 964 965 writel_relaxed(reg, mtx->regs + reg_offset); 966 967 return 0; 968 } 969 EXPORT_SYMBOL_GPL(mtk_mutex_write_mod); 970 971 int mtk_mutex_write_sof(struct mtk_mutex *mutex, 972 enum mtk_mutex_sof_index idx) 973 { 974 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, 975 mutex[mutex->id]); 976 977 WARN_ON(&mtx->mutex[mutex->id] != mutex); 978 979 if (idx < MUTEX_SOF_IDX_SINGLE_MODE || 980 idx >= MUTEX_SOF_IDX_MAX) { 981 dev_err(mtx->dev, "Not supported SOF index : %d", idx); 982 return -EINVAL; 983 } 984 985 writel_relaxed(idx, mtx->regs + 986 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); 987 988 return 0; 989 } 990 EXPORT_SYMBOL_GPL(mtk_mutex_write_sof); 991 992 static int mtk_mutex_probe(struct platform_device *pdev) 993 { 994 struct device *dev = &pdev->dev; 995 struct mtk_mutex_ctx *mtx; 996 struct resource *regs; 997 int i, ret; 998 999 mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL); 1000 if (!mtx) 1001 return -ENOMEM; 1002 1003 for (i = 0; i < MTK_MUTEX_MAX_HANDLES; i++) 1004 mtx->mutex[i].id = i; 1005 1006 mtx->data = of_device_get_match_data(dev); 1007 1008 if (!mtx->data->no_clk) { 1009 mtx->clk = devm_clk_get(dev, NULL); 1010 if (IS_ERR(mtx->clk)) 1011 return dev_err_probe(dev, PTR_ERR(mtx->clk), "Failed to get clock\n"); 1012 } 1013 1014 mtx->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); 1015 if (IS_ERR(mtx->regs)) { 1016 dev_err(dev, "Failed to map mutex registers\n"); 1017 return PTR_ERR(mtx->regs); 1018 } 1019 mtx->addr = regs->start; 1020 1021 /* CMDQ is optional */ 1022 ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0); 1023 if (ret) 1024 dev_dbg(dev, "No mediatek,gce-client-reg!\n"); 1025 1026 platform_set_drvdata(pdev, mtx); 1027 1028 return 0; 1029 } 1030 1031 static const struct of_device_id mutex_driver_dt_match[] = { 1032 { .compatible = "mediatek,mt2701-disp-mutex", .data = &mt2701_mutex_driver_data }, 1033 { .compatible = "mediatek,mt2712-disp-mutex", .data = &mt2712_mutex_driver_data }, 1034 { .compatible = "mediatek,mt6795-disp-mutex", .data = &mt6795_mutex_driver_data }, 1035 { .compatible = "mediatek,mt8167-disp-mutex", .data = &mt8167_mutex_driver_data }, 1036 { .compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_mutex_driver_data }, 1037 { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data }, 1038 { .compatible = "mediatek,mt8186-disp-mutex", .data = &mt8186_mutex_driver_data }, 1039 { .compatible = "mediatek,mt8186-mdp3-mutex", .data = &mt8186_mdp_mutex_driver_data }, 1040 { .compatible = "mediatek,mt8188-disp-mutex", .data = &mt8188_mutex_driver_data }, 1041 { .compatible = "mediatek,mt8192-disp-mutex", .data = &mt8192_mutex_driver_data }, 1042 { .compatible = "mediatek,mt8195-disp-mutex", .data = &mt8195_mutex_driver_data }, 1043 { .compatible = "mediatek,mt8195-vpp-mutex", .data = &mt8195_vpp_mutex_driver_data }, 1044 { .compatible = "mediatek,mt8365-disp-mutex", .data = &mt8365_mutex_driver_data }, 1045 { /* sentinel */ }, 1046 }; 1047 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); 1048 1049 static struct platform_driver mtk_mutex_driver = { 1050 .probe = mtk_mutex_probe, 1051 .driver = { 1052 .name = "mediatek-mutex", 1053 .of_match_table = mutex_driver_dt_match, 1054 }, 1055 }; 1056 module_platform_driver(mtk_mutex_driver); 1057 1058 MODULE_AUTHOR("Yongqiang Niu <yongqiang.niu@mediatek.com>"); 1059 MODULE_DESCRIPTION("MediaTek SoC MUTEX driver"); 1060 MODULE_LICENSE("GPL"); 1061