1*44014763SCK Hu /* SPDX-License-Identifier: GPL-2.0-only */ 2*44014763SCK Hu 3*44014763SCK Hu #ifndef __SOC_MEDIATEK_MTK_MMSYS_H 4*44014763SCK Hu #define __SOC_MEDIATEK_MTK_MMSYS_H 5*44014763SCK Hu 6*44014763SCK Hu #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 7*44014763SCK Hu #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 8*44014763SCK Hu #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 9*44014763SCK Hu #define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c 10*44014763SCK Hu #define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 11*44014763SCK Hu #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 12*44014763SCK Hu #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 13*44014763SCK Hu #define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 14*44014763SCK Hu #define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 15*44014763SCK Hu #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac 16*44014763SCK Hu #define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 17*44014763SCK Hu #define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 18*44014763SCK Hu #define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 19*44014763SCK Hu #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 20*44014763SCK Hu 21*44014763SCK Hu #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 22*44014763SCK Hu #define DISP_REG_CONFIG_OUT_SEL 0x04c 23*44014763SCK Hu #define DISP_REG_CONFIG_DSI_SEL 0x050 24*44014763SCK Hu #define DISP_REG_CONFIG_DPI_SEL 0x064 25*44014763SCK Hu 26*44014763SCK Hu #define OVL0_MOUT_EN_COLOR0 0x1 27*44014763SCK Hu #define OD_MOUT_EN_RDMA0 0x1 28*44014763SCK Hu #define OD1_MOUT_EN_RDMA1 BIT(16) 29*44014763SCK Hu #define UFOE_MOUT_EN_DSI0 0x1 30*44014763SCK Hu #define COLOR0_SEL_IN_OVL0 0x1 31*44014763SCK Hu #define OVL1_MOUT_EN_COLOR1 0x1 32*44014763SCK Hu #define GAMMA_MOUT_EN_RDMA1 0x1 33*44014763SCK Hu #define RDMA0_SOUT_DPI0 0x2 34*44014763SCK Hu #define RDMA0_SOUT_DPI1 0x3 35*44014763SCK Hu #define RDMA0_SOUT_DSI1 0x1 36*44014763SCK Hu #define RDMA0_SOUT_DSI2 0x4 37*44014763SCK Hu #define RDMA0_SOUT_DSI3 0x5 38*44014763SCK Hu #define RDMA1_SOUT_DPI0 0x2 39*44014763SCK Hu #define RDMA1_SOUT_DPI1 0x3 40*44014763SCK Hu #define RDMA1_SOUT_DSI1 0x1 41*44014763SCK Hu #define RDMA1_SOUT_DSI2 0x4 42*44014763SCK Hu #define RDMA1_SOUT_DSI3 0x5 43*44014763SCK Hu #define RDMA2_SOUT_DPI0 0x2 44*44014763SCK Hu #define RDMA2_SOUT_DPI1 0x3 45*44014763SCK Hu #define RDMA2_SOUT_DSI1 0x1 46*44014763SCK Hu #define RDMA2_SOUT_DSI2 0x4 47*44014763SCK Hu #define RDMA2_SOUT_DSI3 0x5 48*44014763SCK Hu #define DPI0_SEL_IN_RDMA1 0x1 49*44014763SCK Hu #define DPI0_SEL_IN_RDMA2 0x3 50*44014763SCK Hu #define DPI1_SEL_IN_RDMA1 (0x1 << 8) 51*44014763SCK Hu #define DPI1_SEL_IN_RDMA2 (0x3 << 8) 52*44014763SCK Hu #define DSI0_SEL_IN_RDMA1 0x1 53*44014763SCK Hu #define DSI0_SEL_IN_RDMA2 0x4 54*44014763SCK Hu #define DSI1_SEL_IN_RDMA1 0x1 55*44014763SCK Hu #define DSI1_SEL_IN_RDMA2 0x4 56*44014763SCK Hu #define DSI2_SEL_IN_RDMA1 (0x1 << 16) 57*44014763SCK Hu #define DSI2_SEL_IN_RDMA2 (0x4 << 16) 58*44014763SCK Hu #define DSI3_SEL_IN_RDMA1 (0x1 << 16) 59*44014763SCK Hu #define DSI3_SEL_IN_RDMA2 (0x4 << 16) 60*44014763SCK Hu #define COLOR1_SEL_IN_OVL1 0x1 61*44014763SCK Hu 62*44014763SCK Hu #define OVL_MOUT_EN_RDMA 0x1 63*44014763SCK Hu #define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 64*44014763SCK Hu #define BLS_TO_DPI_RDMA1_TO_DSI 0x2 65*44014763SCK Hu #define DSI_SEL_IN_BLS 0x0 66*44014763SCK Hu #define DPI_SEL_IN_BLS 0x0 67*44014763SCK Hu #define DSI_SEL_IN_RDMA 0x1 68*44014763SCK Hu 69*44014763SCK Hu struct mtk_mmsys_routes { 70*44014763SCK Hu u32 from_comp; 71*44014763SCK Hu u32 to_comp; 72*44014763SCK Hu u32 addr; 73*44014763SCK Hu u32 val; 74*44014763SCK Hu }; 75*44014763SCK Hu 76*44014763SCK Hu struct mtk_mmsys_driver_data { 77*44014763SCK Hu const char *clk_driver; 78*44014763SCK Hu const struct mtk_mmsys_routes *routes; 79*44014763SCK Hu const unsigned int num_routes; 80*44014763SCK Hu }; 81*44014763SCK Hu 82*44014763SCK Hu /* 83*44014763SCK Hu * Routes in mt8173, mt2701, mt2712 are different. That means 84*44014763SCK Hu * in the same register address, it controls different input/output 85*44014763SCK Hu * selection for each SoC. But, right now, they use the same table as 86*44014763SCK Hu * default routes meet their requirements. But we don't have the complete 87*44014763SCK Hu * route information for these three SoC, so just keep them in the same 88*44014763SCK Hu * table. After we've more information, we could separate mt2701, mt2712 89*44014763SCK Hu * to an independent table. 90*44014763SCK Hu */ 91*44014763SCK Hu static const struct mtk_mmsys_routes mmsys_default_routing_table[] = { 92*44014763SCK Hu { 93*44014763SCK Hu DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0, 94*44014763SCK Hu DISP_REG_CONFIG_OUT_SEL, BLS_TO_DSI_RDMA1_TO_DPI1 95*44014763SCK Hu }, { 96*44014763SCK Hu DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0, 97*44014763SCK Hu DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_BLS 98*44014763SCK Hu }, { 99*44014763SCK Hu DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0, 100*44014763SCK Hu DISP_REG_CONFIG_OUT_SEL, BLS_TO_DPI_RDMA1_TO_DSI 101*44014763SCK Hu }, { 102*44014763SCK Hu DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0, 103*44014763SCK Hu DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_RDMA 104*44014763SCK Hu }, { 105*44014763SCK Hu DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0, 106*44014763SCK Hu DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_BLS 107*44014763SCK Hu }, { 108*44014763SCK Hu DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1, 109*44014763SCK Hu DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1 110*44014763SCK Hu }, { 111*44014763SCK Hu DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0, 112*44014763SCK Hu DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0 113*44014763SCK Hu }, { 114*44014763SCK Hu DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1, 115*44014763SCK Hu DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1 116*44014763SCK Hu }, { 117*44014763SCK Hu DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, 118*44014763SCK Hu DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0 119*44014763SCK Hu }, { 120*44014763SCK Hu DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, 121*44014763SCK Hu DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0 122*44014763SCK Hu }, { 123*44014763SCK Hu DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 124*44014763SCK Hu DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA 125*44014763SCK Hu }, { 126*44014763SCK Hu DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1, 127*44014763SCK Hu DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1 128*44014763SCK Hu }, { 129*44014763SCK Hu DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1, 130*44014763SCK Hu DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1 131*44014763SCK Hu }, { 132*44014763SCK Hu DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0, 133*44014763SCK Hu DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DPI0 134*44014763SCK Hu }, { 135*44014763SCK Hu DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1, 136*44014763SCK Hu DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DPI1 137*44014763SCK Hu }, { 138*44014763SCK Hu DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1, 139*44014763SCK Hu DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI1 140*44014763SCK Hu }, { 141*44014763SCK Hu DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2, 142*44014763SCK Hu DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI2 143*44014763SCK Hu }, { 144*44014763SCK Hu DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3, 145*44014763SCK Hu DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI3 146*44014763SCK Hu }, { 147*44014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, 148*44014763SCK Hu DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DPI0 149*44014763SCK Hu }, { 150*44014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, 151*44014763SCK Hu DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_RDMA1 152*44014763SCK Hu }, { 153*44014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1, 154*44014763SCK Hu DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DPI1 155*44014763SCK Hu }, { 156*44014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1, 157*44014763SCK Hu DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_RDMA1 158*44014763SCK Hu }, { 159*44014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0, 160*44014763SCK Hu DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_RDMA1 161*44014763SCK Hu }, { 162*44014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1, 163*44014763SCK Hu DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI1 164*44014763SCK Hu }, { 165*44014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1, 166*44014763SCK Hu DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_RDMA1 167*44014763SCK Hu }, { 168*44014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2, 169*44014763SCK Hu DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI2 170*44014763SCK Hu }, { 171*44014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2, 172*44014763SCK Hu DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_RDMA1 173*44014763SCK Hu }, { 174*44014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3, 175*44014763SCK Hu DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI3 176*44014763SCK Hu }, { 177*44014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3, 178*44014763SCK Hu DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_RDMA1 179*44014763SCK Hu }, { 180*44014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0, 181*44014763SCK Hu DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DPI0 182*44014763SCK Hu }, { 183*44014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0, 184*44014763SCK Hu DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_RDMA2 185*44014763SCK Hu }, { 186*44014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1, 187*44014763SCK Hu DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DPI1 188*44014763SCK Hu }, { 189*44014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1, 190*44014763SCK Hu DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_RDMA2 191*44014763SCK Hu }, { 192*44014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0, 193*44014763SCK Hu DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_RDMA2 194*44014763SCK Hu }, { 195*44014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1, 196*44014763SCK Hu DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI1 197*44014763SCK Hu }, { 198*44014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1, 199*44014763SCK Hu DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_RDMA2 200*44014763SCK Hu }, { 201*44014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2, 202*44014763SCK Hu DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI2 203*44014763SCK Hu }, { 204*44014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2, 205*44014763SCK Hu DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_RDMA2 206*44014763SCK Hu }, { 207*44014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3, 208*44014763SCK Hu DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI3 209*44014763SCK Hu }, { 210*44014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3, 211*44014763SCK Hu DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_RDMA2 212*44014763SCK Hu } 213*44014763SCK Hu }; 214*44014763SCK Hu 215*44014763SCK Hu #endif /* __SOC_MEDIATEK_MTK_MMSYS_H */ 216