144014763SCK Hu /* SPDX-License-Identifier: GPL-2.0-only */ 244014763SCK Hu 344014763SCK Hu #ifndef __SOC_MEDIATEK_MTK_MMSYS_H 444014763SCK Hu #define __SOC_MEDIATEK_MTK_MMSYS_H 544014763SCK Hu 644014763SCK Hu #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 744014763SCK Hu #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 844014763SCK Hu #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 944014763SCK Hu #define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c 1044014763SCK Hu #define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 1144014763SCK Hu #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 1244014763SCK Hu #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 1344014763SCK Hu #define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 1444014763SCK Hu #define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 1544014763SCK Hu #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac 1644014763SCK Hu #define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 1744014763SCK Hu #define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 1844014763SCK Hu #define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 1944014763SCK Hu #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 2044014763SCK Hu 2144014763SCK Hu #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 2244014763SCK Hu #define DISP_REG_CONFIG_OUT_SEL 0x04c 2344014763SCK Hu #define DISP_REG_CONFIG_DSI_SEL 0x050 2444014763SCK Hu #define DISP_REG_CONFIG_DPI_SEL 0x064 2544014763SCK Hu 2644014763SCK Hu #define OVL0_MOUT_EN_COLOR0 0x1 2744014763SCK Hu #define OD_MOUT_EN_RDMA0 0x1 2844014763SCK Hu #define OD1_MOUT_EN_RDMA1 BIT(16) 2944014763SCK Hu #define UFOE_MOUT_EN_DSI0 0x1 3044014763SCK Hu #define COLOR0_SEL_IN_OVL0 0x1 3144014763SCK Hu #define OVL1_MOUT_EN_COLOR1 0x1 3244014763SCK Hu #define GAMMA_MOUT_EN_RDMA1 0x1 3344014763SCK Hu #define RDMA0_SOUT_DPI0 0x2 3444014763SCK Hu #define RDMA0_SOUT_DPI1 0x3 3544014763SCK Hu #define RDMA0_SOUT_DSI1 0x1 3644014763SCK Hu #define RDMA0_SOUT_DSI2 0x4 3744014763SCK Hu #define RDMA0_SOUT_DSI3 0x5 387bdcead7SCK Hu #define RDMA0_SOUT_MASK 0x7 3944014763SCK Hu #define RDMA1_SOUT_DPI0 0x2 4044014763SCK Hu #define RDMA1_SOUT_DPI1 0x3 4144014763SCK Hu #define RDMA1_SOUT_DSI1 0x1 4244014763SCK Hu #define RDMA1_SOUT_DSI2 0x4 4344014763SCK Hu #define RDMA1_SOUT_DSI3 0x5 447bdcead7SCK Hu #define RDMA1_SOUT_MASK 0x7 4544014763SCK Hu #define RDMA2_SOUT_DPI0 0x2 4644014763SCK Hu #define RDMA2_SOUT_DPI1 0x3 4744014763SCK Hu #define RDMA2_SOUT_DSI1 0x1 4844014763SCK Hu #define RDMA2_SOUT_DSI2 0x4 4944014763SCK Hu #define RDMA2_SOUT_DSI3 0x5 507bdcead7SCK Hu #define RDMA2_SOUT_MASK 0x7 5144014763SCK Hu #define DPI0_SEL_IN_RDMA1 0x1 5244014763SCK Hu #define DPI0_SEL_IN_RDMA2 0x3 537bdcead7SCK Hu #define DPI0_SEL_IN_MASK 0x3 5444014763SCK Hu #define DPI1_SEL_IN_RDMA1 (0x1 << 8) 5544014763SCK Hu #define DPI1_SEL_IN_RDMA2 (0x3 << 8) 567bdcead7SCK Hu #define DPI1_SEL_IN_MASK (0x3 << 8) 5744014763SCK Hu #define DSI0_SEL_IN_RDMA1 0x1 5844014763SCK Hu #define DSI0_SEL_IN_RDMA2 0x4 597bdcead7SCK Hu #define DSI0_SEL_IN_MASK 0x7 6044014763SCK Hu #define DSI1_SEL_IN_RDMA1 0x1 6144014763SCK Hu #define DSI1_SEL_IN_RDMA2 0x4 627bdcead7SCK Hu #define DSI1_SEL_IN_MASK 0x7 6344014763SCK Hu #define DSI2_SEL_IN_RDMA1 (0x1 << 16) 6444014763SCK Hu #define DSI2_SEL_IN_RDMA2 (0x4 << 16) 657bdcead7SCK Hu #define DSI2_SEL_IN_MASK (0x7 << 16) 6644014763SCK Hu #define DSI3_SEL_IN_RDMA1 (0x1 << 16) 6744014763SCK Hu #define DSI3_SEL_IN_RDMA2 (0x4 << 16) 687bdcead7SCK Hu #define DSI3_SEL_IN_MASK (0x7 << 16) 6944014763SCK Hu #define COLOR1_SEL_IN_OVL1 0x1 7044014763SCK Hu 7144014763SCK Hu #define OVL_MOUT_EN_RDMA 0x1 7244014763SCK Hu #define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 7344014763SCK Hu #define BLS_TO_DPI_RDMA1_TO_DSI 0x2 747bdcead7SCK Hu #define BLS_RDMA1_DSI_DPI_MASK 0xf 7544014763SCK Hu #define DSI_SEL_IN_BLS 0x0 7644014763SCK Hu #define DPI_SEL_IN_BLS 0x0 777bdcead7SCK Hu #define DPI_SEL_IN_MASK 0x1 7844014763SCK Hu #define DSI_SEL_IN_RDMA 0x1 797bdcead7SCK Hu #define DSI_SEL_IN_MASK 0x1 8044014763SCK Hu 8144014763SCK Hu struct mtk_mmsys_routes { 8244014763SCK Hu u32 from_comp; 8344014763SCK Hu u32 to_comp; 8444014763SCK Hu u32 addr; 857bdcead7SCK Hu u32 mask; 8644014763SCK Hu u32 val; 8744014763SCK Hu }; 8844014763SCK Hu 8944014763SCK Hu struct mtk_mmsys_driver_data { 9044014763SCK Hu const char *clk_driver; 9144014763SCK Hu const struct mtk_mmsys_routes *routes; 9244014763SCK Hu const unsigned int num_routes; 9362dc3015SRex-BC Chen const u16 sw0_rst_offset; 94*2004f8beSNancy.Lin const u32 num_resets; 9544014763SCK Hu }; 9644014763SCK Hu 9744014763SCK Hu /* 9844014763SCK Hu * Routes in mt8173, mt2701, mt2712 are different. That means 9944014763SCK Hu * in the same register address, it controls different input/output 10044014763SCK Hu * selection for each SoC. But, right now, they use the same table as 10144014763SCK Hu * default routes meet their requirements. But we don't have the complete 10244014763SCK Hu * route information for these three SoC, so just keep them in the same 10344014763SCK Hu * table. After we've more information, we could separate mt2701, mt2712 10444014763SCK Hu * to an independent table. 10544014763SCK Hu */ 10644014763SCK Hu static const struct mtk_mmsys_routes mmsys_default_routing_table[] = { 10744014763SCK Hu { 10844014763SCK Hu DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0, 1097bdcead7SCK Hu DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK, 1107bdcead7SCK Hu BLS_TO_DSI_RDMA1_TO_DPI1 11144014763SCK Hu }, { 11244014763SCK Hu DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0, 1137bdcead7SCK Hu DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK, 1147bdcead7SCK Hu DSI_SEL_IN_BLS 11544014763SCK Hu }, { 11644014763SCK Hu DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0, 1177bdcead7SCK Hu DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK, 1187bdcead7SCK Hu BLS_TO_DPI_RDMA1_TO_DSI 11944014763SCK Hu }, { 12044014763SCK Hu DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0, 1217bdcead7SCK Hu DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK, 1227bdcead7SCK Hu DSI_SEL_IN_RDMA 12344014763SCK Hu }, { 12444014763SCK Hu DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0, 1257bdcead7SCK Hu DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK, 1267bdcead7SCK Hu DPI_SEL_IN_BLS 12744014763SCK Hu }, { 12844014763SCK Hu DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1, 1297bdcead7SCK Hu DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1, 1307bdcead7SCK Hu GAMMA_MOUT_EN_RDMA1 13144014763SCK Hu }, { 13244014763SCK Hu DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0, 1337bdcead7SCK Hu DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0, 1347bdcead7SCK Hu OD_MOUT_EN_RDMA0 13544014763SCK Hu }, { 13644014763SCK Hu DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1, 1377bdcead7SCK Hu DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1, 1387bdcead7SCK Hu OD1_MOUT_EN_RDMA1 13944014763SCK Hu }, { 14044014763SCK Hu DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, 1417bdcead7SCK Hu DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0, 1427bdcead7SCK Hu OVL0_MOUT_EN_COLOR0 14344014763SCK Hu }, { 14444014763SCK Hu DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, 1457bdcead7SCK Hu DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0, 1467bdcead7SCK Hu COLOR0_SEL_IN_OVL0 14744014763SCK Hu }, { 14844014763SCK Hu DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 1497bdcead7SCK Hu DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA, 1507bdcead7SCK Hu OVL_MOUT_EN_RDMA 15144014763SCK Hu }, { 15244014763SCK Hu DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1, 1537bdcead7SCK Hu DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1, 1547bdcead7SCK Hu OVL1_MOUT_EN_COLOR1 15544014763SCK Hu }, { 15644014763SCK Hu DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1, 1577bdcead7SCK Hu DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1, 1587bdcead7SCK Hu COLOR1_SEL_IN_OVL1 15944014763SCK Hu }, { 16044014763SCK Hu DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0, 1617bdcead7SCK Hu DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, 1627bdcead7SCK Hu RDMA0_SOUT_DPI0 16344014763SCK Hu }, { 16444014763SCK Hu DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1, 1657bdcead7SCK Hu DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, 1667bdcead7SCK Hu RDMA0_SOUT_DPI1 16744014763SCK Hu }, { 16844014763SCK Hu DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1, 1697bdcead7SCK Hu DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, 1707bdcead7SCK Hu RDMA0_SOUT_DSI1 17144014763SCK Hu }, { 17244014763SCK Hu DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2, 1737bdcead7SCK Hu DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, 1747bdcead7SCK Hu RDMA0_SOUT_DSI2 17544014763SCK Hu }, { 17644014763SCK Hu DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3, 1777bdcead7SCK Hu DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, 1787bdcead7SCK Hu RDMA0_SOUT_DSI3 17944014763SCK Hu }, { 18044014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, 1817bdcead7SCK Hu DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, 1827bdcead7SCK Hu RDMA1_SOUT_DPI0 18344014763SCK Hu }, { 18444014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, 1857bdcead7SCK Hu DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK, 1867bdcead7SCK Hu DPI0_SEL_IN_RDMA1 18744014763SCK Hu }, { 18844014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1, 1897bdcead7SCK Hu DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, 1907bdcead7SCK Hu RDMA1_SOUT_DPI1 19144014763SCK Hu }, { 19244014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1, 1937bdcead7SCK Hu DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK, 1947bdcead7SCK Hu DPI1_SEL_IN_RDMA1 19544014763SCK Hu }, { 19644014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0, 1977bdcead7SCK Hu DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK, 1987bdcead7SCK Hu DSI0_SEL_IN_RDMA1 19944014763SCK Hu }, { 20044014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1, 2017bdcead7SCK Hu DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, 2027bdcead7SCK Hu RDMA1_SOUT_DSI1 20344014763SCK Hu }, { 20444014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1, 2057bdcead7SCK Hu DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK, 2067bdcead7SCK Hu DSI1_SEL_IN_RDMA1 20744014763SCK Hu }, { 20844014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2, 2097bdcead7SCK Hu DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, 2107bdcead7SCK Hu RDMA1_SOUT_DSI2 21144014763SCK Hu }, { 21244014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2, 2137bdcead7SCK Hu DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK, 2147bdcead7SCK Hu DSI2_SEL_IN_RDMA1 21544014763SCK Hu }, { 21644014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3, 2177bdcead7SCK Hu DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, 2187bdcead7SCK Hu RDMA1_SOUT_DSI3 21944014763SCK Hu }, { 22044014763SCK Hu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3, 2217bdcead7SCK Hu DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK, 2227bdcead7SCK Hu DSI3_SEL_IN_RDMA1 22344014763SCK Hu }, { 22444014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0, 2257bdcead7SCK Hu DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, 2267bdcead7SCK Hu RDMA2_SOUT_DPI0 22744014763SCK Hu }, { 22844014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0, 2297bdcead7SCK Hu DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK, 2307bdcead7SCK Hu DPI0_SEL_IN_RDMA2 23144014763SCK Hu }, { 23244014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1, 2337bdcead7SCK Hu DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, 2347bdcead7SCK Hu RDMA2_SOUT_DPI1 23544014763SCK Hu }, { 23644014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1, 2377bdcead7SCK Hu DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK, 2387bdcead7SCK Hu DPI1_SEL_IN_RDMA2 23944014763SCK Hu }, { 24044014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0, 2417bdcead7SCK Hu DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK, 2427bdcead7SCK Hu DSI0_SEL_IN_RDMA2 24344014763SCK Hu }, { 24444014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1, 2457bdcead7SCK Hu DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, 2467bdcead7SCK Hu RDMA2_SOUT_DSI1 24744014763SCK Hu }, { 24844014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1, 2497bdcead7SCK Hu DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK, 2507bdcead7SCK Hu DSI1_SEL_IN_RDMA2 25144014763SCK Hu }, { 25244014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2, 2537bdcead7SCK Hu DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, 2547bdcead7SCK Hu RDMA2_SOUT_DSI2 25544014763SCK Hu }, { 25644014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2, 2577bdcead7SCK Hu DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK, 2587bdcead7SCK Hu DSI2_SEL_IN_RDMA2 25944014763SCK Hu }, { 26044014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3, 2617bdcead7SCK Hu DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, 2627bdcead7SCK Hu RDMA2_SOUT_DSI3 26344014763SCK Hu }, { 26444014763SCK Hu DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3, 2657bdcead7SCK Hu DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK, 2667bdcead7SCK Hu DSI3_SEL_IN_RDMA2 26725423731SEnric Balletbo i Serra }, { 26825423731SEnric Balletbo i Serra DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0, 26925423731SEnric Balletbo i Serra DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, UFOE_MOUT_EN_DSI0, 27025423731SEnric Balletbo i Serra UFOE_MOUT_EN_DSI0 27144014763SCK Hu } 27244014763SCK Hu }; 27344014763SCK Hu 27444014763SCK Hu #endif /* __SOC_MEDIATEK_MTK_MMSYS_H */ 275