1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: James Liao <jamesjj.liao@mediatek.com> 5 */ 6 7 #include <linux/delay.h> 8 #include <linux/device.h> 9 #include <linux/io.h> 10 #include <linux/of_device.h> 11 #include <linux/platform_device.h> 12 #include <linux/reset-controller.h> 13 #include <linux/soc/mediatek/mtk-mmsys.h> 14 15 #include "mtk-mmsys.h" 16 #include "mt8167-mmsys.h" 17 #include "mt8183-mmsys.h" 18 #include "mt8186-mmsys.h" 19 #include "mt8192-mmsys.h" 20 #include "mt8195-mmsys.h" 21 #include "mt8365-mmsys.h" 22 23 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 24 .clk_driver = "clk-mt2701-mm", 25 .routes = mmsys_default_routing_table, 26 .num_routes = ARRAY_SIZE(mmsys_default_routing_table), 27 }; 28 29 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 30 .clk_driver = "clk-mt2712-mm", 31 .routes = mmsys_default_routing_table, 32 .num_routes = ARRAY_SIZE(mmsys_default_routing_table), 33 }; 34 35 static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { 36 .clk_driver = "clk-mt6779-mm", 37 }; 38 39 static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { 40 .clk_driver = "clk-mt6797-mm", 41 }; 42 43 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 44 .clk_driver = "clk-mt8167-mm", 45 .routes = mt8167_mmsys_routing_table, 46 .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table), 47 }; 48 49 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 50 .clk_driver = "clk-mt8173-mm", 51 .routes = mmsys_default_routing_table, 52 .num_routes = ARRAY_SIZE(mmsys_default_routing_table), 53 .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, 54 }; 55 56 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 57 .clk_driver = "clk-mt8183-mm", 58 .routes = mmsys_mt8183_routing_table, 59 .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), 60 .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, 61 }; 62 63 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { 64 .clk_driver = "clk-mt8186-mm", 65 .routes = mmsys_mt8186_routing_table, 66 .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table), 67 .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, 68 }; 69 70 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { 71 .clk_driver = "clk-mt8192-mm", 72 .routes = mmsys_mt8192_routing_table, 73 .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), 74 .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, 75 }; 76 77 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { 78 .clk_driver = "clk-mt8195-vdo0", 79 .routes = mmsys_mt8195_routing_table, 80 .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), 81 }; 82 83 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { 84 .clk_driver = "clk-mt8365-mm", 85 .routes = mt8365_mmsys_routing_table, 86 .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table), 87 }; 88 89 struct mtk_mmsys { 90 void __iomem *regs; 91 const struct mtk_mmsys_driver_data *data; 92 spinlock_t lock; /* protects mmsys_sw_rst_b reg */ 93 struct reset_controller_dev rcdev; 94 }; 95 96 void mtk_mmsys_ddp_connect(struct device *dev, 97 enum mtk_ddp_comp_id cur, 98 enum mtk_ddp_comp_id next) 99 { 100 struct mtk_mmsys *mmsys = dev_get_drvdata(dev); 101 const struct mtk_mmsys_routes *routes = mmsys->data->routes; 102 u32 reg; 103 int i; 104 105 for (i = 0; i < mmsys->data->num_routes; i++) 106 if (cur == routes[i].from_comp && next == routes[i].to_comp) { 107 reg = readl_relaxed(mmsys->regs + routes[i].addr); 108 reg &= ~routes[i].mask; 109 reg |= routes[i].val; 110 writel_relaxed(reg, mmsys->regs + routes[i].addr); 111 } 112 } 113 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); 114 115 void mtk_mmsys_ddp_disconnect(struct device *dev, 116 enum mtk_ddp_comp_id cur, 117 enum mtk_ddp_comp_id next) 118 { 119 struct mtk_mmsys *mmsys = dev_get_drvdata(dev); 120 const struct mtk_mmsys_routes *routes = mmsys->data->routes; 121 u32 reg; 122 int i; 123 124 for (i = 0; i < mmsys->data->num_routes; i++) 125 if (cur == routes[i].from_comp && next == routes[i].to_comp) { 126 reg = readl_relaxed(mmsys->regs + routes[i].addr); 127 reg &= ~routes[i].mask; 128 writel_relaxed(reg, mmsys->regs + routes[i].addr); 129 } 130 } 131 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); 132 133 static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val) 134 { 135 u32 tmp; 136 137 tmp = readl_relaxed(mmsys->regs + offset); 138 tmp = (tmp & ~mask) | val; 139 writel_relaxed(tmp, mmsys->regs + offset); 140 } 141 142 void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val) 143 { 144 struct mtk_mmsys *mmsys = dev_get_drvdata(dev); 145 146 switch (val) { 147 case MTK_DPI_RGB888_SDR_CON: 148 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, 149 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_SDR_CON); 150 break; 151 case MTK_DPI_RGB565_SDR_CON: 152 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, 153 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_SDR_CON); 154 break; 155 case MTK_DPI_RGB565_DDR_CON: 156 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, 157 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_DDR_CON); 158 break; 159 case MTK_DPI_RGB888_DDR_CON: 160 default: 161 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, 162 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_DDR_CON); 163 break; 164 } 165 } 166 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config); 167 168 static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id, 169 bool assert) 170 { 171 struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev); 172 unsigned long flags; 173 u32 reg; 174 175 spin_lock_irqsave(&mmsys->lock, flags); 176 177 reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset); 178 179 if (assert) 180 reg &= ~BIT(id); 181 else 182 reg |= BIT(id); 183 184 writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset); 185 186 spin_unlock_irqrestore(&mmsys->lock, flags); 187 188 return 0; 189 } 190 191 static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 192 { 193 return mtk_mmsys_reset_update(rcdev, id, true); 194 } 195 196 static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 197 { 198 return mtk_mmsys_reset_update(rcdev, id, false); 199 } 200 201 static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id) 202 { 203 int ret; 204 205 ret = mtk_mmsys_reset_assert(rcdev, id); 206 if (ret) 207 return ret; 208 209 usleep_range(1000, 1100); 210 211 return mtk_mmsys_reset_deassert(rcdev, id); 212 } 213 214 static const struct reset_control_ops mtk_mmsys_reset_ops = { 215 .assert = mtk_mmsys_reset_assert, 216 .deassert = mtk_mmsys_reset_deassert, 217 .reset = mtk_mmsys_reset, 218 }; 219 220 static int mtk_mmsys_probe(struct platform_device *pdev) 221 { 222 struct device *dev = &pdev->dev; 223 struct platform_device *clks; 224 struct platform_device *drm; 225 struct mtk_mmsys *mmsys; 226 int ret; 227 228 mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); 229 if (!mmsys) 230 return -ENOMEM; 231 232 mmsys->regs = devm_platform_ioremap_resource(pdev, 0); 233 if (IS_ERR(mmsys->regs)) { 234 ret = PTR_ERR(mmsys->regs); 235 dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret); 236 return ret; 237 } 238 239 spin_lock_init(&mmsys->lock); 240 241 mmsys->rcdev.owner = THIS_MODULE; 242 mmsys->rcdev.nr_resets = 32; 243 mmsys->rcdev.ops = &mtk_mmsys_reset_ops; 244 mmsys->rcdev.of_node = pdev->dev.of_node; 245 ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev); 246 if (ret) { 247 dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret); 248 return ret; 249 } 250 251 mmsys->data = of_device_get_match_data(&pdev->dev); 252 platform_set_drvdata(pdev, mmsys); 253 254 clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, 255 PLATFORM_DEVID_AUTO, NULL, 0); 256 if (IS_ERR(clks)) 257 return PTR_ERR(clks); 258 259 drm = platform_device_register_data(&pdev->dev, "mediatek-drm", 260 PLATFORM_DEVID_AUTO, NULL, 0); 261 if (IS_ERR(drm)) { 262 platform_device_unregister(clks); 263 return PTR_ERR(drm); 264 } 265 266 return 0; 267 } 268 269 static const struct of_device_id of_match_mtk_mmsys[] = { 270 { 271 .compatible = "mediatek,mt2701-mmsys", 272 .data = &mt2701_mmsys_driver_data, 273 }, 274 { 275 .compatible = "mediatek,mt2712-mmsys", 276 .data = &mt2712_mmsys_driver_data, 277 }, 278 { 279 .compatible = "mediatek,mt6779-mmsys", 280 .data = &mt6779_mmsys_driver_data, 281 }, 282 { 283 .compatible = "mediatek,mt6797-mmsys", 284 .data = &mt6797_mmsys_driver_data, 285 }, 286 { 287 .compatible = "mediatek,mt8167-mmsys", 288 .data = &mt8167_mmsys_driver_data, 289 }, 290 { 291 .compatible = "mediatek,mt8173-mmsys", 292 .data = &mt8173_mmsys_driver_data, 293 }, 294 { 295 .compatible = "mediatek,mt8183-mmsys", 296 .data = &mt8183_mmsys_driver_data, 297 }, 298 { 299 .compatible = "mediatek,mt8186-mmsys", 300 .data = &mt8186_mmsys_driver_data, 301 }, 302 { 303 .compatible = "mediatek,mt8192-mmsys", 304 .data = &mt8192_mmsys_driver_data, 305 }, 306 { /* deprecated compatible */ 307 .compatible = "mediatek,mt8195-mmsys", 308 .data = &mt8195_vdosys0_driver_data, 309 }, 310 { 311 .compatible = "mediatek,mt8195-vdosys0", 312 .data = &mt8195_vdosys0_driver_data, 313 }, 314 { 315 .compatible = "mediatek,mt8365-mmsys", 316 .data = &mt8365_mmsys_driver_data, 317 }, 318 { } 319 }; 320 321 static struct platform_driver mtk_mmsys_drv = { 322 .driver = { 323 .name = "mtk-mmsys", 324 .of_match_table = of_match_mtk_mmsys, 325 }, 326 .probe = mtk_mmsys_probe, 327 }; 328 329 builtin_platform_driver(mtk_mmsys_drv); 330