113032709SMatthias Brugger // SPDX-License-Identifier: GPL-2.0-only 213032709SMatthias Brugger /* 313032709SMatthias Brugger * Copyright (c) 2014 MediaTek Inc. 413032709SMatthias Brugger * Author: James Liao <jamesjj.liao@mediatek.com> 513032709SMatthias Brugger */ 613032709SMatthias Brugger 7f27ef285SEnric Balletbo i Serra #include <linux/delay.h> 82c758e30SEnric Balletbo i Serra #include <linux/device.h> 951c0e618SYongqiang Niu #include <linux/io.h> 10a7596e62SYongqiang Niu #include <linux/module.h> 1113032709SMatthias Brugger #include <linux/of_device.h> 1213032709SMatthias Brugger #include <linux/platform_device.h> 13f27ef285SEnric Balletbo i Serra #include <linux/reset-controller.h> 142c758e30SEnric Balletbo i Serra #include <linux/soc/mediatek/mtk-mmsys.h> 152c758e30SEnric Balletbo i Serra 1644014763SCK Hu #include "mtk-mmsys.h" 17060f7875SFabien Parent #include "mt8167-mmsys.h" 181ff1270fSHsin-Yi Wang #include "mt8183-mmsys.h" 195f9b5b75SYongqiang Niu #include "mt8186-mmsys.h" 203b1a57c4SNathan Lu #include "mt8188-mmsys.h" 21d687e056SYongqiang Niu #include "mt8192-mmsys.h" 22b2b99a7aSJason-JH.Lin #include "mt8195-mmsys.h" 23bc3fc5c0SFabien Parent #include "mt8365-mmsys.h" 2413032709SMatthias Brugger 252004f8beSNancy.Lin #define MMSYS_SW_RESET_PER_REG 32 262004f8beSNancy.Lin 27c292b133SEnric Balletbo i Serra static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 28c292b133SEnric Balletbo i Serra .clk_driver = "clk-mt2701-mm", 2944014763SCK Hu .routes = mmsys_default_routing_table, 3044014763SCK Hu .num_routes = ARRAY_SIZE(mmsys_default_routing_table), 31c292b133SEnric Balletbo i Serra }; 32c292b133SEnric Balletbo i Serra 339c5a0a3aSEnric Balletbo i Serra static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 349c5a0a3aSEnric Balletbo i Serra .clk_driver = "clk-mt2712-mm", 3544014763SCK Hu .routes = mmsys_default_routing_table, 3644014763SCK Hu .num_routes = ARRAY_SIZE(mmsys_default_routing_table), 379c5a0a3aSEnric Balletbo i Serra }; 389c5a0a3aSEnric Balletbo i Serra 3932956ddaSMatthias Brugger static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { 4032956ddaSMatthias Brugger .clk_driver = "clk-mt6779-mm", 4132956ddaSMatthias Brugger }; 4232956ddaSMatthias Brugger 43cad4e379SMatthias Brugger static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { 44cad4e379SMatthias Brugger .clk_driver = "clk-mt6797-mm", 45cad4e379SMatthias Brugger }; 46cad4e379SMatthias Brugger 47060f7875SFabien Parent static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 48060f7875SFabien Parent .clk_driver = "clk-mt8167-mm", 49060f7875SFabien Parent .routes = mt8167_mmsys_routing_table, 50060f7875SFabien Parent .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table), 51060f7875SFabien Parent }; 52060f7875SFabien Parent 5313032709SMatthias Brugger static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 5413032709SMatthias Brugger .clk_driver = "clk-mt8173-mm", 5544014763SCK Hu .routes = mmsys_default_routing_table, 5644014763SCK Hu .num_routes = ARRAY_SIZE(mmsys_default_routing_table), 5762dc3015SRex-BC Chen .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, 582004f8beSNancy.Lin .num_resets = 32, 5913032709SMatthias Brugger }; 6013032709SMatthias Brugger 611f9adbc7SMatthias Brugger static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 621f9adbc7SMatthias Brugger .clk_driver = "clk-mt8183-mm", 631ff1270fSHsin-Yi Wang .routes = mmsys_mt8183_routing_table, 641ff1270fSHsin-Yi Wang .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), 6562dc3015SRex-BC Chen .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, 662004f8beSNancy.Lin .num_resets = 32, 671f9adbc7SMatthias Brugger }; 681f9adbc7SMatthias Brugger 695f9b5b75SYongqiang Niu static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { 705f9b5b75SYongqiang Niu .clk_driver = "clk-mt8186-mm", 715f9b5b75SYongqiang Niu .routes = mmsys_mt8186_routing_table, 725f9b5b75SYongqiang Niu .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table), 73831785f0SRex-BC Chen .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, 742004f8beSNancy.Lin .num_resets = 32, 755f9b5b75SYongqiang Niu }; 765f9b5b75SYongqiang Niu 773b1a57c4SNathan Lu static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { 783b1a57c4SNathan Lu .clk_driver = "clk-mt8188-vdo0", 793b1a57c4SNathan Lu .routes = mmsys_mt8188_routing_table, 803b1a57c4SNathan Lu .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table), 813b1a57c4SNathan Lu }; 823b1a57c4SNathan Lu 83d687e056SYongqiang Niu static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { 84d687e056SYongqiang Niu .clk_driver = "clk-mt8192-mm", 85d687e056SYongqiang Niu .routes = mmsys_mt8192_routing_table, 86d687e056SYongqiang Niu .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), 879d7370a5SAngeloGioacchino Del Regno .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, 882004f8beSNancy.Lin .num_resets = 32, 89d687e056SYongqiang Niu }; 90d687e056SYongqiang Niu 91b2b99a7aSJason-JH.Lin static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { 92b2b99a7aSJason-JH.Lin .clk_driver = "clk-mt8195-vdo0", 93b2b99a7aSJason-JH.Lin .routes = mmsys_mt8195_routing_table, 94b2b99a7aSJason-JH.Lin .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), 95b2b99a7aSJason-JH.Lin }; 96b2b99a7aSJason-JH.Lin 9739170127SNancy.Lin static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { 9839170127SNancy.Lin .clk_driver = "clk-mt8195-vdo1", 9939170127SNancy.Lin .routes = mmsys_mt8195_vdo1_routing_table, 10039170127SNancy.Lin .num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table), 1017f0a38f4SNancy.Lin .sw0_rst_offset = MT8195_VDO1_SW0_RST_B, 1027f0a38f4SNancy.Lin .num_resets = 64, 10339170127SNancy.Lin }; 10439170127SNancy.Lin 105*78ce3093SRoy-CW.Yeh static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = { 106*78ce3093SRoy-CW.Yeh .clk_driver = "clk-mt8195-vpp0", 107*78ce3093SRoy-CW.Yeh .is_vppsys = true, 108*78ce3093SRoy-CW.Yeh }; 109*78ce3093SRoy-CW.Yeh 110*78ce3093SRoy-CW.Yeh static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = { 111*78ce3093SRoy-CW.Yeh .clk_driver = "clk-mt8195-vpp1", 112*78ce3093SRoy-CW.Yeh .is_vppsys = true, 113*78ce3093SRoy-CW.Yeh }; 114*78ce3093SRoy-CW.Yeh 115bc3fc5c0SFabien Parent static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { 116bc3fc5c0SFabien Parent .clk_driver = "clk-mt8365-mm", 117bc3fc5c0SFabien Parent .routes = mt8365_mmsys_routing_table, 118bc3fc5c0SFabien Parent .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table), 119bc3fc5c0SFabien Parent }; 120bc3fc5c0SFabien Parent 121ce15e7faSCK Hu struct mtk_mmsys { 122ce15e7faSCK Hu void __iomem *regs; 123ce15e7faSCK Hu const struct mtk_mmsys_driver_data *data; 124f27ef285SEnric Balletbo i Serra spinlock_t lock; /* protects mmsys_sw_rst_b reg */ 125f27ef285SEnric Balletbo i Serra struct reset_controller_dev rcdev; 1268af1f6b5SNancy.Lin struct cmdq_client_reg cmdq_base; 127ce15e7faSCK Hu }; 128ce15e7faSCK Hu 1298af1f6b5SNancy.Lin static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val, 1308af1f6b5SNancy.Lin struct cmdq_pkt *cmdq_pkt) 1310a815034SNancy.Lin { 1320a815034SNancy.Lin u32 tmp; 1330a815034SNancy.Lin 1348af1f6b5SNancy.Lin #if IS_REACHABLE(CONFIG_MTK_CMDQ) 1358af1f6b5SNancy.Lin if (cmdq_pkt) { 1368af1f6b5SNancy.Lin if (mmsys->cmdq_base.size == 0) { 1378af1f6b5SNancy.Lin pr_err("mmsys lose gce property, failed to update mmsys bits with cmdq"); 1388af1f6b5SNancy.Lin return; 1398af1f6b5SNancy.Lin } 1408af1f6b5SNancy.Lin cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys, 1418af1f6b5SNancy.Lin mmsys->cmdq_base.offset + offset, val, 1428af1f6b5SNancy.Lin mask); 1438af1f6b5SNancy.Lin return; 1448af1f6b5SNancy.Lin } 1458af1f6b5SNancy.Lin #endif 1468af1f6b5SNancy.Lin 1470a815034SNancy.Lin tmp = readl_relaxed(mmsys->regs + offset); 1480a815034SNancy.Lin tmp = (tmp & ~mask) | (val & mask); 1490a815034SNancy.Lin writel_relaxed(tmp, mmsys->regs + offset); 1500a815034SNancy.Lin } 1510a815034SNancy.Lin 1522c758e30SEnric Balletbo i Serra void mtk_mmsys_ddp_connect(struct device *dev, 1532c758e30SEnric Balletbo i Serra enum mtk_ddp_comp_id cur, 1542c758e30SEnric Balletbo i Serra enum mtk_ddp_comp_id next) 1552c758e30SEnric Balletbo i Serra { 156ce15e7faSCK Hu struct mtk_mmsys *mmsys = dev_get_drvdata(dev); 15744014763SCK Hu const struct mtk_mmsys_routes *routes = mmsys->data->routes; 15844014763SCK Hu int i; 1592c758e30SEnric Balletbo i Serra 16044014763SCK Hu for (i = 0; i < mmsys->data->num_routes; i++) 1610a815034SNancy.Lin if (cur == routes[i].from_comp && next == routes[i].to_comp) 1620a815034SNancy.Lin mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 1638af1f6b5SNancy.Lin routes[i].val, NULL); 1642c758e30SEnric Balletbo i Serra } 1652c758e30SEnric Balletbo i Serra EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); 1662c758e30SEnric Balletbo i Serra 1672c758e30SEnric Balletbo i Serra void mtk_mmsys_ddp_disconnect(struct device *dev, 1682c758e30SEnric Balletbo i Serra enum mtk_ddp_comp_id cur, 1692c758e30SEnric Balletbo i Serra enum mtk_ddp_comp_id next) 1702c758e30SEnric Balletbo i Serra { 171ce15e7faSCK Hu struct mtk_mmsys *mmsys = dev_get_drvdata(dev); 17244014763SCK Hu const struct mtk_mmsys_routes *routes = mmsys->data->routes; 17344014763SCK Hu int i; 1742c758e30SEnric Balletbo i Serra 17544014763SCK Hu for (i = 0; i < mmsys->data->num_routes; i++) 1760a815034SNancy.Lin if (cur == routes[i].from_comp && next == routes[i].to_comp) 1778af1f6b5SNancy.Lin mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0, NULL); 1782c758e30SEnric Balletbo i Serra } 1792c758e30SEnric Balletbo i Serra EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); 1802c758e30SEnric Balletbo i Serra 1818af1f6b5SNancy.Lin void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height, 1828af1f6b5SNancy.Lin struct cmdq_pkt *cmdq_pkt) 1833dd20b71SNancy.Lin { 1843dd20b71SNancy.Lin mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx, 1858af1f6b5SNancy.Lin ~0, height << 16 | width, cmdq_pkt); 1863dd20b71SNancy.Lin } 1873dd20b71SNancy.Lin EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config); 1883dd20b71SNancy.Lin 1898af1f6b5SNancy.Lin void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height, 1908af1f6b5SNancy.Lin struct cmdq_pkt *cmdq_pkt) 1913dd20b71SNancy.Lin { 1923dd20b71SNancy.Lin mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0, 1938af1f6b5SNancy.Lin be_height << 16 | be_width, cmdq_pkt); 1943dd20b71SNancy.Lin } 1953dd20b71SNancy.Lin EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_config); 1963dd20b71SNancy.Lin 1973dd20b71SNancy.Lin void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha, 1988af1f6b5SNancy.Lin u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt) 1993dd20b71SNancy.Lin { 2003dd20b71SNancy.Lin struct mtk_mmsys *mmsys = dev_get_drvdata(dev); 2013dd20b71SNancy.Lin 2023dd20b71SNancy.Lin mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0, 2038af1f6b5SNancy.Lin alpha << 16 | alpha, cmdq_pkt); 2043dd20b71SNancy.Lin mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx), 2058af1f6b5SNancy.Lin alpha_sel << (19 + idx), cmdq_pkt); 2063dd20b71SNancy.Lin mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, 2078af1f6b5SNancy.Lin GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt); 2083dd20b71SNancy.Lin } 2093dd20b71SNancy.Lin EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config); 2103dd20b71SNancy.Lin 2118af1f6b5SNancy.Lin void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap, 2128af1f6b5SNancy.Lin struct cmdq_pkt *cmdq_pkt) 2133dd20b71SNancy.Lin { 2143dd20b71SNancy.Lin mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, 2158af1f6b5SNancy.Lin BIT(4), channel_swap << 4, cmdq_pkt); 2163dd20b71SNancy.Lin } 2173dd20b71SNancy.Lin EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap); 2183dd20b71SNancy.Lin 219b404cb45SXinlei Lee void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val) 220b404cb45SXinlei Lee { 221e6c7e621SXinlei Lee struct mtk_mmsys *mmsys = dev_get_drvdata(dev); 222e6c7e621SXinlei Lee 223e6c7e621SXinlei Lee switch (val) { 224e6c7e621SXinlei Lee case MTK_DPI_RGB888_SDR_CON: 225e6c7e621SXinlei Lee mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, 2268af1f6b5SNancy.Lin MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_SDR_CON, NULL); 227e6c7e621SXinlei Lee break; 228e6c7e621SXinlei Lee case MTK_DPI_RGB565_SDR_CON: 229e6c7e621SXinlei Lee mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, 2308af1f6b5SNancy.Lin MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_SDR_CON, NULL); 231e6c7e621SXinlei Lee break; 232e6c7e621SXinlei Lee case MTK_DPI_RGB565_DDR_CON: 233e6c7e621SXinlei Lee mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, 2348af1f6b5SNancy.Lin MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_DDR_CON, NULL); 235e6c7e621SXinlei Lee break; 236e6c7e621SXinlei Lee case MTK_DPI_RGB888_DDR_CON: 237e6c7e621SXinlei Lee default: 238e6c7e621SXinlei Lee mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, 2398af1f6b5SNancy.Lin MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_DDR_CON, NULL); 240e6c7e621SXinlei Lee break; 241e6c7e621SXinlei Lee } 242b404cb45SXinlei Lee } 243b404cb45SXinlei Lee EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config); 244b404cb45SXinlei Lee 245f27ef285SEnric Balletbo i Serra static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id, 246f27ef285SEnric Balletbo i Serra bool assert) 247f27ef285SEnric Balletbo i Serra { 248f27ef285SEnric Balletbo i Serra struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev); 249f27ef285SEnric Balletbo i Serra unsigned long flags; 2502004f8beSNancy.Lin u32 offset; 2512004f8beSNancy.Lin u32 reg; 2522004f8beSNancy.Lin 2532004f8beSNancy.Lin offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); 2542004f8beSNancy.Lin id = id % MMSYS_SW_RESET_PER_REG; 2552004f8beSNancy.Lin reg = mmsys->data->sw0_rst_offset + offset; 256f27ef285SEnric Balletbo i Serra 257f27ef285SEnric Balletbo i Serra spin_lock_irqsave(&mmsys->lock, flags); 258f27ef285SEnric Balletbo i Serra 259f27ef285SEnric Balletbo i Serra if (assert) 2602004f8beSNancy.Lin mtk_mmsys_update_bits(mmsys, reg, BIT(id), 0, NULL); 261f27ef285SEnric Balletbo i Serra else 2622004f8beSNancy.Lin mtk_mmsys_update_bits(mmsys, reg, BIT(id), BIT(id), NULL); 263f27ef285SEnric Balletbo i Serra 264f27ef285SEnric Balletbo i Serra spin_unlock_irqrestore(&mmsys->lock, flags); 265f27ef285SEnric Balletbo i Serra 266f27ef285SEnric Balletbo i Serra return 0; 267f27ef285SEnric Balletbo i Serra } 268f27ef285SEnric Balletbo i Serra 269f27ef285SEnric Balletbo i Serra static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 270f27ef285SEnric Balletbo i Serra { 271f27ef285SEnric Balletbo i Serra return mtk_mmsys_reset_update(rcdev, id, true); 272f27ef285SEnric Balletbo i Serra } 273f27ef285SEnric Balletbo i Serra 274f27ef285SEnric Balletbo i Serra static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 275f27ef285SEnric Balletbo i Serra { 276f27ef285SEnric Balletbo i Serra return mtk_mmsys_reset_update(rcdev, id, false); 277f27ef285SEnric Balletbo i Serra } 278f27ef285SEnric Balletbo i Serra 279f27ef285SEnric Balletbo i Serra static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id) 280f27ef285SEnric Balletbo i Serra { 281f27ef285SEnric Balletbo i Serra int ret; 282f27ef285SEnric Balletbo i Serra 283f27ef285SEnric Balletbo i Serra ret = mtk_mmsys_reset_assert(rcdev, id); 284f27ef285SEnric Balletbo i Serra if (ret) 285f27ef285SEnric Balletbo i Serra return ret; 286f27ef285SEnric Balletbo i Serra 287f27ef285SEnric Balletbo i Serra usleep_range(1000, 1100); 288f27ef285SEnric Balletbo i Serra 289f27ef285SEnric Balletbo i Serra return mtk_mmsys_reset_deassert(rcdev, id); 290f27ef285SEnric Balletbo i Serra } 291f27ef285SEnric Balletbo i Serra 292f27ef285SEnric Balletbo i Serra static const struct reset_control_ops mtk_mmsys_reset_ops = { 293f27ef285SEnric Balletbo i Serra .assert = mtk_mmsys_reset_assert, 294f27ef285SEnric Balletbo i Serra .deassert = mtk_mmsys_reset_deassert, 295f27ef285SEnric Balletbo i Serra .reset = mtk_mmsys_reset, 296f27ef285SEnric Balletbo i Serra }; 297f27ef285SEnric Balletbo i Serra 29813032709SMatthias Brugger static int mtk_mmsys_probe(struct platform_device *pdev) 29913032709SMatthias Brugger { 3002c758e30SEnric Balletbo i Serra struct device *dev = &pdev->dev; 30113032709SMatthias Brugger struct platform_device *clks; 302667c7692SEnric Balletbo i Serra struct platform_device *drm; 303ce15e7faSCK Hu struct mtk_mmsys *mmsys; 3042c758e30SEnric Balletbo i Serra int ret; 3052c758e30SEnric Balletbo i Serra 306ce15e7faSCK Hu mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); 307ce15e7faSCK Hu if (!mmsys) 308ce15e7faSCK Hu return -ENOMEM; 309ce15e7faSCK Hu 310ce15e7faSCK Hu mmsys->regs = devm_platform_ioremap_resource(pdev, 0); 311ce15e7faSCK Hu if (IS_ERR(mmsys->regs)) { 312ce15e7faSCK Hu ret = PTR_ERR(mmsys->regs); 313cc657602SEnric Balletbo i Serra dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret); 3142c758e30SEnric Balletbo i Serra return ret; 3152c758e30SEnric Balletbo i Serra } 3162c758e30SEnric Balletbo i Serra 3172004f8beSNancy.Lin mmsys->data = of_device_get_match_data(&pdev->dev); 3182004f8beSNancy.Lin 3192004f8beSNancy.Lin if (mmsys->data->num_resets > 0) { 320f27ef285SEnric Balletbo i Serra spin_lock_init(&mmsys->lock); 321f27ef285SEnric Balletbo i Serra 322f27ef285SEnric Balletbo i Serra mmsys->rcdev.owner = THIS_MODULE; 3232004f8beSNancy.Lin mmsys->rcdev.nr_resets = mmsys->data->num_resets; 324f27ef285SEnric Balletbo i Serra mmsys->rcdev.ops = &mtk_mmsys_reset_ops; 325f27ef285SEnric Balletbo i Serra mmsys->rcdev.of_node = pdev->dev.of_node; 326f27ef285SEnric Balletbo i Serra ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev); 327f27ef285SEnric Balletbo i Serra if (ret) { 328f27ef285SEnric Balletbo i Serra dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret); 329f27ef285SEnric Balletbo i Serra return ret; 330f27ef285SEnric Balletbo i Serra } 3312004f8beSNancy.Lin } 3328af1f6b5SNancy.Lin 3338af1f6b5SNancy.Lin #if IS_REACHABLE(CONFIG_MTK_CMDQ) 3348af1f6b5SNancy.Lin ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); 3358af1f6b5SNancy.Lin if (ret) 3368af1f6b5SNancy.Lin dev_dbg(dev, "No mediatek,gce-client-reg!\n"); 3378af1f6b5SNancy.Lin #endif 3388af1f6b5SNancy.Lin 339ce15e7faSCK Hu platform_set_drvdata(pdev, mmsys); 34013032709SMatthias Brugger 341ce15e7faSCK Hu clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, 34213032709SMatthias Brugger PLATFORM_DEVID_AUTO, NULL, 0); 34313032709SMatthias Brugger if (IS_ERR(clks)) 34413032709SMatthias Brugger return PTR_ERR(clks); 34513032709SMatthias Brugger 346*78ce3093SRoy-CW.Yeh if (mmsys->data->is_vppsys) 347*78ce3093SRoy-CW.Yeh goto out_probe_done; 348*78ce3093SRoy-CW.Yeh 349667c7692SEnric Balletbo i Serra drm = platform_device_register_data(&pdev->dev, "mediatek-drm", 350667c7692SEnric Balletbo i Serra PLATFORM_DEVID_AUTO, NULL, 0); 351ff34e17cSWei Yongjun if (IS_ERR(drm)) { 352ff34e17cSWei Yongjun platform_device_unregister(clks); 353667c7692SEnric Balletbo i Serra return PTR_ERR(drm); 354ff34e17cSWei Yongjun } 355667c7692SEnric Balletbo i Serra 356*78ce3093SRoy-CW.Yeh out_probe_done: 35713032709SMatthias Brugger return 0; 35813032709SMatthias Brugger } 35913032709SMatthias Brugger 36013032709SMatthias Brugger static const struct of_device_id of_match_mtk_mmsys[] = { 36113032709SMatthias Brugger { 362c292b133SEnric Balletbo i Serra .compatible = "mediatek,mt2701-mmsys", 3638d8ccdd2SJason-JH.Lin .data = &mt2701_mmsys_driver_data, 364c292b133SEnric Balletbo i Serra }, 365c292b133SEnric Balletbo i Serra { 3669c5a0a3aSEnric Balletbo i Serra .compatible = "mediatek,mt2712-mmsys", 3678d8ccdd2SJason-JH.Lin .data = &mt2712_mmsys_driver_data, 3689c5a0a3aSEnric Balletbo i Serra }, 3699c5a0a3aSEnric Balletbo i Serra { 37032956ddaSMatthias Brugger .compatible = "mediatek,mt6779-mmsys", 3718d8ccdd2SJason-JH.Lin .data = &mt6779_mmsys_driver_data, 37232956ddaSMatthias Brugger }, 37332956ddaSMatthias Brugger { 374cad4e379SMatthias Brugger .compatible = "mediatek,mt6797-mmsys", 3758d8ccdd2SJason-JH.Lin .data = &mt6797_mmsys_driver_data, 376cad4e379SMatthias Brugger }, 377cad4e379SMatthias Brugger { 378060f7875SFabien Parent .compatible = "mediatek,mt8167-mmsys", 3798d8ccdd2SJason-JH.Lin .data = &mt8167_mmsys_driver_data, 380060f7875SFabien Parent }, 381060f7875SFabien Parent { 38213032709SMatthias Brugger .compatible = "mediatek,mt8173-mmsys", 3838d8ccdd2SJason-JH.Lin .data = &mt8173_mmsys_driver_data, 38413032709SMatthias Brugger }, 3851f9adbc7SMatthias Brugger { 3861f9adbc7SMatthias Brugger .compatible = "mediatek,mt8183-mmsys", 3878d8ccdd2SJason-JH.Lin .data = &mt8183_mmsys_driver_data, 3881f9adbc7SMatthias Brugger }, 389bc3fc5c0SFabien Parent { 3905f9b5b75SYongqiang Niu .compatible = "mediatek,mt8186-mmsys", 3918d8ccdd2SJason-JH.Lin .data = &mt8186_mmsys_driver_data, 3925f9b5b75SYongqiang Niu }, 3935f9b5b75SYongqiang Niu { 3943b1a57c4SNathan Lu .compatible = "mediatek,mt8188-vdosys0", 3953b1a57c4SNathan Lu .data = &mt8188_vdosys0_driver_data, 3963b1a57c4SNathan Lu }, 3973b1a57c4SNathan Lu { 398d687e056SYongqiang Niu .compatible = "mediatek,mt8192-mmsys", 3998d8ccdd2SJason-JH.Lin .data = &mt8192_mmsys_driver_data, 400d687e056SYongqiang Niu }, 4017fd731a8SMatthias Brugger { /* deprecated compatible */ 4027fd731a8SMatthias Brugger .compatible = "mediatek,mt8195-mmsys", 4037fd731a8SMatthias Brugger .data = &mt8195_vdosys0_driver_data, 4047fd731a8SMatthias Brugger }, 405d687e056SYongqiang Niu { 406b2b99a7aSJason-JH.Lin .compatible = "mediatek,mt8195-vdosys0", 407b2b99a7aSJason-JH.Lin .data = &mt8195_vdosys0_driver_data, 408b2b99a7aSJason-JH.Lin }, 409b2b99a7aSJason-JH.Lin { 41039170127SNancy.Lin .compatible = "mediatek,mt8195-vdosys1", 41139170127SNancy.Lin .data = &mt8195_vdosys1_driver_data, 41239170127SNancy.Lin }, 41339170127SNancy.Lin { 414*78ce3093SRoy-CW.Yeh .compatible = "mediatek,mt8195-vppsys0", 415*78ce3093SRoy-CW.Yeh .data = &mt8195_vppsys0_driver_data, 416*78ce3093SRoy-CW.Yeh }, 417*78ce3093SRoy-CW.Yeh { 418*78ce3093SRoy-CW.Yeh .compatible = "mediatek,mt8195-vppsys1", 419*78ce3093SRoy-CW.Yeh .data = &mt8195_vppsys1_driver_data, 420*78ce3093SRoy-CW.Yeh }, 421*78ce3093SRoy-CW.Yeh { 422bc3fc5c0SFabien Parent .compatible = "mediatek,mt8365-mmsys", 4238d8ccdd2SJason-JH.Lin .data = &mt8365_mmsys_driver_data, 424bc3fc5c0SFabien Parent }, 42513032709SMatthias Brugger { } 42613032709SMatthias Brugger }; 42713032709SMatthias Brugger 42813032709SMatthias Brugger static struct platform_driver mtk_mmsys_drv = { 42913032709SMatthias Brugger .driver = { 43013032709SMatthias Brugger .name = "mtk-mmsys", 43113032709SMatthias Brugger .of_match_table = of_match_mtk_mmsys, 43213032709SMatthias Brugger }, 43313032709SMatthias Brugger .probe = mtk_mmsys_probe, 43413032709SMatthias Brugger }; 43513032709SMatthias Brugger 436a7596e62SYongqiang Niu static int __init mtk_mmsys_init(void) 437a7596e62SYongqiang Niu { 438a7596e62SYongqiang Niu return platform_driver_register(&mtk_mmsys_drv); 439a7596e62SYongqiang Niu } 440a7596e62SYongqiang Niu 441a7596e62SYongqiang Niu static void __exit mtk_mmsys_exit(void) 442a7596e62SYongqiang Niu { 443a7596e62SYongqiang Niu platform_driver_unregister(&mtk_mmsys_drv); 444a7596e62SYongqiang Niu } 445a7596e62SYongqiang Niu 446a7596e62SYongqiang Niu module_init(mtk_mmsys_init); 447a7596e62SYongqiang Niu module_exit(mtk_mmsys_exit); 448a7596e62SYongqiang Niu 449a7596e62SYongqiang Niu MODULE_AUTHOR("Yongqiang Niu <yongqiang.niu@mediatek.com>"); 450a7596e62SYongqiang Niu MODULE_DESCRIPTION("MediaTek SoC MMSYS driver"); 451a7596e62SYongqiang Niu MODULE_LICENSE("GPL"); 452