10890beb2SNeal Liu // SPDX-License-Identifier: GPL-2.0 20890beb2SNeal Liu /* 30890beb2SNeal Liu * Copyright (C) 2020 MediaTek Inc. 40890beb2SNeal Liu */ 50890beb2SNeal Liu 60890beb2SNeal Liu #include <linux/clk.h> 70890beb2SNeal Liu #include <linux/interrupt.h> 80890beb2SNeal Liu #include <linux/iopoll.h> 90890beb2SNeal Liu #include <linux/module.h> 100890beb2SNeal Liu #include <linux/platform_device.h> 110890beb2SNeal Liu #include <linux/of_device.h> 120890beb2SNeal Liu #include <linux/of_irq.h> 130890beb2SNeal Liu #include <linux/of_address.h> 140890beb2SNeal Liu 150890beb2SNeal Liu #define VIO_MOD_TO_REG_IND(m) ((m) / 32) 160890beb2SNeal Liu #define VIO_MOD_TO_REG_OFF(m) ((m) % 32) 170890beb2SNeal Liu 180890beb2SNeal Liu struct mtk_devapc_vio_dbgs { 190890beb2SNeal Liu union { 200890beb2SNeal Liu u32 vio_dbg0; 210890beb2SNeal Liu struct { 220890beb2SNeal Liu u32 mstid:16; 230890beb2SNeal Liu u32 dmnid:6; 240890beb2SNeal Liu u32 vio_w:1; 250890beb2SNeal Liu u32 vio_r:1; 260890beb2SNeal Liu u32 addr_h:4; 270890beb2SNeal Liu u32 resv:4; 280890beb2SNeal Liu } dbg0_bits; 290890beb2SNeal Liu }; 300890beb2SNeal Liu 310890beb2SNeal Liu u32 vio_dbg1; 320890beb2SNeal Liu }; 330890beb2SNeal Liu 342cb41ed0SRex-BC Chen struct mtk_devapc_regs_ofs { 350890beb2SNeal Liu /* reg offset */ 360890beb2SNeal Liu u32 vio_mask_offset; 370890beb2SNeal Liu u32 vio_sta_offset; 380890beb2SNeal Liu u32 vio_dbg0_offset; 390890beb2SNeal Liu u32 vio_dbg1_offset; 400890beb2SNeal Liu u32 apc_con_offset; 410890beb2SNeal Liu u32 vio_shift_sta_offset; 420890beb2SNeal Liu u32 vio_shift_sel_offset; 430890beb2SNeal Liu u32 vio_shift_con_offset; 440890beb2SNeal Liu }; 450890beb2SNeal Liu 462cb41ed0SRex-BC Chen struct mtk_devapc_data { 472cb41ed0SRex-BC Chen /* numbers of violation index */ 482cb41ed0SRex-BC Chen u32 vio_idx_num; 492cb41ed0SRex-BC Chen const struct mtk_devapc_regs_ofs *regs_ofs; 502cb41ed0SRex-BC Chen }; 512cb41ed0SRex-BC Chen 520890beb2SNeal Liu struct mtk_devapc_context { 530890beb2SNeal Liu struct device *dev; 540890beb2SNeal Liu void __iomem *infra_base; 550890beb2SNeal Liu struct clk *infra_clk; 560890beb2SNeal Liu const struct mtk_devapc_data *data; 570890beb2SNeal Liu }; 580890beb2SNeal Liu 590890beb2SNeal Liu static void clear_vio_status(struct mtk_devapc_context *ctx) 600890beb2SNeal Liu { 610890beb2SNeal Liu void __iomem *reg; 620890beb2SNeal Liu int i; 630890beb2SNeal Liu 642cb41ed0SRex-BC Chen reg = ctx->infra_base + ctx->data->regs_ofs->vio_sta_offset; 650890beb2SNeal Liu 660890beb2SNeal Liu for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++) 670890beb2SNeal Liu writel(GENMASK(31, 0), reg + 4 * i); 680890beb2SNeal Liu 690890beb2SNeal Liu writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, 0), 700890beb2SNeal Liu reg + 4 * i); 710890beb2SNeal Liu } 720890beb2SNeal Liu 730890beb2SNeal Liu static void mask_module_irq(struct mtk_devapc_context *ctx, bool mask) 740890beb2SNeal Liu { 750890beb2SNeal Liu void __iomem *reg; 760890beb2SNeal Liu u32 val; 770890beb2SNeal Liu int i; 780890beb2SNeal Liu 792cb41ed0SRex-BC Chen reg = ctx->infra_base + ctx->data->regs_ofs->vio_mask_offset; 800890beb2SNeal Liu 810890beb2SNeal Liu if (mask) 820890beb2SNeal Liu val = GENMASK(31, 0); 830890beb2SNeal Liu else 840890beb2SNeal Liu val = 0; 850890beb2SNeal Liu 860890beb2SNeal Liu for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++) 870890beb2SNeal Liu writel(val, reg + 4 * i); 880890beb2SNeal Liu 890890beb2SNeal Liu val = readl(reg + 4 * i); 900890beb2SNeal Liu if (mask) 910890beb2SNeal Liu val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, 920890beb2SNeal Liu 0); 930890beb2SNeal Liu else 940890beb2SNeal Liu val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, 950890beb2SNeal Liu 0); 960890beb2SNeal Liu 970890beb2SNeal Liu writel(val, reg + 4 * i); 980890beb2SNeal Liu } 990890beb2SNeal Liu 1000890beb2SNeal Liu #define PHY_DEVAPC_TIMEOUT 0x10000 1010890beb2SNeal Liu 1020890beb2SNeal Liu /* 1030890beb2SNeal Liu * devapc_sync_vio_dbg - do "shift" mechansim" to get full violation information. 1040890beb2SNeal Liu * shift mechanism is depends on devapc hardware design. 1050890beb2SNeal Liu * Mediatek devapc set multiple slaves as a group. 1060890beb2SNeal Liu * When violation is triggered, violation info is kept 1070890beb2SNeal Liu * inside devapc hardware. 1080890beb2SNeal Liu * Driver should do shift mechansim to sync full violation 1090890beb2SNeal Liu * info to VIO_DBGs registers. 1100890beb2SNeal Liu * 1110890beb2SNeal Liu */ 1120890beb2SNeal Liu static int devapc_sync_vio_dbg(struct mtk_devapc_context *ctx) 1130890beb2SNeal Liu { 1140890beb2SNeal Liu void __iomem *pd_vio_shift_sta_reg; 1150890beb2SNeal Liu void __iomem *pd_vio_shift_sel_reg; 1160890beb2SNeal Liu void __iomem *pd_vio_shift_con_reg; 1170890beb2SNeal Liu int min_shift_group; 1180890beb2SNeal Liu int ret; 1190890beb2SNeal Liu u32 val; 1200890beb2SNeal Liu 1210890beb2SNeal Liu pd_vio_shift_sta_reg = ctx->infra_base + 1222cb41ed0SRex-BC Chen ctx->data->regs_ofs->vio_shift_sta_offset; 1230890beb2SNeal Liu pd_vio_shift_sel_reg = ctx->infra_base + 1242cb41ed0SRex-BC Chen ctx->data->regs_ofs->vio_shift_sel_offset; 1250890beb2SNeal Liu pd_vio_shift_con_reg = ctx->infra_base + 1262cb41ed0SRex-BC Chen ctx->data->regs_ofs->vio_shift_con_offset; 1270890beb2SNeal Liu 1280890beb2SNeal Liu /* Find the minimum shift group which has violation */ 1290890beb2SNeal Liu val = readl(pd_vio_shift_sta_reg); 1300890beb2SNeal Liu if (!val) 1310890beb2SNeal Liu return false; 1320890beb2SNeal Liu 1330890beb2SNeal Liu min_shift_group = __ffs(val); 1340890beb2SNeal Liu 1350890beb2SNeal Liu /* Assign the group to sync */ 1360890beb2SNeal Liu writel(0x1 << min_shift_group, pd_vio_shift_sel_reg); 1370890beb2SNeal Liu 1380890beb2SNeal Liu /* Start syncing */ 1390890beb2SNeal Liu writel(0x1, pd_vio_shift_con_reg); 1400890beb2SNeal Liu 1410890beb2SNeal Liu ret = readl_poll_timeout(pd_vio_shift_con_reg, val, val == 0x3, 0, 1420890beb2SNeal Liu PHY_DEVAPC_TIMEOUT); 1430890beb2SNeal Liu if (ret) { 1440890beb2SNeal Liu dev_err(ctx->dev, "%s: Shift violation info failed\n", __func__); 1450890beb2SNeal Liu return false; 1460890beb2SNeal Liu } 1470890beb2SNeal Liu 1480890beb2SNeal Liu /* Stop syncing */ 1490890beb2SNeal Liu writel(0x0, pd_vio_shift_con_reg); 1500890beb2SNeal Liu 1510890beb2SNeal Liu /* Write clear */ 1520890beb2SNeal Liu writel(0x1 << min_shift_group, pd_vio_shift_sta_reg); 1530890beb2SNeal Liu 1540890beb2SNeal Liu return true; 1550890beb2SNeal Liu } 1560890beb2SNeal Liu 1570890beb2SNeal Liu /* 1580890beb2SNeal Liu * devapc_extract_vio_dbg - extract full violation information after doing 1590890beb2SNeal Liu * shift mechanism. 1600890beb2SNeal Liu */ 1610890beb2SNeal Liu static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx) 1620890beb2SNeal Liu { 1630890beb2SNeal Liu struct mtk_devapc_vio_dbgs vio_dbgs; 1640890beb2SNeal Liu void __iomem *vio_dbg0_reg; 1650890beb2SNeal Liu void __iomem *vio_dbg1_reg; 1660890beb2SNeal Liu 1672cb41ed0SRex-BC Chen vio_dbg0_reg = ctx->infra_base + ctx->data->regs_ofs->vio_dbg0_offset; 1682cb41ed0SRex-BC Chen vio_dbg1_reg = ctx->infra_base + ctx->data->regs_ofs->vio_dbg1_offset; 1690890beb2SNeal Liu 1700890beb2SNeal Liu vio_dbgs.vio_dbg0 = readl(vio_dbg0_reg); 1710890beb2SNeal Liu vio_dbgs.vio_dbg1 = readl(vio_dbg1_reg); 1720890beb2SNeal Liu 1730890beb2SNeal Liu /* Print violation information */ 1740890beb2SNeal Liu if (vio_dbgs.dbg0_bits.vio_w) 1750890beb2SNeal Liu dev_info(ctx->dev, "Write Violation\n"); 1760890beb2SNeal Liu else if (vio_dbgs.dbg0_bits.vio_r) 1770890beb2SNeal Liu dev_info(ctx->dev, "Read Violation\n"); 1780890beb2SNeal Liu 1790890beb2SNeal Liu dev_info(ctx->dev, "Bus ID:0x%x, Dom ID:0x%x, Vio Addr:0x%x\n", 1800890beb2SNeal Liu vio_dbgs.dbg0_bits.mstid, vio_dbgs.dbg0_bits.dmnid, 1810890beb2SNeal Liu vio_dbgs.vio_dbg1); 1820890beb2SNeal Liu } 1830890beb2SNeal Liu 1840890beb2SNeal Liu /* 1850890beb2SNeal Liu * devapc_violation_irq - the devapc Interrupt Service Routine (ISR) will dump 1860890beb2SNeal Liu * violation information including which master violates 1870890beb2SNeal Liu * access slave. 1880890beb2SNeal Liu */ 1890890beb2SNeal Liu static irqreturn_t devapc_violation_irq(int irq_number, void *data) 1900890beb2SNeal Liu { 1910890beb2SNeal Liu struct mtk_devapc_context *ctx = data; 1920890beb2SNeal Liu 1930890beb2SNeal Liu while (devapc_sync_vio_dbg(ctx)) 1940890beb2SNeal Liu devapc_extract_vio_dbg(ctx); 1950890beb2SNeal Liu 1960890beb2SNeal Liu clear_vio_status(ctx); 1970890beb2SNeal Liu 1980890beb2SNeal Liu return IRQ_HANDLED; 1990890beb2SNeal Liu } 2000890beb2SNeal Liu 2010890beb2SNeal Liu /* 2020890beb2SNeal Liu * start_devapc - unmask slave's irq to start receiving devapc violation. 2030890beb2SNeal Liu */ 2040890beb2SNeal Liu static void start_devapc(struct mtk_devapc_context *ctx) 2050890beb2SNeal Liu { 2062cb41ed0SRex-BC Chen writel(BIT(31), ctx->infra_base + ctx->data->regs_ofs->apc_con_offset); 2070890beb2SNeal Liu 2080890beb2SNeal Liu mask_module_irq(ctx, false); 2090890beb2SNeal Liu } 2100890beb2SNeal Liu 2110890beb2SNeal Liu /* 2120890beb2SNeal Liu * stop_devapc - mask slave's irq to stop service. 2130890beb2SNeal Liu */ 2140890beb2SNeal Liu static void stop_devapc(struct mtk_devapc_context *ctx) 2150890beb2SNeal Liu { 2160890beb2SNeal Liu mask_module_irq(ctx, true); 2170890beb2SNeal Liu 2182cb41ed0SRex-BC Chen writel(BIT(2), ctx->infra_base + ctx->data->regs_ofs->apc_con_offset); 2190890beb2SNeal Liu } 2200890beb2SNeal Liu 2212cb41ed0SRex-BC Chen static const struct mtk_devapc_regs_ofs devapc_regs_ofs_mt6779 = { 2220890beb2SNeal Liu .vio_mask_offset = 0x0, 2230890beb2SNeal Liu .vio_sta_offset = 0x400, 2240890beb2SNeal Liu .vio_dbg0_offset = 0x900, 2250890beb2SNeal Liu .vio_dbg1_offset = 0x904, 2260890beb2SNeal Liu .apc_con_offset = 0xF00, 2270890beb2SNeal Liu .vio_shift_sta_offset = 0xF10, 2280890beb2SNeal Liu .vio_shift_sel_offset = 0xF14, 2290890beb2SNeal Liu .vio_shift_con_offset = 0xF20, 2300890beb2SNeal Liu }; 2310890beb2SNeal Liu 2322cb41ed0SRex-BC Chen static const struct mtk_devapc_data devapc_mt6779 = { 2332cb41ed0SRex-BC Chen .vio_idx_num = 511, 2342cb41ed0SRex-BC Chen .regs_ofs = &devapc_regs_ofs_mt6779, 2352cb41ed0SRex-BC Chen }; 2362cb41ed0SRex-BC Chen 2371c9faaceSRex-BC Chen static const struct mtk_devapc_data devapc_mt8186 = { 2381c9faaceSRex-BC Chen .vio_idx_num = 519, 2391c9faaceSRex-BC Chen .regs_ofs = &devapc_regs_ofs_mt6779, 2401c9faaceSRex-BC Chen }; 2411c9faaceSRex-BC Chen 2420890beb2SNeal Liu static const struct of_device_id mtk_devapc_dt_match[] = { 2430890beb2SNeal Liu { 2440890beb2SNeal Liu .compatible = "mediatek,mt6779-devapc", 2450890beb2SNeal Liu .data = &devapc_mt6779, 2460890beb2SNeal Liu }, { 2471c9faaceSRex-BC Chen .compatible = "mediatek,mt8186-devapc", 2481c9faaceSRex-BC Chen .data = &devapc_mt8186, 2491c9faaceSRex-BC Chen }, { 2500890beb2SNeal Liu }, 2510890beb2SNeal Liu }; 252ba96de3aSZou Wei MODULE_DEVICE_TABLE(of, mtk_devapc_dt_match); 2530890beb2SNeal Liu 2540890beb2SNeal Liu static int mtk_devapc_probe(struct platform_device *pdev) 2550890beb2SNeal Liu { 2560890beb2SNeal Liu struct device_node *node = pdev->dev.of_node; 2570890beb2SNeal Liu struct mtk_devapc_context *ctx; 2580890beb2SNeal Liu u32 devapc_irq; 2590890beb2SNeal Liu int ret; 2600890beb2SNeal Liu 2610890beb2SNeal Liu if (IS_ERR(node)) 2620890beb2SNeal Liu return -ENODEV; 2630890beb2SNeal Liu 2640890beb2SNeal Liu ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); 2650890beb2SNeal Liu if (!ctx) 2660890beb2SNeal Liu return -ENOMEM; 2670890beb2SNeal Liu 2680890beb2SNeal Liu ctx->data = of_device_get_match_data(&pdev->dev); 2690890beb2SNeal Liu ctx->dev = &pdev->dev; 2700890beb2SNeal Liu 2710890beb2SNeal Liu ctx->infra_base = of_iomap(node, 0); 2720890beb2SNeal Liu if (!ctx->infra_base) 2730890beb2SNeal Liu return -EINVAL; 2740890beb2SNeal Liu 2750890beb2SNeal Liu devapc_irq = irq_of_parse_and_map(node, 0); 2760890beb2SNeal Liu if (!devapc_irq) 2770890beb2SNeal Liu return -EINVAL; 2780890beb2SNeal Liu 279*916120dfSAngeloGioacchino Del Regno ctx->infra_clk = devm_clk_get_enabled(&pdev->dev, "devapc-infra-clock"); 2800890beb2SNeal Liu if (IS_ERR(ctx->infra_clk)) 2810890beb2SNeal Liu return -EINVAL; 2820890beb2SNeal Liu 2830890beb2SNeal Liu ret = devm_request_irq(&pdev->dev, devapc_irq, devapc_violation_irq, 2840890beb2SNeal Liu IRQF_TRIGGER_NONE, "devapc", ctx); 285*916120dfSAngeloGioacchino Del Regno if (ret) 2860890beb2SNeal Liu return ret; 2870890beb2SNeal Liu 2880890beb2SNeal Liu platform_set_drvdata(pdev, ctx); 2890890beb2SNeal Liu 2900890beb2SNeal Liu start_devapc(ctx); 2910890beb2SNeal Liu 2920890beb2SNeal Liu return 0; 2930890beb2SNeal Liu } 2940890beb2SNeal Liu 2950890beb2SNeal Liu static int mtk_devapc_remove(struct platform_device *pdev) 2960890beb2SNeal Liu { 2970890beb2SNeal Liu struct mtk_devapc_context *ctx = platform_get_drvdata(pdev); 2980890beb2SNeal Liu 2990890beb2SNeal Liu stop_devapc(ctx); 3000890beb2SNeal Liu 3010890beb2SNeal Liu return 0; 3020890beb2SNeal Liu } 3030890beb2SNeal Liu 3040890beb2SNeal Liu static struct platform_driver mtk_devapc_driver = { 3050890beb2SNeal Liu .probe = mtk_devapc_probe, 3060890beb2SNeal Liu .remove = mtk_devapc_remove, 3070890beb2SNeal Liu .driver = { 3080890beb2SNeal Liu .name = "mtk-devapc", 3090890beb2SNeal Liu .of_match_table = mtk_devapc_dt_match, 3100890beb2SNeal Liu }, 3110890beb2SNeal Liu }; 3120890beb2SNeal Liu 3130890beb2SNeal Liu module_platform_driver(mtk_devapc_driver); 3140890beb2SNeal Liu 3150890beb2SNeal Liu MODULE_DESCRIPTION("Mediatek Device APC Driver"); 3160890beb2SNeal Liu MODULE_AUTHOR("Neal Liu <neal.liu@mediatek.com>"); 3170890beb2SNeal Liu MODULE_LICENSE("GPL"); 318