1*bc3fc5c0SFabien Parent /* SPDX-License-Identifier: GPL-2.0-only */ 2*bc3fc5c0SFabien Parent 3*bc3fc5c0SFabien Parent #ifndef __SOC_MEDIATEK_MT8365_MMSYS_H 4*bc3fc5c0SFabien Parent #define __SOC_MEDIATEK_MT8365_MMSYS_H 5*bc3fc5c0SFabien Parent 6*bc3fc5c0SFabien Parent #define MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0xf3c 7*bc3fc5c0SFabien Parent #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL 0xf4c 8*bc3fc5c0SFabien Parent #define MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN 0xf50 9*bc3fc5c0SFabien Parent #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN 0xf54 10*bc3fc5c0SFabien Parent #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN 0xf60 11*bc3fc5c0SFabien Parent #define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0xf64 12*bc3fc5c0SFabien Parent #define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0xf68 13*bc3fc5c0SFabien Parent 14*bc3fc5c0SFabien Parent #define MT8365_RDMA0_SOUT_COLOR0 0x1 15*bc3fc5c0SFabien Parent #define MT8365_DITHER_MOUT_EN_DSI0 0x1 16*bc3fc5c0SFabien Parent #define MT8365_DSI0_SEL_IN_DITHER 0x1 17*bc3fc5c0SFabien Parent #define MT8365_RDMA0_SEL_IN_OVL0 0x0 18*bc3fc5c0SFabien Parent #define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 0x0 19*bc3fc5c0SFabien Parent #define MT8365_DISP_COLOR_SEL_IN_COLOR0 0x0 20*bc3fc5c0SFabien Parent #define MT8365_OVL0_MOUT_PATH0_SEL BIT(0) 21*bc3fc5c0SFabien Parent 22*bc3fc5c0SFabien Parent static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = { 23*bc3fc5c0SFabien Parent { 24*bc3fc5c0SFabien Parent DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 25*bc3fc5c0SFabien Parent MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, 26*bc3fc5c0SFabien Parent MT8365_OVL0_MOUT_PATH0_SEL, MT8365_OVL0_MOUT_PATH0_SEL 27*bc3fc5c0SFabien Parent }, 28*bc3fc5c0SFabien Parent { 29*bc3fc5c0SFabien Parent DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 30*bc3fc5c0SFabien Parent MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN, 31*bc3fc5c0SFabien Parent MT8365_RDMA0_SEL_IN_OVL0, MT8365_RDMA0_SEL_IN_OVL0 32*bc3fc5c0SFabien Parent }, 33*bc3fc5c0SFabien Parent { 34*bc3fc5c0SFabien Parent DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, 35*bc3fc5c0SFabien Parent MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL, 36*bc3fc5c0SFabien Parent MT8365_RDMA0_SOUT_COLOR0, MT8365_RDMA0_SOUT_COLOR0 37*bc3fc5c0SFabien Parent }, 38*bc3fc5c0SFabien Parent { 39*bc3fc5c0SFabien Parent DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR, 40*bc3fc5c0SFabien Parent MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, 41*bc3fc5c0SFabien Parent MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0 42*bc3fc5c0SFabien Parent }, 43*bc3fc5c0SFabien Parent { 44*bc3fc5c0SFabien Parent DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, 45*bc3fc5c0SFabien Parent MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN, 46*bc3fc5c0SFabien Parent MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0 47*bc3fc5c0SFabien Parent }, 48*bc3fc5c0SFabien Parent { 49*bc3fc5c0SFabien Parent DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, 50*bc3fc5c0SFabien Parent MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, 51*bc3fc5c0SFabien Parent MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER 52*bc3fc5c0SFabien Parent }, 53*bc3fc5c0SFabien Parent { 54*bc3fc5c0SFabien Parent DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, 55*bc3fc5c0SFabien Parent MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN, 56*bc3fc5c0SFabien Parent MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 57*bc3fc5c0SFabien Parent }, 58*bc3fc5c0SFabien Parent }; 59*bc3fc5c0SFabien Parent 60*bc3fc5c0SFabien Parent #endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */ 61