1bc3fc5c0SFabien Parent /* SPDX-License-Identifier: GPL-2.0-only */
2bc3fc5c0SFabien Parent 
3bc3fc5c0SFabien Parent #ifndef __SOC_MEDIATEK_MT8365_MMSYS_H
4bc3fc5c0SFabien Parent #define __SOC_MEDIATEK_MT8365_MMSYS_H
5bc3fc5c0SFabien Parent 
6bc3fc5c0SFabien Parent #define MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0xf3c
7bc3fc5c0SFabien Parent #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL	0xf4c
8bc3fc5c0SFabien Parent #define MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN	0xf50
9bc3fc5c0SFabien Parent #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN	0xf54
10bc3fc5c0SFabien Parent #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN	0xf60
11bc3fc5c0SFabien Parent #define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0xf64
12bc3fc5c0SFabien Parent #define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN		0xf68
13bc3fc5c0SFabien Parent 
14bc3fc5c0SFabien Parent #define MT8365_RDMA0_SOUT_COLOR0			0x1
15bc3fc5c0SFabien Parent #define MT8365_DITHER_MOUT_EN_DSI0			0x1
16bc3fc5c0SFabien Parent #define MT8365_DSI0_SEL_IN_DITHER			0x1
17bc3fc5c0SFabien Parent #define MT8365_RDMA0_SEL_IN_OVL0			0x0
18bc3fc5c0SFabien Parent #define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0			0x0
19bc3fc5c0SFabien Parent #define MT8365_DISP_COLOR_SEL_IN_COLOR0			0x0
20bc3fc5c0SFabien Parent #define MT8365_OVL0_MOUT_PATH0_SEL			BIT(0)
21bc3fc5c0SFabien Parent 
22bc3fc5c0SFabien Parent static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
23bc3fc5c0SFabien Parent 	{
24bc3fc5c0SFabien Parent 		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
25bc3fc5c0SFabien Parent 		MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
26bc3fc5c0SFabien Parent 		MT8365_OVL0_MOUT_PATH0_SEL, MT8365_OVL0_MOUT_PATH0_SEL
27bc3fc5c0SFabien Parent 	},
28bc3fc5c0SFabien Parent 	{
29bc3fc5c0SFabien Parent 		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
30bc3fc5c0SFabien Parent 		MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
31bc3fc5c0SFabien Parent 		MT8365_RDMA0_SEL_IN_OVL0, MT8365_RDMA0_SEL_IN_OVL0
32bc3fc5c0SFabien Parent 	},
33bc3fc5c0SFabien Parent 	{
34bc3fc5c0SFabien Parent 		DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
35bc3fc5c0SFabien Parent 		MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
36bc3fc5c0SFabien Parent 		MT8365_RDMA0_SOUT_COLOR0, MT8365_RDMA0_SOUT_COLOR0
37bc3fc5c0SFabien Parent 	},
38bc3fc5c0SFabien Parent 	{
39bc3fc5c0SFabien Parent 		DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR,
40bc3fc5c0SFabien Parent 		MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
41bc3fc5c0SFabien Parent 		MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
42bc3fc5c0SFabien Parent 	},
43bc3fc5c0SFabien Parent 	{
44*4e8988c6Sjason-jh.lin 		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
45bc3fc5c0SFabien Parent 		MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
46bc3fc5c0SFabien Parent 		MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
47bc3fc5c0SFabien Parent 	},
48bc3fc5c0SFabien Parent 	{
49*4e8988c6Sjason-jh.lin 		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
50bc3fc5c0SFabien Parent 		MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
51bc3fc5c0SFabien Parent 		MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
52bc3fc5c0SFabien Parent 	},
53bc3fc5c0SFabien Parent 	{
54bc3fc5c0SFabien Parent 		DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
55bc3fc5c0SFabien Parent 		MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
56bc3fc5c0SFabien Parent 		MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0
57bc3fc5c0SFabien Parent 	},
58bc3fc5c0SFabien Parent };
59bc3fc5c0SFabien Parent 
60bc3fc5c0SFabien Parent #endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */
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