1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MT8195_MMSYS_H 4 #define __SOC_MEDIATEK_MT8195_MMSYS_H 5 6 #define MT8195_VDO0_OVL_MOUT_EN 0xf14 7 #define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) 8 #define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) 9 #define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) 10 #define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) 11 #define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) 12 #define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) 13 14 #define MT8195_VDO0_SEL_IN 0xf34 15 #define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0) 16 #define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) 17 #define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0) 18 #define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0) 19 #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4) 20 #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4) 21 #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4) 22 #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5) 23 #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5) 24 #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5) 25 #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8) 26 #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8) 27 #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8) 28 #define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9) 29 #define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9) 30 #define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12) 31 #define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0) 32 #define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12) 33 #define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12) 34 #define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16) 35 #define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16) 36 #define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16) 37 #define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17) 38 #define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17) 39 #define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17) 40 #define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20) 41 #define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20) 42 #define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20) 43 #define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21) 44 #define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21) 45 #define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21) 46 #define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22) 47 #define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22) 48 49 #define MT8195_VDO0_SEL_OUT 0xf38 50 #define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0) 51 #define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) 52 #define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) 53 #define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1) 54 #define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1) 55 #define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1) 56 #define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1) 57 #define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4) 58 #define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4) 59 #define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4) 60 #define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8) 61 #define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8) 62 #define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8) 63 #define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8) 64 #define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8) 65 #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8) 66 #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11) 67 #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11) 68 #define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12) 69 #define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12) 70 #define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12) 71 #define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12) 72 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16) 73 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16) 74 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16) 75 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) 76 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16) 77 78 #define MT8195_VDO1_SW0_RST_B 0x1d0 79 #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 80 #define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 81 #define MT8195_VDO1_HDR_TOP_CFG 0xd00 82 #define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30 83 #define MT8195_VDO1_MIXER_IN1_PAD 0xd40 84 85 #define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 86 #define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1 87 88 #define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08 89 #define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1 90 91 #define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10 92 #define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0 93 94 #define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14 95 #define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0 96 97 #define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18 98 #define MT8195_MERGE4_SOUT_TO_DPI1_SEL 2 99 #define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL 3 100 101 #define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24 102 #define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1 103 104 #define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28 105 #define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1 106 107 #define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c 108 #define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1 109 110 #define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30 111 #define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1 112 113 #define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34 114 #define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1 115 116 #define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c 117 #define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1 118 119 #define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 120 #define MT8195_SOUT_TO_MIXER_IN1_SEL 1 121 122 #define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 123 #define MT8195_SOUT_TO_MIXER_IN2_SEL 1 124 125 #define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 126 #define MT8195_SOUT_TO_MIXER_IN3_SEL 1 127 128 #define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c 129 #define MT8195_SOUT_TO_MIXER_IN4_SEL 1 130 131 #define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50 132 #define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1 133 134 #define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58 135 #define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER 0 136 137 #define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c 138 #define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER 0 139 140 #define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60 141 #define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER 0 142 143 #define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64 144 #define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER 0 145 146 #define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68 147 #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 148 149 static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { 150 { 151 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 152 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0, 153 MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 154 }, { 155 DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, 156 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0, 157 MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 158 }, { 159 DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1, 160 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1, 161 MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 162 }, { 163 DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1, 164 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1, 165 MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 166 }, { 167 DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1, 168 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1, 169 MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 170 }, { 171 DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0, 172 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0, 173 MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 174 }, { 175 DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, 176 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, 177 MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT 178 }, { 179 DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0, 180 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, 181 MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 182 }, { 183 DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0, 184 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, 185 MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 186 }, { 187 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, 188 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, 189 MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 190 }, { 191 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, 192 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, 193 MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE 194 }, { 195 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1, 196 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, 197 MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 198 }, { 199 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1, 200 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, 201 MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE 202 }, { 203 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1, 204 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 205 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE 206 }, { 207 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, 208 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 209 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE 210 }, { 211 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1, 212 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 213 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE 214 }, { 215 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, 216 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 217 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT 218 }, { 219 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, 220 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 221 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT 222 }, { 223 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, 224 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 225 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT 226 }, { 227 DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1, 228 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, 229 MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT 230 }, { 231 DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0, 232 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, 233 MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT 234 }, { 235 DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1, 236 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, 237 MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT 238 }, { 239 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, 240 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, 241 MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT 242 }, { 243 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, 244 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, 245 MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE 246 }, { 247 DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0, 248 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, 249 MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 250 }, { 251 DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, 252 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, 253 MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT 254 }, { 255 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, 256 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, 257 MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 258 }, { 259 DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, 260 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, 261 MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT 262 }, { 263 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1, 264 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, 265 MT8195_SEL_IN_DSI1_FROM_VPP_MERGE 266 }, { 267 DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1, 268 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, 269 MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 270 }, { 271 DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1, 272 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, 273 MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE 274 }, { 275 DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, 276 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 277 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 278 }, { 279 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, 280 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 281 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 282 }, { 283 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, 284 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 285 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 286 }, { 287 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, 288 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 289 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 290 }, { 291 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, 292 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 293 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 294 }, { 295 DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0, 296 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 297 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 298 }, { 299 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1, 300 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 301 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 302 }, { 303 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, 304 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 305 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 306 }, { 307 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0, 308 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 309 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 310 }, { 311 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1, 312 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 313 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 314 }, { 315 DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, 316 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK, 317 MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 318 }, { 319 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, 320 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, 321 MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN 322 }, { 323 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, 324 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, 325 MT8195_SOUT_DISP_DITHER0_TO_DSI0 326 }, { 327 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1, 328 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 329 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN 330 }, { 331 DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0, 332 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 333 MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE 334 }, { 335 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1, 336 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 337 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 338 }, { 339 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, 340 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 341 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 342 }, { 343 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1, 344 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 345 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 346 }, { 347 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0, 348 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 349 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 350 }, { 351 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1, 352 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 353 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 354 }, { 355 DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0, 356 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, 357 MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE 358 }, { 359 DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0, 360 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, 361 MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 362 }, { 363 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1, 364 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 365 MT8195_SOUT_VPP_MERGE_TO_DSI1 366 }, { 367 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, 368 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 369 MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 370 }, { 371 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1, 372 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 373 MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 374 }, { 375 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, 376 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 377 MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 378 }, { 379 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1, 380 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 381 MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 382 }, { 383 DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1, 384 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 385 MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 386 }, { 387 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, 388 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 389 MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN 390 }, { 391 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1, 392 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK, 393 MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN 394 }, { 395 DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, 396 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 397 MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 398 }, { 399 DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1, 400 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 401 MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 402 }, { 403 DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0, 404 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 405 MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 406 }, { 407 DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1, 408 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 409 MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 410 }, { 411 DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, 412 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 413 MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE 414 }, { 415 DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, 416 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 417 MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 418 }, { 419 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, 420 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 421 MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 422 }, { 423 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, 424 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 425 MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 426 }, { 427 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, 428 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 429 MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 430 }, { 431 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, 432 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 433 MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 434 }, { 435 DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0, 436 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 437 MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE 438 } 439 }; 440 441 static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = { 442 { 443 DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1, 444 MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), 445 MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 446 }, { 447 DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1, 448 MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), 449 MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 450 }, { 451 DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2, 452 MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), 453 MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 454 }, { 455 DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, 456 MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), 457 MT8195_SOUT_TO_MIXER_IN1_SEL 458 }, { 459 DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, 460 MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), 461 MT8195_SOUT_TO_MIXER_IN2_SEL 462 }, { 463 DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, 464 MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), 465 MT8195_SOUT_TO_MIXER_IN3_SEL 466 }, { 467 DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, 468 MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), 469 MT8195_SOUT_TO_MIXER_IN4_SEL 470 }, { 471 DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, 472 MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), 473 MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 474 }, { 475 DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, 476 MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), 477 MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 478 }, { 479 DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, 480 MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), 481 MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 482 }, { 483 DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, 484 MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), 485 MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 486 }, { 487 DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, 488 MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), 489 MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 490 }, { 491 DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, 492 MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), 493 MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 494 }, { 495 DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, 496 MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), 497 MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 498 }, { 499 DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, 500 MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), 501 MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 502 }, { 503 DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, 504 MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), 505 MT8195_MERGE4_SOUT_TO_DPI1_SEL 506 }, { 507 DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, 508 MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), 509 MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 510 }, { 511 DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, 512 MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), 513 MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL 514 } 515 }; 516 #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */ 517