1*b804923bSjason-jh.lin /* SPDX-License-Identifier: GPL-2.0-only */ 2*b804923bSjason-jh.lin 3*b804923bSjason-jh.lin #ifndef __SOC_MEDIATEK_MT8195_MMSYS_H 4*b804923bSjason-jh.lin #define __SOC_MEDIATEK_MT8195_MMSYS_H 5*b804923bSjason-jh.lin 6*b804923bSjason-jh.lin #define MT8195_VDO0_OVL_MOUT_EN 0xf14 7*b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) 8*b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) 9*b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) 10*b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) 11*b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) 12*b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) 13*b804923bSjason-jh.lin 14*b804923bSjason-jh.lin #define MT8195_VDO0_SEL_IN 0xf34 15*b804923bSjason-jh.lin #define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0) 16*b804923bSjason-jh.lin #define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) 17*b804923bSjason-jh.lin #define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0) 18*b804923bSjason-jh.lin #define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0) 19*b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4) 20*b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4) 21*b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4) 22*b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5) 23*b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5) 24*b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5) 25*b804923bSjason-jh.lin #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8) 26*b804923bSjason-jh.lin #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8) 27*b804923bSjason-jh.lin #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8) 28*b804923bSjason-jh.lin #define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9) 29*b804923bSjason-jh.lin #define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9) 30*b804923bSjason-jh.lin #define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12) 31*b804923bSjason-jh.lin #define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0) 32*b804923bSjason-jh.lin #define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12) 33*b804923bSjason-jh.lin #define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12) 34*b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16) 35*b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16) 36*b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16) 37*b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17) 38*b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17) 39*b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17) 40*b804923bSjason-jh.lin #define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20) 41*b804923bSjason-jh.lin #define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20) 42*b804923bSjason-jh.lin #define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20) 43*b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21) 44*b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21) 45*b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21) 46*b804923bSjason-jh.lin #define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22) 47*b804923bSjason-jh.lin #define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22) 48*b804923bSjason-jh.lin 49*b804923bSjason-jh.lin #define MT8195_VDO0_SEL_OUT 0xf38 50*b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0) 51*b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) 52*b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) 53*b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1) 54*b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1) 55*b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1) 56*b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1) 57*b804923bSjason-jh.lin #define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4) 58*b804923bSjason-jh.lin #define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4) 59*b804923bSjason-jh.lin #define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4) 60*b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8) 61*b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8) 62*b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8) 63*b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8) 64*b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8) 65*b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8) 66*b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11) 67*b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11) 68*b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12) 69*b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12) 70*b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12) 71*b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12) 72*b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16) 73*b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16) 74*b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16) 75*b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) 76*b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16) 77*b804923bSjason-jh.lin 78*b804923bSjason-jh.lin static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { 79*b804923bSjason-jh.lin { 80*b804923bSjason-jh.lin DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 81*b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0, 82*b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 83*b804923bSjason-jh.lin }, { 84*b804923bSjason-jh.lin DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, 85*b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0, 86*b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 87*b804923bSjason-jh.lin }, { 88*b804923bSjason-jh.lin DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1, 89*b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1, 90*b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 91*b804923bSjason-jh.lin }, { 92*b804923bSjason-jh.lin DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1, 93*b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1, 94*b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 95*b804923bSjason-jh.lin }, { 96*b804923bSjason-jh.lin DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1, 97*b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1, 98*b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 99*b804923bSjason-jh.lin }, { 100*b804923bSjason-jh.lin DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0, 101*b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0, 102*b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 103*b804923bSjason-jh.lin }, { 104*b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, 105*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, 106*b804923bSjason-jh.lin MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT 107*b804923bSjason-jh.lin }, { 108*b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0, 109*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, 110*b804923bSjason-jh.lin MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 111*b804923bSjason-jh.lin }, { 112*b804923bSjason-jh.lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0, 113*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, 114*b804923bSjason-jh.lin MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 115*b804923bSjason-jh.lin }, { 116*b804923bSjason-jh.lin DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0, 117*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, 118*b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 119*b804923bSjason-jh.lin }, { 120*b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, 121*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, 122*b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE 123*b804923bSjason-jh.lin }, { 124*b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1, 125*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, 126*b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 127*b804923bSjason-jh.lin }, { 128*b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1, 129*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, 130*b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE 131*b804923bSjason-jh.lin }, { 132*b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1, 133*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 134*b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE 135*b804923bSjason-jh.lin }, { 136*b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, 137*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 138*b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE 139*b804923bSjason-jh.lin }, { 140*b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1, 141*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 142*b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE 143*b804923bSjason-jh.lin }, { 144*b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, 145*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 146*b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT 147*b804923bSjason-jh.lin }, { 148*b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, 149*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 150*b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT 151*b804923bSjason-jh.lin }, { 152*b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, 153*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 154*b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT 155*b804923bSjason-jh.lin }, { 156*b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1, 157*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, 158*b804923bSjason-jh.lin MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT 159*b804923bSjason-jh.lin }, { 160*b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0, 161*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, 162*b804923bSjason-jh.lin MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT 163*b804923bSjason-jh.lin }, { 164*b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1, 165*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, 166*b804923bSjason-jh.lin MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT 167*b804923bSjason-jh.lin }, { 168*b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, 169*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, 170*b804923bSjason-jh.lin MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT 171*b804923bSjason-jh.lin }, { 172*b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, 173*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, 174*b804923bSjason-jh.lin MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE 175*b804923bSjason-jh.lin }, { 176*b804923bSjason-jh.lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0, 177*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, 178*b804923bSjason-jh.lin MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 179*b804923bSjason-jh.lin }, { 180*b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, 181*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, 182*b804923bSjason-jh.lin MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT 183*b804923bSjason-jh.lin }, { 184*b804923bSjason-jh.lin DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, 185*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, 186*b804923bSjason-jh.lin MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 187*b804923bSjason-jh.lin }, { 188*b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, 189*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, 190*b804923bSjason-jh.lin MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT 191*b804923bSjason-jh.lin }, { 192*b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1, 193*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, 194*b804923bSjason-jh.lin MT8195_SEL_IN_DSI1_FROM_VPP_MERGE 195*b804923bSjason-jh.lin }, { 196*b804923bSjason-jh.lin DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1, 197*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, 198*b804923bSjason-jh.lin MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 199*b804923bSjason-jh.lin }, { 200*b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1, 201*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, 202*b804923bSjason-jh.lin MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE 203*b804923bSjason-jh.lin }, { 204*b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, 205*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 206*b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 207*b804923bSjason-jh.lin }, { 208*b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, 209*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 210*b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 211*b804923bSjason-jh.lin }, { 212*b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, 213*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 214*b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 215*b804923bSjason-jh.lin }, { 216*b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, 217*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 218*b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 219*b804923bSjason-jh.lin }, { 220*b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, 221*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 222*b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 223*b804923bSjason-jh.lin }, { 224*b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0, 225*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 226*b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 227*b804923bSjason-jh.lin }, { 228*b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1, 229*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 230*b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 231*b804923bSjason-jh.lin }, { 232*b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, 233*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 234*b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 235*b804923bSjason-jh.lin }, { 236*b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0, 237*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 238*b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 239*b804923bSjason-jh.lin }, { 240*b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1, 241*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 242*b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 243*b804923bSjason-jh.lin }, { 244*b804923bSjason-jh.lin DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, 245*b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK, 246*b804923bSjason-jh.lin MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 247*b804923bSjason-jh.lin }, { 248*b804923bSjason-jh.lin DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0, 249*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, 250*b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN 251*b804923bSjason-jh.lin }, { 252*b804923bSjason-jh.lin DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, 253*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, 254*b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER0_TO_DSI0 255*b804923bSjason-jh.lin }, { 256*b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1, 257*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 258*b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN 259*b804923bSjason-jh.lin }, { 260*b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0, 261*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 262*b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE 263*b804923bSjason-jh.lin }, { 264*b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1, 265*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 266*b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 267*b804923bSjason-jh.lin }, { 268*b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, 269*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 270*b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 271*b804923bSjason-jh.lin }, { 272*b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1, 273*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 274*b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 275*b804923bSjason-jh.lin }, { 276*b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0, 277*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 278*b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 279*b804923bSjason-jh.lin }, { 280*b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1, 281*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 282*b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 283*b804923bSjason-jh.lin }, { 284*b804923bSjason-jh.lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0, 285*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, 286*b804923bSjason-jh.lin MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE 287*b804923bSjason-jh.lin }, { 288*b804923bSjason-jh.lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0, 289*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, 290*b804923bSjason-jh.lin MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 291*b804923bSjason-jh.lin }, { 292*b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1, 293*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 294*b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_DSI1 295*b804923bSjason-jh.lin }, { 296*b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, 297*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 298*b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 299*b804923bSjason-jh.lin }, { 300*b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1, 301*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 302*b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 303*b804923bSjason-jh.lin }, { 304*b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, 305*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 306*b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 307*b804923bSjason-jh.lin }, { 308*b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1, 309*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 310*b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 311*b804923bSjason-jh.lin }, { 312*b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1, 313*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 314*b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 315*b804923bSjason-jh.lin }, { 316*b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, 317*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 318*b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN 319*b804923bSjason-jh.lin }, { 320*b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1, 321*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK, 322*b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN 323*b804923bSjason-jh.lin }, { 324*b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, 325*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 326*b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 327*b804923bSjason-jh.lin }, { 328*b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1, 329*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 330*b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 331*b804923bSjason-jh.lin }, { 332*b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0, 333*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 334*b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 335*b804923bSjason-jh.lin }, { 336*b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1, 337*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 338*b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 339*b804923bSjason-jh.lin }, { 340*b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, 341*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 342*b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE 343*b804923bSjason-jh.lin }, { 344*b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, 345*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 346*b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 347*b804923bSjason-jh.lin }, { 348*b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, 349*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 350*b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 351*b804923bSjason-jh.lin }, { 352*b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, 353*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 354*b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 355*b804923bSjason-jh.lin }, { 356*b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, 357*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 358*b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 359*b804923bSjason-jh.lin }, { 360*b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, 361*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 362*b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 363*b804923bSjason-jh.lin }, { 364*b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0, 365*b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 366*b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE 367*b804923bSjason-jh.lin } 368*b804923bSjason-jh.lin }; 369*b804923bSjason-jh.lin 370*b804923bSjason-jh.lin #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */ 371