1b804923bSjason-jh.lin /* SPDX-License-Identifier: GPL-2.0-only */ 2b804923bSjason-jh.lin 3b804923bSjason-jh.lin #ifndef __SOC_MEDIATEK_MT8195_MMSYS_H 4b804923bSjason-jh.lin #define __SOC_MEDIATEK_MT8195_MMSYS_H 5b804923bSjason-jh.lin 6b804923bSjason-jh.lin #define MT8195_VDO0_OVL_MOUT_EN 0xf14 7b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) 8b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) 9b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) 10b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) 11b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) 12b804923bSjason-jh.lin #define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) 13b804923bSjason-jh.lin 14b804923bSjason-jh.lin #define MT8195_VDO0_SEL_IN 0xf34 15b804923bSjason-jh.lin #define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0) 16b804923bSjason-jh.lin #define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) 17b804923bSjason-jh.lin #define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0) 18b804923bSjason-jh.lin #define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0) 19b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4) 20b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4) 21b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4) 22b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5) 23b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5) 24b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5) 25b804923bSjason-jh.lin #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8) 26b804923bSjason-jh.lin #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8) 27b804923bSjason-jh.lin #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8) 28b804923bSjason-jh.lin #define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9) 29b804923bSjason-jh.lin #define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9) 30b804923bSjason-jh.lin #define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12) 31b804923bSjason-jh.lin #define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0) 32b804923bSjason-jh.lin #define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12) 33b804923bSjason-jh.lin #define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12) 34b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16) 35b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16) 36b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16) 37b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17) 38b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17) 39b804923bSjason-jh.lin #define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17) 40b804923bSjason-jh.lin #define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20) 41b804923bSjason-jh.lin #define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20) 42b804923bSjason-jh.lin #define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20) 43b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21) 44b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21) 45b804923bSjason-jh.lin #define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21) 46b804923bSjason-jh.lin #define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22) 47b804923bSjason-jh.lin #define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22) 48b804923bSjason-jh.lin 49b804923bSjason-jh.lin #define MT8195_VDO0_SEL_OUT 0xf38 50b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0) 51b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) 52b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) 53b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1) 54b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1) 55b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1) 56b804923bSjason-jh.lin #define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1) 57b804923bSjason-jh.lin #define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4) 58b804923bSjason-jh.lin #define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4) 59b804923bSjason-jh.lin #define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4) 60b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8) 61b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8) 62b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8) 63b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8) 64b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8) 65b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8) 66b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11) 67b804923bSjason-jh.lin #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11) 68b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12) 69b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12) 70b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12) 71b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12) 72b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16) 73b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16) 74b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16) 75b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) 76b804923bSjason-jh.lin #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16) 77b804923bSjason-jh.lin 78*39170127SNancy.Lin #define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 79*39170127SNancy.Lin #define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1 80*39170127SNancy.Lin 81*39170127SNancy.Lin #define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08 82*39170127SNancy.Lin #define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1 83*39170127SNancy.Lin 84*39170127SNancy.Lin #define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10 85*39170127SNancy.Lin #define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0 86*39170127SNancy.Lin 87*39170127SNancy.Lin #define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14 88*39170127SNancy.Lin #define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0 89*39170127SNancy.Lin 90*39170127SNancy.Lin #define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18 91*39170127SNancy.Lin #define MT8195_MERGE4_SOUT_TO_DPI1_SEL 2 92*39170127SNancy.Lin #define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL 3 93*39170127SNancy.Lin 94*39170127SNancy.Lin #define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24 95*39170127SNancy.Lin #define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1 96*39170127SNancy.Lin 97*39170127SNancy.Lin #define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28 98*39170127SNancy.Lin #define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1 99*39170127SNancy.Lin 100*39170127SNancy.Lin #define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c 101*39170127SNancy.Lin #define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1 102*39170127SNancy.Lin 103*39170127SNancy.Lin #define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30 104*39170127SNancy.Lin #define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1 105*39170127SNancy.Lin 106*39170127SNancy.Lin #define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34 107*39170127SNancy.Lin #define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1 108*39170127SNancy.Lin 109*39170127SNancy.Lin #define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c 110*39170127SNancy.Lin #define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1 111*39170127SNancy.Lin 112*39170127SNancy.Lin #define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 113*39170127SNancy.Lin #define MT8195_SOUT_TO_MIXER_IN1_SEL 1 114*39170127SNancy.Lin 115*39170127SNancy.Lin #define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 116*39170127SNancy.Lin #define MT8195_SOUT_TO_MIXER_IN2_SEL 1 117*39170127SNancy.Lin 118*39170127SNancy.Lin #define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 119*39170127SNancy.Lin #define MT8195_SOUT_TO_MIXER_IN3_SEL 1 120*39170127SNancy.Lin 121*39170127SNancy.Lin #define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c 122*39170127SNancy.Lin #define MT8195_SOUT_TO_MIXER_IN4_SEL 1 123*39170127SNancy.Lin 124*39170127SNancy.Lin #define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50 125*39170127SNancy.Lin #define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1 126*39170127SNancy.Lin 127*39170127SNancy.Lin #define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58 128*39170127SNancy.Lin #define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER 0 129*39170127SNancy.Lin 130*39170127SNancy.Lin #define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c 131*39170127SNancy.Lin #define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER 0 132*39170127SNancy.Lin 133*39170127SNancy.Lin #define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60 134*39170127SNancy.Lin #define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER 0 135*39170127SNancy.Lin 136*39170127SNancy.Lin #define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64 137*39170127SNancy.Lin #define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER 0 138*39170127SNancy.Lin 139*39170127SNancy.Lin #define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68 140*39170127SNancy.Lin #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 141*39170127SNancy.Lin 142b804923bSjason-jh.lin static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { 143b804923bSjason-jh.lin { 144b804923bSjason-jh.lin DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 145b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0, 146b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 147b804923bSjason-jh.lin }, { 148b804923bSjason-jh.lin DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, 149b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0, 150b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 151b804923bSjason-jh.lin }, { 152b804923bSjason-jh.lin DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1, 153b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1, 154b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 155b804923bSjason-jh.lin }, { 156b804923bSjason-jh.lin DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1, 157b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1, 158b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 159b804923bSjason-jh.lin }, { 160b804923bSjason-jh.lin DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1, 161b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1, 162b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 163b804923bSjason-jh.lin }, { 164b804923bSjason-jh.lin DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0, 165b804923bSjason-jh.lin MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0, 166b804923bSjason-jh.lin MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 167b804923bSjason-jh.lin }, { 168b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, 169b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, 170b804923bSjason-jh.lin MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT 171b804923bSjason-jh.lin }, { 172b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0, 173b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, 174b804923bSjason-jh.lin MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 175b804923bSjason-jh.lin }, { 176b804923bSjason-jh.lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0, 177b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, 178b804923bSjason-jh.lin MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 179b804923bSjason-jh.lin }, { 1804e8988c6Sjason-jh.lin DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, 181b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, 182b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 183b804923bSjason-jh.lin }, { 184b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, 185b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, 186b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE 187b804923bSjason-jh.lin }, { 188b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1, 189b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, 190b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 191b804923bSjason-jh.lin }, { 192b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1, 193b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, 194b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE 195b804923bSjason-jh.lin }, { 196b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1, 197b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 198b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE 199b804923bSjason-jh.lin }, { 200b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, 201b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 202b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE 203b804923bSjason-jh.lin }, { 204b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1, 205b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 206b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE 207b804923bSjason-jh.lin }, { 208b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, 209b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 210b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT 211b804923bSjason-jh.lin }, { 212b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, 213b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 214b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT 215b804923bSjason-jh.lin }, { 216b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, 217b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 218b804923bSjason-jh.lin MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT 219b804923bSjason-jh.lin }, { 220b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1, 221b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, 222b804923bSjason-jh.lin MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT 223b804923bSjason-jh.lin }, { 224b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0, 225b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, 226b804923bSjason-jh.lin MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT 227b804923bSjason-jh.lin }, { 228b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1, 229b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, 230b804923bSjason-jh.lin MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT 231b804923bSjason-jh.lin }, { 232b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, 233b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, 234b804923bSjason-jh.lin MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT 235b804923bSjason-jh.lin }, { 236b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, 237b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, 238b804923bSjason-jh.lin MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE 239b804923bSjason-jh.lin }, { 240b804923bSjason-jh.lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0, 241b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, 242b804923bSjason-jh.lin MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 243b804923bSjason-jh.lin }, { 244b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, 245b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, 246b804923bSjason-jh.lin MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT 247b804923bSjason-jh.lin }, { 2484e8988c6Sjason-jh.lin DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, 249b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, 250b804923bSjason-jh.lin MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 251b804923bSjason-jh.lin }, { 252b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, 253b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, 254b804923bSjason-jh.lin MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT 255b804923bSjason-jh.lin }, { 256b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1, 257b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, 258b804923bSjason-jh.lin MT8195_SEL_IN_DSI1_FROM_VPP_MERGE 259b804923bSjason-jh.lin }, { 260b804923bSjason-jh.lin DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1, 261b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, 262b804923bSjason-jh.lin MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 263b804923bSjason-jh.lin }, { 264b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1, 265b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, 266b804923bSjason-jh.lin MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE 267b804923bSjason-jh.lin }, { 268b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, 269b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 270b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 271b804923bSjason-jh.lin }, { 272b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, 273b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 274b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 275b804923bSjason-jh.lin }, { 276b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, 277b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 278b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 279b804923bSjason-jh.lin }, { 280b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, 281b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 282b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 283b804923bSjason-jh.lin }, { 284b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, 285b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 286b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 287b804923bSjason-jh.lin }, { 288b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0, 289b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 290b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN 291b804923bSjason-jh.lin }, { 292b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1, 293b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 294b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 295b804923bSjason-jh.lin }, { 296b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, 297b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 298b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 299b804923bSjason-jh.lin }, { 300b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0, 301b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 302b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 303b804923bSjason-jh.lin }, { 304b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1, 305b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 306b804923bSjason-jh.lin MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 307b804923bSjason-jh.lin }, { 308b804923bSjason-jh.lin DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, 309b804923bSjason-jh.lin MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK, 310b804923bSjason-jh.lin MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 311b804923bSjason-jh.lin }, { 3124e8988c6Sjason-jh.lin DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, 313b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, 314b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN 315b804923bSjason-jh.lin }, { 3164e8988c6Sjason-jh.lin DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, 317b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, 318b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER0_TO_DSI0 319b804923bSjason-jh.lin }, { 320b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1, 321b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 322b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN 323b804923bSjason-jh.lin }, { 324b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0, 325b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 326b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE 327b804923bSjason-jh.lin }, { 328b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1, 329b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 330b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 331b804923bSjason-jh.lin }, { 332b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, 333b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 334b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 335b804923bSjason-jh.lin }, { 336b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1, 337b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 338b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 339b804923bSjason-jh.lin }, { 340b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0, 341b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 342b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 343b804923bSjason-jh.lin }, { 344b804923bSjason-jh.lin DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1, 345b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 346b804923bSjason-jh.lin MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT 347b804923bSjason-jh.lin }, { 348b804923bSjason-jh.lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0, 349b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, 350b804923bSjason-jh.lin MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE 351b804923bSjason-jh.lin }, { 352b804923bSjason-jh.lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0, 353b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, 354b804923bSjason-jh.lin MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 355b804923bSjason-jh.lin }, { 356b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1, 357b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 358b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_DSI1 359b804923bSjason-jh.lin }, { 360b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, 361b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 362b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 363b804923bSjason-jh.lin }, { 364b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1, 365b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 366b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 367b804923bSjason-jh.lin }, { 368b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, 369b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 370b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 371b804923bSjason-jh.lin }, { 372b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1, 373b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 374b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 375b804923bSjason-jh.lin }, { 376b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1, 377b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 378b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 379b804923bSjason-jh.lin }, { 380b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, 381b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 382b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN 383b804923bSjason-jh.lin }, { 384b804923bSjason-jh.lin DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1, 385b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK, 386b804923bSjason-jh.lin MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN 387b804923bSjason-jh.lin }, { 388b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, 389b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 390b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 391b804923bSjason-jh.lin }, { 392b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1, 393b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 394b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 395b804923bSjason-jh.lin }, { 396b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0, 397b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 398b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 399b804923bSjason-jh.lin }, { 400b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1, 401b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 402b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 403b804923bSjason-jh.lin }, { 404b804923bSjason-jh.lin DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, 405b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 406b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE 407b804923bSjason-jh.lin }, { 408b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, 409b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 410b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 411b804923bSjason-jh.lin }, { 412b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, 413b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 414b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 415b804923bSjason-jh.lin }, { 416b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, 417b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 418b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 419b804923bSjason-jh.lin }, { 420b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, 421b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 422b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 423b804923bSjason-jh.lin }, { 424b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, 425b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 426b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 427b804923bSjason-jh.lin }, { 428b804923bSjason-jh.lin DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0, 429b804923bSjason-jh.lin MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 430b804923bSjason-jh.lin MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE 431b804923bSjason-jh.lin } 432b804923bSjason-jh.lin }; 433b804923bSjason-jh.lin 434*39170127SNancy.Lin static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = { 435*39170127SNancy.Lin { 436*39170127SNancy.Lin DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1, 437*39170127SNancy.Lin MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), 438*39170127SNancy.Lin MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 439*39170127SNancy.Lin }, { 440*39170127SNancy.Lin DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1, 441*39170127SNancy.Lin MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), 442*39170127SNancy.Lin MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 443*39170127SNancy.Lin }, { 444*39170127SNancy.Lin DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2, 445*39170127SNancy.Lin MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), 446*39170127SNancy.Lin MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 447*39170127SNancy.Lin }, { 448*39170127SNancy.Lin DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, 449*39170127SNancy.Lin MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), 450*39170127SNancy.Lin MT8195_SOUT_TO_MIXER_IN1_SEL 451*39170127SNancy.Lin }, { 452*39170127SNancy.Lin DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, 453*39170127SNancy.Lin MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), 454*39170127SNancy.Lin MT8195_SOUT_TO_MIXER_IN2_SEL 455*39170127SNancy.Lin }, { 456*39170127SNancy.Lin DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, 457*39170127SNancy.Lin MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), 458*39170127SNancy.Lin MT8195_SOUT_TO_MIXER_IN3_SEL 459*39170127SNancy.Lin }, { 460*39170127SNancy.Lin DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, 461*39170127SNancy.Lin MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), 462*39170127SNancy.Lin MT8195_SOUT_TO_MIXER_IN4_SEL 463*39170127SNancy.Lin }, { 464*39170127SNancy.Lin DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, 465*39170127SNancy.Lin MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), 466*39170127SNancy.Lin MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 467*39170127SNancy.Lin }, { 468*39170127SNancy.Lin DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, 469*39170127SNancy.Lin MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), 470*39170127SNancy.Lin MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 471*39170127SNancy.Lin }, { 472*39170127SNancy.Lin DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, 473*39170127SNancy.Lin MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), 474*39170127SNancy.Lin MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 475*39170127SNancy.Lin }, { 476*39170127SNancy.Lin DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, 477*39170127SNancy.Lin MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), 478*39170127SNancy.Lin MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 479*39170127SNancy.Lin }, { 480*39170127SNancy.Lin DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, 481*39170127SNancy.Lin MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), 482*39170127SNancy.Lin MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 483*39170127SNancy.Lin }, { 484*39170127SNancy.Lin DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, 485*39170127SNancy.Lin MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), 486*39170127SNancy.Lin MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 487*39170127SNancy.Lin }, { 488*39170127SNancy.Lin DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, 489*39170127SNancy.Lin MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), 490*39170127SNancy.Lin MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 491*39170127SNancy.Lin }, { 492*39170127SNancy.Lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, 493*39170127SNancy.Lin MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), 494*39170127SNancy.Lin MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 495*39170127SNancy.Lin }, { 496*39170127SNancy.Lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, 497*39170127SNancy.Lin MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), 498*39170127SNancy.Lin MT8195_MERGE4_SOUT_TO_DPI1_SEL 499*39170127SNancy.Lin }, { 500*39170127SNancy.Lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, 501*39170127SNancy.Lin MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), 502*39170127SNancy.Lin MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 503*39170127SNancy.Lin }, { 504*39170127SNancy.Lin DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, 505*39170127SNancy.Lin MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), 506*39170127SNancy.Lin MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL 507*39170127SNancy.Lin } 508*39170127SNancy.Lin }; 509b804923bSjason-jh.lin #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */ 510