1*3b1a57c4SNathan Lu /* SPDX-License-Identifier: GPL-2.0-only */ 2*3b1a57c4SNathan Lu 3*3b1a57c4SNathan Lu #ifndef __SOC_MEDIATEK_MT8188_MMSYS_H 4*3b1a57c4SNathan Lu #define __SOC_MEDIATEK_MT8188_MMSYS_H 5*3b1a57c4SNathan Lu 6*3b1a57c4SNathan Lu #define MT8188_VDO0_OVL_MOUT_EN 0xf14 7*3b1a57c4SNathan Lu #define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) 8*3b1a57c4SNathan Lu #define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) 9*3b1a57c4SNathan Lu #define MT8188_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) 10*3b1a57c4SNathan Lu #define MT8188_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) 11*3b1a57c4SNathan Lu #define MT8188_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) 12*3b1a57c4SNathan Lu #define MT8188_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) 13*3b1a57c4SNathan Lu 14*3b1a57c4SNathan Lu #define MT8188_VDO0_SEL_IN 0xf34 15*3b1a57c4SNathan Lu #define MT8188_VDO0_SEL_OUT 0xf38 16*3b1a57c4SNathan Lu 17*3b1a57c4SNathan Lu #define MT8188_VDO0_DISP_RDMA_SEL 0xf40 18*3b1a57c4SNathan Lu #define MT8188_SOUT_DISP_RDMA0_TO_MASK GENMASK(2, 0) 19*3b1a57c4SNathan Lu #define MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0 (0 << 0) 20*3b1a57c4SNathan Lu #define MT8188_SOUT_DISP_RDMA0_TO_DISP_DSI0 (1 << 0) 21*3b1a57c4SNathan Lu #define MT8188_SOUT_DISP_RDMA0_TO_DISP_DP_INTF0 (5 << 0) 22*3b1a57c4SNathan Lu #define MT8188_SEL_IN_DISP_RDMA0_FROM_MASK GENMASK(8, 8) 23*3b1a57c4SNathan Lu #define MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0 (0 << 8) 24*3b1a57c4SNathan Lu #define MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_RSZ0 (1 << 8) 25*3b1a57c4SNathan Lu 26*3b1a57c4SNathan Lu 27*3b1a57c4SNathan Lu #define MT8188_VDO0_DSI0_SEL_IN 0xf44 28*3b1a57c4SNathan Lu #define MT8188_SEL_IN_DSI0_FROM_MASK BIT(0) 29*3b1a57c4SNathan Lu #define MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 0) 30*3b1a57c4SNathan Lu #define MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 0) 31*3b1a57c4SNathan Lu 32*3b1a57c4SNathan Lu #define MT8188_VDO0_DP_INTF0_SEL_IN 0xf4C 33*3b1a57c4SNathan Lu #define MT8188_SEL_IN_DP_INTF0_FROM_MASK GENMASK(2, 0) 34*3b1a57c4SNathan Lu #define MT8188_SEL_IN_DP_INTF0_FROM_DSC_WRAP0C1_OUT (0 << 0) 35*3b1a57c4SNathan Lu #define MT8188_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 0) 36*3b1a57c4SNathan Lu #define MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0 (3 << 0) 37*3b1a57c4SNathan Lu 38*3b1a57c4SNathan Lu #define MT8188_VDO0_DISP_DITHER0_SEL_OUT 0xf58 39*3b1a57c4SNathan Lu #define MT8188_SOUT_DISP_DITHER0_TO_MASK GENMASK(2, 0) 40*3b1a57c4SNathan Lu #define MT8188_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) 41*3b1a57c4SNathan Lu #define MT8188_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) 42*3b1a57c4SNathan Lu #define MT8188_SOUT_DISP_DITHER0_TO_VPP_MERGE0 (6 << 0) 43*3b1a57c4SNathan Lu #define MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0 (7 << 0) 44*3b1a57c4SNathan Lu 45*3b1a57c4SNathan Lu #define MT8188_VDO0_VPP_MERGE_SEL 0xf60 46*3b1a57c4SNathan Lu #define MT8188_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0) 47*3b1a57c4SNathan Lu #define MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) 48*3b1a57c4SNathan Lu #define MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT (3 << 0) 49*3b1a57c4SNathan Lu 50*3b1a57c4SNathan Lu #define MT8188_SOUT_VPP_MERGE_TO_MASK GENMASK(6, 4) 51*3b1a57c4SNathan Lu #define MT8188_SOUT_VPP_MERGE_TO_DSI1 (0 << 4) 52*3b1a57c4SNathan Lu #define MT8188_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 4) 53*3b1a57c4SNathan Lu #define MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 4) 54*3b1a57c4SNathan Lu #define MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 4) 55*3b1a57c4SNathan Lu #define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 4) 56*3b1a57c4SNathan Lu #define MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0 (5 << 4) 57*3b1a57c4SNathan Lu #define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11) 58*3b1a57c4SNathan Lu #define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11) 59*3b1a57c4SNathan Lu 60*3b1a57c4SNathan Lu #define MT8188_VDO0_DSC_WARP_SEL 0xf64 61*3b1a57c4SNathan Lu #define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK GENMASK(0, 0) 62*3b1a57c4SNathan Lu #define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0 (0 << 0) 63*3b1a57c4SNathan Lu #define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_VPP_MERGE (1 << 0) 64*3b1a57c4SNathan Lu #define MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(19, 16) 65*3b1a57c4SNathan Lu #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0 BIT(16) 66*3b1a57c4SNathan Lu #define MT8188_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 BIT(17) 67*3b1a57c4SNathan Lu #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18) 68*3b1a57c4SNathan Lu #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19) 69*3b1a57c4SNathan Lu 70*3b1a57c4SNathan Lu static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { 71*3b1a57c4SNathan Lu { 72*3b1a57c4SNathan Lu DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 73*3b1a57c4SNathan Lu MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0, 74*3b1a57c4SNathan Lu MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 75*3b1a57c4SNathan Lu }, { 76*3b1a57c4SNathan Lu DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, 77*3b1a57c4SNathan Lu MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0, 78*3b1a57c4SNathan Lu MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 79*3b1a57c4SNathan Lu }, { 80*3b1a57c4SNathan Lu DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 81*3b1a57c4SNathan Lu MT8188_VDO0_DISP_RDMA_SEL, MT8188_SEL_IN_DISP_RDMA0_FROM_MASK, 82*3b1a57c4SNathan Lu MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0 83*3b1a57c4SNathan Lu }, { 84*3b1a57c4SNathan Lu DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, 85*3b1a57c4SNathan Lu MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK, 86*3b1a57c4SNathan Lu MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0 87*3b1a57c4SNathan Lu }, { 88*3b1a57c4SNathan Lu DDP_COMPONENT_DITHER0, DDP_COMPONENT_MERGE0, 89*3b1a57c4SNathan Lu MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK, 90*3b1a57c4SNathan Lu MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT 91*3b1a57c4SNathan Lu }, { 92*3b1a57c4SNathan Lu DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, 93*3b1a57c4SNathan Lu MT8188_VDO0_DSC_WARP_SEL, 94*3b1a57c4SNathan Lu MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK, 95*3b1a57c4SNathan Lu MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0 96*3b1a57c4SNathan Lu }, { 97*3b1a57c4SNathan Lu DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0, 98*3b1a57c4SNathan Lu MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK, 99*3b1a57c4SNathan Lu MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0 100*3b1a57c4SNathan Lu }, { 101*3b1a57c4SNathan Lu DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, 102*3b1a57c4SNathan Lu MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK, 103*3b1a57c4SNathan Lu MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT 104*3b1a57c4SNathan Lu }, { 105*3b1a57c4SNathan Lu DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, 106*3b1a57c4SNathan Lu MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK, 107*3b1a57c4SNathan Lu MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT 108*3b1a57c4SNathan Lu }, { 109*3b1a57c4SNathan Lu DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, 110*3b1a57c4SNathan Lu MT8188_VDO0_DISP_RDMA_SEL, MT8188_SOUT_DISP_RDMA0_TO_MASK, 111*3b1a57c4SNathan Lu MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0 112*3b1a57c4SNathan Lu }, { 113*3b1a57c4SNathan Lu DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, 114*3b1a57c4SNathan Lu MT8188_VDO0_DISP_DITHER0_SEL_OUT, 115*3b1a57c4SNathan Lu MT8188_SOUT_DISP_DITHER0_TO_MASK, 116*3b1a57c4SNathan Lu MT8188_SOUT_DISP_DITHER0_TO_DSI0 117*3b1a57c4SNathan Lu }, { 118*3b1a57c4SNathan Lu DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0, 119*3b1a57c4SNathan Lu MT8188_VDO0_DISP_DITHER0_SEL_OUT, 120*3b1a57c4SNathan Lu MT8188_SOUT_DISP_DITHER0_TO_MASK, 121*3b1a57c4SNathan Lu MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0 122*3b1a57c4SNathan Lu }, { 123*3b1a57c4SNathan Lu DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, 124*3b1a57c4SNathan Lu MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, 125*3b1a57c4SNathan Lu MT8188_SOUT_VPP_MERGE_TO_DP_INTF0 126*3b1a57c4SNathan Lu }, { 127*3b1a57c4SNathan Lu DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, 128*3b1a57c4SNathan Lu MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, 129*3b1a57c4SNathan Lu MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 130*3b1a57c4SNathan Lu }, { 131*3b1a57c4SNathan Lu DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA0, 132*3b1a57c4SNathan Lu MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, 133*3b1a57c4SNathan Lu MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0 134*3b1a57c4SNathan Lu }, { 135*3b1a57c4SNathan Lu DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, 136*3b1a57c4SNathan Lu MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, 137*3b1a57c4SNathan Lu MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN 138*3b1a57c4SNathan Lu }, { 139*3b1a57c4SNathan Lu DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, 140*3b1a57c4SNathan Lu MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK, 141*3b1a57c4SNathan Lu MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0 142*3b1a57c4SNathan Lu }, { 143*3b1a57c4SNathan Lu DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, 144*3b1a57c4SNathan Lu MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK, 145*3b1a57c4SNathan Lu MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE 146*3b1a57c4SNathan Lu }, 147*3b1a57c4SNathan Lu }; 148*3b1a57c4SNathan Lu 149*3b1a57c4SNathan Lu #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */ 150