1*5f9b5b75SYongqiang Niu /* SPDX-License-Identifier: GPL-2.0-only */ 2*5f9b5b75SYongqiang Niu 3*5f9b5b75SYongqiang Niu #ifndef __SOC_MEDIATEK_MT8186_MMSYS_H 4*5f9b5b75SYongqiang Niu #define __SOC_MEDIATEK_MT8186_MMSYS_H 5*5f9b5b75SYongqiang Niu 6*5f9b5b75SYongqiang Niu #define MT8186_MMSYS_OVL_CON 0xF04 7*5f9b5b75SYongqiang Niu #define MT8186_MMSYS_OVL0_CON_MASK 0x3 8*5f9b5b75SYongqiang Niu #define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC 9*5f9b5b75SYongqiang Niu #define MT8186_OVL0_GO_BLEND BIT(0) 10*5f9b5b75SYongqiang Niu #define MT8186_OVL0_GO_BG BIT(1) 11*5f9b5b75SYongqiang Niu #define MT8186_OVL0_2L_GO_BLEND BIT(2) 12*5f9b5b75SYongqiang Niu #define MT8186_OVL0_2L_GO_BG BIT(3) 13*5f9b5b75SYongqiang Niu #define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C 14*5f9b5b75SYongqiang Niu #define MT8186_RDMA0_SOUT_SEL_MASK 0xF 15*5f9b5b75SYongqiang Niu #define MT8186_RDMA0_SOUT_TO_DSI0 (0) 16*5f9b5b75SYongqiang Niu #define MT8186_RDMA0_SOUT_TO_COLOR0 (1) 17*5f9b5b75SYongqiang Niu #define MT8186_RDMA0_SOUT_TO_DPI0 (2) 18*5f9b5b75SYongqiang Niu #define MT8186_DISP_OVL0_2L_MOUT_EN 0xF14 19*5f9b5b75SYongqiang Niu #define MT8186_OVL0_2L_MOUT_EN_MASK 0xF 20*5f9b5b75SYongqiang Niu #define MT8186_OVL0_2L_MOUT_TO_RDMA0 BIT(0) 21*5f9b5b75SYongqiang Niu #define MT8186_OVL0_2L_MOUT_TO_RDMA1 BIT(3) 22*5f9b5b75SYongqiang Niu #define MT8186_DISP_OVL0_MOUT_EN 0xF18 23*5f9b5b75SYongqiang Niu #define MT8186_OVL0_MOUT_EN_MASK 0xF 24*5f9b5b75SYongqiang Niu #define MT8186_OVL0_MOUT_TO_RDMA0 BIT(0) 25*5f9b5b75SYongqiang Niu #define MT8186_OVL0_MOUT_TO_RDMA1 BIT(3) 26*5f9b5b75SYongqiang Niu #define MT8186_DISP_DITHER0_MOUT_EN 0xF20 27*5f9b5b75SYongqiang Niu #define MT8186_DITHER0_MOUT_EN_MASK 0xF 28*5f9b5b75SYongqiang Niu #define MT8186_DITHER0_MOUT_TO_DSI0 BIT(0) 29*5f9b5b75SYongqiang Niu #define MT8186_DITHER0_MOUT_TO_RDMA1 BIT(2) 30*5f9b5b75SYongqiang Niu #define MT8186_DITHER0_MOUT_TO_DPI0 BIT(3) 31*5f9b5b75SYongqiang Niu #define MT8186_DISP_RDMA0_SEL_IN 0xF28 32*5f9b5b75SYongqiang Niu #define MT8186_RDMA0_SEL_IN_MASK 0xF 33*5f9b5b75SYongqiang Niu #define MT8186_RDMA0_FROM_OVL0 0 34*5f9b5b75SYongqiang Niu #define MT8186_RDMA0_FROM_OVL0_2L 2 35*5f9b5b75SYongqiang Niu #define MT8186_DISP_DSI0_SEL_IN 0xF30 36*5f9b5b75SYongqiang Niu #define MT8186_DSI0_SEL_IN_MASK 0xF 37*5f9b5b75SYongqiang Niu #define MT8186_DSI0_FROM_RDMA0 0 38*5f9b5b75SYongqiang Niu #define MT8186_DSI0_FROM_DITHER0 1 39*5f9b5b75SYongqiang Niu #define MT8186_DSI0_FROM_RDMA1 2 40*5f9b5b75SYongqiang Niu #define MT8186_DISP_RDMA1_MOUT_EN 0xF3C 41*5f9b5b75SYongqiang Niu #define MT8186_RDMA1_MOUT_EN_MASK 0xF 42*5f9b5b75SYongqiang Niu #define MT8186_RDMA1_MOUT_TO_DPI0_SEL BIT(0) 43*5f9b5b75SYongqiang Niu #define MT8186_RDMA1_MOUT_TO_DSI0_SEL BIT(2) 44*5f9b5b75SYongqiang Niu #define MT8186_DISP_RDMA1_SEL_IN 0xF40 45*5f9b5b75SYongqiang Niu #define MT8186_RDMA1_SEL_IN_MASK 0xF 46*5f9b5b75SYongqiang Niu #define MT8186_RDMA1_FROM_OVL0 0 47*5f9b5b75SYongqiang Niu #define MT8186_RDMA1_FROM_OVL0_2L 2 48*5f9b5b75SYongqiang Niu #define MT8186_RDMA1_FROM_DITHER0 3 49*5f9b5b75SYongqiang Niu #define MT8186_DISP_DPI0_SEL_IN 0xF44 50*5f9b5b75SYongqiang Niu #define MT8186_DPI0_SEL_IN_MASK 0xF 51*5f9b5b75SYongqiang Niu #define MT8186_DPI0_FROM_RDMA1 0 52*5f9b5b75SYongqiang Niu #define MT8186_DPI0_FROM_DITHER0 1 53*5f9b5b75SYongqiang Niu #define MT8186_DPI0_FROM_RDMA0 2 54*5f9b5b75SYongqiang Niu 55*5f9b5b75SYongqiang Niu static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = { 56*5f9b5b75SYongqiang Niu { 57*5f9b5b75SYongqiang Niu DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 58*5f9b5b75SYongqiang Niu MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK, 59*5f9b5b75SYongqiang Niu MT8186_OVL0_MOUT_TO_RDMA0 60*5f9b5b75SYongqiang Niu }, 61*5f9b5b75SYongqiang Niu { 62*5f9b5b75SYongqiang Niu DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 63*5f9b5b75SYongqiang Niu MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK, 64*5f9b5b75SYongqiang Niu MT8186_RDMA0_FROM_OVL0 65*5f9b5b75SYongqiang Niu }, 66*5f9b5b75SYongqiang Niu { 67*5f9b5b75SYongqiang Niu DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 68*5f9b5b75SYongqiang Niu MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK, 69*5f9b5b75SYongqiang Niu MT8186_OVL0_GO_BLEND 70*5f9b5b75SYongqiang Niu }, 71*5f9b5b75SYongqiang Niu { 72*5f9b5b75SYongqiang Niu DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, 73*5f9b5b75SYongqiang Niu MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK, 74*5f9b5b75SYongqiang Niu MT8186_RDMA0_SOUT_TO_COLOR0 75*5f9b5b75SYongqiang Niu }, 76*5f9b5b75SYongqiang Niu { 77*5f9b5b75SYongqiang Niu DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, 78*5f9b5b75SYongqiang Niu MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK, 79*5f9b5b75SYongqiang Niu MT8186_DITHER0_MOUT_TO_DSI0, 80*5f9b5b75SYongqiang Niu }, 81*5f9b5b75SYongqiang Niu { 82*5f9b5b75SYongqiang Niu DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, 83*5f9b5b75SYongqiang Niu MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK, 84*5f9b5b75SYongqiang Niu MT8186_DSI0_FROM_DITHER0 85*5f9b5b75SYongqiang Niu }, 86*5f9b5b75SYongqiang Niu { 87*5f9b5b75SYongqiang Niu DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, 88*5f9b5b75SYongqiang Niu MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK, 89*5f9b5b75SYongqiang Niu MT8186_OVL0_2L_MOUT_TO_RDMA1 90*5f9b5b75SYongqiang Niu }, 91*5f9b5b75SYongqiang Niu { 92*5f9b5b75SYongqiang Niu DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, 93*5f9b5b75SYongqiang Niu MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK, 94*5f9b5b75SYongqiang Niu MT8186_RDMA1_FROM_OVL0_2L 95*5f9b5b75SYongqiang Niu }, 96*5f9b5b75SYongqiang Niu { 97*5f9b5b75SYongqiang Niu DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, 98*5f9b5b75SYongqiang Niu MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK, 99*5f9b5b75SYongqiang Niu MT8186_OVL0_2L_GO_BLEND 100*5f9b5b75SYongqiang Niu }, 101*5f9b5b75SYongqiang Niu { 102*5f9b5b75SYongqiang Niu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, 103*5f9b5b75SYongqiang Niu MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK, 104*5f9b5b75SYongqiang Niu MT8186_RDMA1_MOUT_TO_DPI0_SEL 105*5f9b5b75SYongqiang Niu }, 106*5f9b5b75SYongqiang Niu { 107*5f9b5b75SYongqiang Niu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, 108*5f9b5b75SYongqiang Niu MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK, 109*5f9b5b75SYongqiang Niu MT8186_DPI0_FROM_RDMA1 110*5f9b5b75SYongqiang Niu }, 111*5f9b5b75SYongqiang Niu }; 112*5f9b5b75SYongqiang Niu 113*5f9b5b75SYongqiang Niu #endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */ 114