1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2019 NXP. 4 */ 5 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/of_address.h> 9 #include <linux/slab.h> 10 #include <linux/sys_soc.h> 11 #include <linux/platform_device.h> 12 #include <linux/arm-smccc.h> 13 #include <linux/of.h> 14 #include <linux/clk.h> 15 16 #define REV_B1 0x21 17 18 #define IMX8MQ_SW_INFO_B1 0x40 19 #define IMX8MQ_SW_MAGIC_B1 0xff0055aa 20 21 #define IMX_SIP_GET_SOC_INFO 0xc2000006 22 23 #define OCOTP_UID_LOW 0x410 24 #define OCOTP_UID_HIGH 0x420 25 26 #define IMX8MP_OCOTP_UID_OFFSET 0x10 27 28 /* Same as ANADIG_DIGPROG_IMX7D */ 29 #define ANADIG_DIGPROG_IMX8MM 0x800 30 31 struct imx8_soc_data { 32 char *name; 33 u32 (*soc_revision)(void); 34 }; 35 36 static u64 soc_uid; 37 38 #ifdef CONFIG_HAVE_ARM_SMCCC 39 static u32 imx8mq_soc_revision_from_atf(void) 40 { 41 struct arm_smccc_res res; 42 43 arm_smccc_smc(IMX_SIP_GET_SOC_INFO, 0, 0, 0, 0, 0, 0, 0, &res); 44 45 if (res.a0 == SMCCC_RET_NOT_SUPPORTED) 46 return 0; 47 else 48 return res.a0 & 0xff; 49 } 50 #else 51 static inline u32 imx8mq_soc_revision_from_atf(void) { return 0; }; 52 #endif 53 54 static u32 __init imx8mq_soc_revision(void) 55 { 56 struct device_node *np; 57 void __iomem *ocotp_base; 58 u32 magic; 59 u32 rev; 60 struct clk *clk; 61 62 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp"); 63 if (!np) 64 return 0; 65 66 ocotp_base = of_iomap(np, 0); 67 WARN_ON(!ocotp_base); 68 clk = of_clk_get_by_name(np, NULL); 69 if (IS_ERR(clk)) { 70 WARN_ON(IS_ERR(clk)); 71 return 0; 72 } 73 74 clk_prepare_enable(clk); 75 76 /* 77 * SOC revision on older imx8mq is not available in fuses so query 78 * the value from ATF instead. 79 */ 80 rev = imx8mq_soc_revision_from_atf(); 81 if (!rev) { 82 magic = readl_relaxed(ocotp_base + IMX8MQ_SW_INFO_B1); 83 if (magic == IMX8MQ_SW_MAGIC_B1) 84 rev = REV_B1; 85 } 86 87 soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH); 88 soc_uid <<= 32; 89 soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW); 90 91 clk_disable_unprepare(clk); 92 clk_put(clk); 93 iounmap(ocotp_base); 94 of_node_put(np); 95 96 return rev; 97 } 98 99 static void __init imx8mm_soc_uid(void) 100 { 101 void __iomem *ocotp_base; 102 struct device_node *np; 103 u32 offset = of_machine_is_compatible("fsl,imx8mp") ? 104 IMX8MP_OCOTP_UID_OFFSET : 0; 105 106 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-ocotp"); 107 if (!np) 108 return; 109 110 ocotp_base = of_iomap(np, 0); 111 WARN_ON(!ocotp_base); 112 113 soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH + offset); 114 soc_uid <<= 32; 115 soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW + offset); 116 117 iounmap(ocotp_base); 118 of_node_put(np); 119 } 120 121 static u32 __init imx8mm_soc_revision(void) 122 { 123 struct device_node *np; 124 void __iomem *anatop_base; 125 u32 rev; 126 127 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); 128 if (!np) 129 return 0; 130 131 anatop_base = of_iomap(np, 0); 132 WARN_ON(!anatop_base); 133 134 rev = readl_relaxed(anatop_base + ANADIG_DIGPROG_IMX8MM); 135 136 iounmap(anatop_base); 137 of_node_put(np); 138 139 imx8mm_soc_uid(); 140 141 return rev; 142 } 143 144 static const struct imx8_soc_data imx8mq_soc_data = { 145 .name = "i.MX8MQ", 146 .soc_revision = imx8mq_soc_revision, 147 }; 148 149 static const struct imx8_soc_data imx8mm_soc_data = { 150 .name = "i.MX8MM", 151 .soc_revision = imx8mm_soc_revision, 152 }; 153 154 static const struct imx8_soc_data imx8mn_soc_data = { 155 .name = "i.MX8MN", 156 .soc_revision = imx8mm_soc_revision, 157 }; 158 159 static const struct imx8_soc_data imx8mp_soc_data = { 160 .name = "i.MX8MP", 161 .soc_revision = imx8mm_soc_revision, 162 }; 163 164 static __maybe_unused const struct of_device_id imx8_soc_match[] = { 165 { .compatible = "fsl,imx8mq", .data = &imx8mq_soc_data, }, 166 { .compatible = "fsl,imx8mm", .data = &imx8mm_soc_data, }, 167 { .compatible = "fsl,imx8mn", .data = &imx8mn_soc_data, }, 168 { .compatible = "fsl,imx8mp", .data = &imx8mp_soc_data, }, 169 { } 170 }; 171 172 #define imx8_revision(soc_rev) \ 173 soc_rev ? \ 174 kasprintf(GFP_KERNEL, "%d.%d", (soc_rev >> 4) & 0xf, soc_rev & 0xf) : \ 175 "unknown" 176 177 static int __init imx8_soc_init(void) 178 { 179 struct soc_device_attribute *soc_dev_attr; 180 struct soc_device *soc_dev; 181 const struct of_device_id *id; 182 u32 soc_rev = 0; 183 const struct imx8_soc_data *data; 184 int ret; 185 186 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 187 if (!soc_dev_attr) 188 return -ENOMEM; 189 190 soc_dev_attr->family = "Freescale i.MX"; 191 192 ret = of_property_read_string(of_root, "model", &soc_dev_attr->machine); 193 if (ret) 194 goto free_soc; 195 196 id = of_match_node(imx8_soc_match, of_root); 197 if (!id) { 198 ret = -ENODEV; 199 goto free_soc; 200 } 201 202 data = id->data; 203 if (data) { 204 soc_dev_attr->soc_id = data->name; 205 if (data->soc_revision) 206 soc_rev = data->soc_revision(); 207 } 208 209 soc_dev_attr->revision = imx8_revision(soc_rev); 210 if (!soc_dev_attr->revision) { 211 ret = -ENOMEM; 212 goto free_soc; 213 } 214 215 soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid); 216 if (!soc_dev_attr->serial_number) { 217 ret = -ENOMEM; 218 goto free_rev; 219 } 220 221 soc_dev = soc_device_register(soc_dev_attr); 222 if (IS_ERR(soc_dev)) { 223 ret = PTR_ERR(soc_dev); 224 goto free_serial_number; 225 } 226 227 pr_info("SoC: %s revision %s\n", soc_dev_attr->soc_id, 228 soc_dev_attr->revision); 229 230 if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT)) 231 platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0); 232 233 return 0; 234 235 free_serial_number: 236 kfree(soc_dev_attr->serial_number); 237 free_rev: 238 if (strcmp(soc_dev_attr->revision, "unknown")) 239 kfree(soc_dev_attr->revision); 240 free_soc: 241 kfree(soc_dev_attr); 242 return ret; 243 } 244 device_initcall(imx8_soc_init); 245