1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2019 NXP. 4 */ 5 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/of_address.h> 9 #include <linux/slab.h> 10 #include <linux/sys_soc.h> 11 #include <linux/platform_device.h> 12 #include <linux/arm-smccc.h> 13 #include <linux/of.h> 14 15 #define REV_B1 0x21 16 17 #define IMX8MQ_SW_INFO_B1 0x40 18 #define IMX8MQ_SW_MAGIC_B1 0xff0055aa 19 20 #define IMX_SIP_GET_SOC_INFO 0xc2000006 21 22 #define OCOTP_UID_LOW 0x410 23 #define OCOTP_UID_HIGH 0x420 24 25 /* Same as ANADIG_DIGPROG_IMX7D */ 26 #define ANADIG_DIGPROG_IMX8MM 0x800 27 28 struct imx8_soc_data { 29 char *name; 30 u32 (*soc_revision)(void); 31 }; 32 33 static u64 soc_uid; 34 35 #ifdef CONFIG_HAVE_ARM_SMCCC 36 static u32 imx8mq_soc_revision_from_atf(void) 37 { 38 struct arm_smccc_res res; 39 40 arm_smccc_smc(IMX_SIP_GET_SOC_INFO, 0, 0, 0, 0, 0, 0, 0, &res); 41 42 if (res.a0 == SMCCC_RET_NOT_SUPPORTED) 43 return 0; 44 else 45 return res.a0 & 0xff; 46 } 47 #else 48 static inline u32 imx8mq_soc_revision_from_atf(void) { return 0; }; 49 #endif 50 51 static u32 __init imx8mq_soc_revision(void) 52 { 53 struct device_node *np; 54 void __iomem *ocotp_base; 55 u32 magic; 56 u32 rev = 0; 57 58 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp"); 59 if (!np) 60 goto out; 61 62 ocotp_base = of_iomap(np, 0); 63 WARN_ON(!ocotp_base); 64 65 /* 66 * SOC revision on older imx8mq is not available in fuses so query 67 * the value from ATF instead. 68 */ 69 rev = imx8mq_soc_revision_from_atf(); 70 if (!rev) { 71 magic = readl_relaxed(ocotp_base + IMX8MQ_SW_INFO_B1); 72 if (magic == IMX8MQ_SW_MAGIC_B1) 73 rev = REV_B1; 74 } 75 76 soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH); 77 soc_uid <<= 32; 78 soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW); 79 80 iounmap(ocotp_base); 81 82 out: 83 of_node_put(np); 84 return rev; 85 } 86 87 static void __init imx8mm_soc_uid(void) 88 { 89 void __iomem *ocotp_base; 90 struct device_node *np; 91 92 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-ocotp"); 93 if (!np) 94 return; 95 96 ocotp_base = of_iomap(np, 0); 97 WARN_ON(!ocotp_base); 98 99 soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH); 100 soc_uid <<= 32; 101 soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW); 102 103 iounmap(ocotp_base); 104 of_node_put(np); 105 } 106 107 static u32 __init imx8mm_soc_revision(void) 108 { 109 struct device_node *np; 110 void __iomem *anatop_base; 111 u32 rev; 112 113 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); 114 if (!np) 115 return 0; 116 117 anatop_base = of_iomap(np, 0); 118 WARN_ON(!anatop_base); 119 120 rev = readl_relaxed(anatop_base + ANADIG_DIGPROG_IMX8MM); 121 122 iounmap(anatop_base); 123 of_node_put(np); 124 125 imx8mm_soc_uid(); 126 127 return rev; 128 } 129 130 static const struct imx8_soc_data imx8mq_soc_data = { 131 .name = "i.MX8MQ", 132 .soc_revision = imx8mq_soc_revision, 133 }; 134 135 static const struct imx8_soc_data imx8mm_soc_data = { 136 .name = "i.MX8MM", 137 .soc_revision = imx8mm_soc_revision, 138 }; 139 140 static const struct imx8_soc_data imx8mn_soc_data = { 141 .name = "i.MX8MN", 142 .soc_revision = imx8mm_soc_revision, 143 }; 144 145 static const struct imx8_soc_data imx8mp_soc_data = { 146 .name = "i.MX8MP", 147 .soc_revision = imx8mm_soc_revision, 148 }; 149 150 static const struct of_device_id imx8_soc_match[] = { 151 { .compatible = "fsl,imx8mq", .data = &imx8mq_soc_data, }, 152 { .compatible = "fsl,imx8mm", .data = &imx8mm_soc_data, }, 153 { .compatible = "fsl,imx8mn", .data = &imx8mn_soc_data, }, 154 { .compatible = "fsl,imx8mp", .data = &imx8mp_soc_data, }, 155 { } 156 }; 157 158 #define imx8_revision(soc_rev) \ 159 soc_rev ? \ 160 kasprintf(GFP_KERNEL, "%d.%d", (soc_rev >> 4) & 0xf, soc_rev & 0xf) : \ 161 "unknown" 162 163 static int __init imx8_soc_init(void) 164 { 165 struct soc_device_attribute *soc_dev_attr; 166 struct soc_device *soc_dev; 167 const struct of_device_id *id; 168 u32 soc_rev = 0; 169 const struct imx8_soc_data *data; 170 int ret; 171 172 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 173 if (!soc_dev_attr) 174 return -ENOMEM; 175 176 soc_dev_attr->family = "Freescale i.MX"; 177 178 ret = of_property_read_string(of_root, "model", &soc_dev_attr->machine); 179 if (ret) 180 goto free_soc; 181 182 id = of_match_node(imx8_soc_match, of_root); 183 if (!id) { 184 ret = -ENODEV; 185 goto free_soc; 186 } 187 188 data = id->data; 189 if (data) { 190 soc_dev_attr->soc_id = data->name; 191 if (data->soc_revision) 192 soc_rev = data->soc_revision(); 193 } 194 195 soc_dev_attr->revision = imx8_revision(soc_rev); 196 if (!soc_dev_attr->revision) { 197 ret = -ENOMEM; 198 goto free_soc; 199 } 200 201 soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid); 202 if (!soc_dev_attr->serial_number) { 203 ret = -ENOMEM; 204 goto free_rev; 205 } 206 207 soc_dev = soc_device_register(soc_dev_attr); 208 if (IS_ERR(soc_dev)) { 209 ret = PTR_ERR(soc_dev); 210 goto free_serial_number; 211 } 212 213 pr_info("SoC: %s revision %s\n", soc_dev_attr->soc_id, 214 soc_dev_attr->revision); 215 216 if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT)) 217 platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0); 218 219 return 0; 220 221 free_serial_number: 222 kfree(soc_dev_attr->serial_number); 223 free_rev: 224 if (strcmp(soc_dev_attr->revision, "unknown")) 225 kfree(soc_dev_attr->revision); 226 free_soc: 227 kfree(soc_dev_attr); 228 return ret; 229 } 230 device_initcall(imx8_soc_init); 231