1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. 4 * 5 * Authors: Shlomi Gridish <gridish@freescale.com> 6 * Li Yang <leoli@freescale.com> 7 * 8 * Description: 9 * QE UCC Slow API Set - UCC Slow specific routines implementations. 10 */ 11 #include <linux/kernel.h> 12 #include <linux/errno.h> 13 #include <linux/slab.h> 14 #include <linux/stddef.h> 15 #include <linux/interrupt.h> 16 #include <linux/err.h> 17 #include <linux/export.h> 18 19 #include <asm/io.h> 20 #include <soc/fsl/qe/immap_qe.h> 21 #include <soc/fsl/qe/qe.h> 22 23 #include <soc/fsl/qe/ucc.h> 24 #include <soc/fsl/qe/ucc_slow.h> 25 26 u32 ucc_slow_get_qe_cr_subblock(int uccs_num) 27 { 28 switch (uccs_num) { 29 case 0: return QE_CR_SUBBLOCK_UCCSLOW1; 30 case 1: return QE_CR_SUBBLOCK_UCCSLOW2; 31 case 2: return QE_CR_SUBBLOCK_UCCSLOW3; 32 case 3: return QE_CR_SUBBLOCK_UCCSLOW4; 33 case 4: return QE_CR_SUBBLOCK_UCCSLOW5; 34 case 5: return QE_CR_SUBBLOCK_UCCSLOW6; 35 case 6: return QE_CR_SUBBLOCK_UCCSLOW7; 36 case 7: return QE_CR_SUBBLOCK_UCCSLOW8; 37 default: return QE_CR_SUBBLOCK_INVALID; 38 } 39 } 40 EXPORT_SYMBOL(ucc_slow_get_qe_cr_subblock); 41 42 void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs) 43 { 44 struct ucc_slow_info *us_info = uccs->us_info; 45 u32 id; 46 47 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); 48 qe_issue_cmd(QE_GRACEFUL_STOP_TX, id, 49 QE_CR_PROTOCOL_UNSPECIFIED, 0); 50 } 51 EXPORT_SYMBOL(ucc_slow_graceful_stop_tx); 52 53 void ucc_slow_stop_tx(struct ucc_slow_private * uccs) 54 { 55 struct ucc_slow_info *us_info = uccs->us_info; 56 u32 id; 57 58 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); 59 qe_issue_cmd(QE_STOP_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0); 60 } 61 EXPORT_SYMBOL(ucc_slow_stop_tx); 62 63 void ucc_slow_restart_tx(struct ucc_slow_private * uccs) 64 { 65 struct ucc_slow_info *us_info = uccs->us_info; 66 u32 id; 67 68 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); 69 qe_issue_cmd(QE_RESTART_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0); 70 } 71 EXPORT_SYMBOL(ucc_slow_restart_tx); 72 73 void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode) 74 { 75 struct ucc_slow *us_regs; 76 u32 gumr_l; 77 78 us_regs = uccs->us_regs; 79 80 /* Enable reception and/or transmission on this UCC. */ 81 gumr_l = qe_ioread32be(&us_regs->gumr_l); 82 if (mode & COMM_DIR_TX) { 83 gumr_l |= UCC_SLOW_GUMR_L_ENT; 84 uccs->enabled_tx = 1; 85 } 86 if (mode & COMM_DIR_RX) { 87 gumr_l |= UCC_SLOW_GUMR_L_ENR; 88 uccs->enabled_rx = 1; 89 } 90 qe_iowrite32be(gumr_l, &us_regs->gumr_l); 91 } 92 EXPORT_SYMBOL(ucc_slow_enable); 93 94 void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode) 95 { 96 struct ucc_slow *us_regs; 97 u32 gumr_l; 98 99 us_regs = uccs->us_regs; 100 101 /* Disable reception and/or transmission on this UCC. */ 102 gumr_l = qe_ioread32be(&us_regs->gumr_l); 103 if (mode & COMM_DIR_TX) { 104 gumr_l &= ~UCC_SLOW_GUMR_L_ENT; 105 uccs->enabled_tx = 0; 106 } 107 if (mode & COMM_DIR_RX) { 108 gumr_l &= ~UCC_SLOW_GUMR_L_ENR; 109 uccs->enabled_rx = 0; 110 } 111 qe_iowrite32be(gumr_l, &us_regs->gumr_l); 112 } 113 EXPORT_SYMBOL(ucc_slow_disable); 114 115 /* Initialize the UCC for Slow operations 116 * 117 * The caller should initialize the following us_info 118 */ 119 int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret) 120 { 121 struct ucc_slow_private *uccs; 122 u32 i; 123 struct ucc_slow __iomem *us_regs; 124 u32 gumr; 125 struct qe_bd *bd; 126 u32 id; 127 u32 command; 128 int ret = 0; 129 130 if (!us_info) 131 return -EINVAL; 132 133 /* check if the UCC port number is in range. */ 134 if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) { 135 printk(KERN_ERR "%s: illegal UCC number\n", __func__); 136 return -EINVAL; 137 } 138 139 /* 140 * Set mrblr 141 * Check that 'max_rx_buf_length' is properly aligned (4), unless 142 * rfw is 1, meaning that QE accepts one byte at a time, unlike normal 143 * case when QE accepts 32 bits at a time. 144 */ 145 if ((!us_info->rfw) && 146 (us_info->max_rx_buf_length & (UCC_SLOW_MRBLR_ALIGNMENT - 1))) { 147 printk(KERN_ERR "max_rx_buf_length not aligned.\n"); 148 return -EINVAL; 149 } 150 151 uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL); 152 if (!uccs) { 153 printk(KERN_ERR "%s: Cannot allocate private data\n", 154 __func__); 155 return -ENOMEM; 156 } 157 uccs->rx_base_offset = -1; 158 uccs->tx_base_offset = -1; 159 uccs->us_pram_offset = -1; 160 161 /* Fill slow UCC structure */ 162 uccs->us_info = us_info; 163 /* Set the PHY base address */ 164 uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow)); 165 if (uccs->us_regs == NULL) { 166 printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__); 167 kfree(uccs); 168 return -ENOMEM; 169 } 170 171 uccs->saved_uccm = 0; 172 uccs->p_rx_frame = 0; 173 us_regs = uccs->us_regs; 174 uccs->p_ucce = (u16 *) & (us_regs->ucce); 175 uccs->p_uccm = (u16 *) & (us_regs->uccm); 176 #ifdef STATISTICS 177 uccs->rx_frames = 0; 178 uccs->tx_frames = 0; 179 uccs->rx_discarded = 0; 180 #endif /* STATISTICS */ 181 182 /* Get PRAM base */ 183 uccs->us_pram_offset = 184 qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM); 185 if (uccs->us_pram_offset < 0) { 186 printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __func__); 187 ucc_slow_free(uccs); 188 return -ENOMEM; 189 } 190 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); 191 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, us_info->protocol, 192 uccs->us_pram_offset); 193 194 uccs->us_pram = qe_muram_addr(uccs->us_pram_offset); 195 196 /* Set UCC to slow type */ 197 ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW); 198 if (ret) { 199 printk(KERN_ERR "%s: cannot set UCC type", __func__); 200 ucc_slow_free(uccs); 201 return ret; 202 } 203 204 qe_iowrite16be(us_info->max_rx_buf_length, &uccs->us_pram->mrblr); 205 206 INIT_LIST_HEAD(&uccs->confQ); 207 208 /* Allocate BDs. */ 209 uccs->rx_base_offset = 210 qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd), 211 QE_ALIGNMENT_OF_BD); 212 if (uccs->rx_base_offset < 0) { 213 printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __func__, 214 us_info->rx_bd_ring_len); 215 ucc_slow_free(uccs); 216 return -ENOMEM; 217 } 218 219 uccs->tx_base_offset = 220 qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd), 221 QE_ALIGNMENT_OF_BD); 222 if (uccs->tx_base_offset < 0) { 223 printk(KERN_ERR "%s: cannot allocate TX BDs", __func__); 224 ucc_slow_free(uccs); 225 return -ENOMEM; 226 } 227 228 /* Init Tx bds */ 229 bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset); 230 for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) { 231 /* clear bd buffer */ 232 qe_iowrite32be(0, &bd->buf); 233 /* set bd status and length */ 234 qe_iowrite32be(0, (u32 *)bd); 235 bd++; 236 } 237 /* for last BD set Wrap bit */ 238 qe_iowrite32be(0, &bd->buf); 239 qe_iowrite32be(cpu_to_be32(T_W), (u32 *)bd); 240 241 /* Init Rx bds */ 242 bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset); 243 for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) { 244 /* set bd status and length */ 245 qe_iowrite32be(0, (u32 *)bd); 246 /* clear bd buffer */ 247 qe_iowrite32be(0, &bd->buf); 248 bd++; 249 } 250 /* for last BD set Wrap bit */ 251 qe_iowrite32be(cpu_to_be32(R_W), (u32 *)bd); 252 qe_iowrite32be(0, &bd->buf); 253 254 /* Set GUMR (For more details see the hardware spec.). */ 255 /* gumr_h */ 256 gumr = us_info->tcrc; 257 if (us_info->cdp) 258 gumr |= UCC_SLOW_GUMR_H_CDP; 259 if (us_info->ctsp) 260 gumr |= UCC_SLOW_GUMR_H_CTSP; 261 if (us_info->cds) 262 gumr |= UCC_SLOW_GUMR_H_CDS; 263 if (us_info->ctss) 264 gumr |= UCC_SLOW_GUMR_H_CTSS; 265 if (us_info->tfl) 266 gumr |= UCC_SLOW_GUMR_H_TFL; 267 if (us_info->rfw) 268 gumr |= UCC_SLOW_GUMR_H_RFW; 269 if (us_info->txsy) 270 gumr |= UCC_SLOW_GUMR_H_TXSY; 271 if (us_info->rtsm) 272 gumr |= UCC_SLOW_GUMR_H_RTSM; 273 qe_iowrite32be(gumr, &us_regs->gumr_h); 274 275 /* gumr_l */ 276 gumr = us_info->tdcr | us_info->rdcr | us_info->tenc | us_info->renc | 277 us_info->diag | us_info->mode; 278 if (us_info->tci) 279 gumr |= UCC_SLOW_GUMR_L_TCI; 280 if (us_info->rinv) 281 gumr |= UCC_SLOW_GUMR_L_RINV; 282 if (us_info->tinv) 283 gumr |= UCC_SLOW_GUMR_L_TINV; 284 if (us_info->tend) 285 gumr |= UCC_SLOW_GUMR_L_TEND; 286 qe_iowrite32be(gumr, &us_regs->gumr_l); 287 288 /* Function code registers */ 289 290 /* if the data is in cachable memory, the 'global' */ 291 /* in the function code should be set. */ 292 uccs->us_pram->tbmr = UCC_BMR_BO_BE; 293 uccs->us_pram->rbmr = UCC_BMR_BO_BE; 294 295 /* rbase, tbase are offsets from MURAM base */ 296 qe_iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase); 297 qe_iowrite16be(uccs->tx_base_offset, &uccs->us_pram->tbase); 298 299 /* Mux clocking */ 300 /* Grant Support */ 301 ucc_set_qe_mux_grant(us_info->ucc_num, us_info->grant_support); 302 /* Breakpoint Support */ 303 ucc_set_qe_mux_bkpt(us_info->ucc_num, us_info->brkpt_support); 304 /* Set Tsa or NMSI mode. */ 305 ucc_set_qe_mux_tsa(us_info->ucc_num, us_info->tsa); 306 /* If NMSI (not Tsa), set Tx and Rx clock. */ 307 if (!us_info->tsa) { 308 /* Rx clock routing */ 309 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock, 310 COMM_DIR_RX)) { 311 printk(KERN_ERR "%s: illegal value for RX clock\n", 312 __func__); 313 ucc_slow_free(uccs); 314 return -EINVAL; 315 } 316 /* Tx clock routing */ 317 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock, 318 COMM_DIR_TX)) { 319 printk(KERN_ERR "%s: illegal value for TX clock\n", 320 __func__); 321 ucc_slow_free(uccs); 322 return -EINVAL; 323 } 324 } 325 326 /* Set interrupt mask register at UCC level. */ 327 qe_iowrite16be(us_info->uccm_mask, &us_regs->uccm); 328 329 /* First, clear anything pending at UCC level, 330 * otherwise, old garbage may come through 331 * as soon as the dam is opened. */ 332 333 /* Writing '1' clears */ 334 qe_iowrite16be(0xffff, &us_regs->ucce); 335 336 /* Issue QE Init command */ 337 if (us_info->init_tx && us_info->init_rx) 338 command = QE_INIT_TX_RX; 339 else if (us_info->init_tx) 340 command = QE_INIT_TX; 341 else 342 command = QE_INIT_RX; /* We know at least one is TRUE */ 343 344 qe_issue_cmd(command, id, us_info->protocol, 0); 345 346 *uccs_ret = uccs; 347 return 0; 348 } 349 EXPORT_SYMBOL(ucc_slow_init); 350 351 void ucc_slow_free(struct ucc_slow_private * uccs) 352 { 353 if (!uccs) 354 return; 355 356 qe_muram_free(uccs->rx_base_offset); 357 qe_muram_free(uccs->tx_base_offset); 358 qe_muram_free(uccs->us_pram_offset); 359 360 if (uccs->us_regs) 361 iounmap(uccs->us_regs); 362 363 kfree(uccs); 364 } 365 EXPORT_SYMBOL(ucc_slow_free); 366 367