1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * arch/powerpc/sysdev/qe_lib/qe_io.c 4 * 5 * QE Parallel I/O ports configuration routines 6 * 7 * Copyright 2006 Freescale Semiconductor, Inc. All rights reserved. 8 * 9 * Author: Li Yang <LeoLi@freescale.com> 10 * Based on code from Shlomi Gridish <gridish@freescale.com> 11 */ 12 13 #include <linux/stddef.h> 14 #include <linux/kernel.h> 15 #include <linux/errno.h> 16 #include <linux/module.h> 17 #include <linux/ioport.h> 18 19 #include <asm/io.h> 20 #include <soc/fsl/qe/qe.h> 21 #include <asm/prom.h> 22 #include <sysdev/fsl_soc.h> 23 24 #undef DEBUG 25 26 static struct qe_pio_regs __iomem *par_io; 27 static int num_par_io_ports = 0; 28 29 int par_io_init(struct device_node *np) 30 { 31 struct resource res; 32 int ret; 33 const u32 *num_ports; 34 35 /* Map Parallel I/O ports registers */ 36 ret = of_address_to_resource(np, 0, &res); 37 if (ret) 38 return ret; 39 par_io = ioremap(res.start, resource_size(&res)); 40 41 num_ports = of_get_property(np, "num-ports", NULL); 42 if (num_ports) 43 num_par_io_ports = *num_ports; 44 45 return 0; 46 } 47 48 void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir, 49 int open_drain, int assignment, int has_irq) 50 { 51 u32 pin_mask1bit; 52 u32 pin_mask2bits; 53 u32 new_mask2bits; 54 u32 tmp_val; 55 56 /* calculate pin location for single and 2 bits information */ 57 pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1))); 58 59 /* Set open drain, if required */ 60 tmp_val = in_be32(&par_io->cpodr); 61 if (open_drain) 62 out_be32(&par_io->cpodr, pin_mask1bit | tmp_val); 63 else 64 out_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val); 65 66 /* define direction */ 67 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? 68 in_be32(&par_io->cpdir2) : 69 in_be32(&par_io->cpdir1); 70 71 /* get all bits mask for 2 bit per port */ 72 pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS - 73 (pin % (QE_PIO_PINS / 2) + 1) * 2)); 74 75 /* Get the final mask we need for the right definition */ 76 new_mask2bits = (u32) (dir << (QE_PIO_PINS - 77 (pin % (QE_PIO_PINS / 2) + 1) * 2)); 78 79 /* clear and set 2 bits mask */ 80 if (pin > (QE_PIO_PINS / 2) - 1) { 81 out_be32(&par_io->cpdir2, 82 ~pin_mask2bits & tmp_val); 83 tmp_val &= ~pin_mask2bits; 84 out_be32(&par_io->cpdir2, new_mask2bits | tmp_val); 85 } else { 86 out_be32(&par_io->cpdir1, 87 ~pin_mask2bits & tmp_val); 88 tmp_val &= ~pin_mask2bits; 89 out_be32(&par_io->cpdir1, new_mask2bits | tmp_val); 90 } 91 /* define pin assignment */ 92 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? 93 in_be32(&par_io->cppar2) : 94 in_be32(&par_io->cppar1); 95 96 new_mask2bits = (u32) (assignment << (QE_PIO_PINS - 97 (pin % (QE_PIO_PINS / 2) + 1) * 2)); 98 /* clear and set 2 bits mask */ 99 if (pin > (QE_PIO_PINS / 2) - 1) { 100 out_be32(&par_io->cppar2, 101 ~pin_mask2bits & tmp_val); 102 tmp_val &= ~pin_mask2bits; 103 out_be32(&par_io->cppar2, new_mask2bits | tmp_val); 104 } else { 105 out_be32(&par_io->cppar1, 106 ~pin_mask2bits & tmp_val); 107 tmp_val &= ~pin_mask2bits; 108 out_be32(&par_io->cppar1, new_mask2bits | tmp_val); 109 } 110 } 111 EXPORT_SYMBOL(__par_io_config_pin); 112 113 int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, 114 int assignment, int has_irq) 115 { 116 if (!par_io || port >= num_par_io_ports) 117 return -EINVAL; 118 119 __par_io_config_pin(&par_io[port], pin, dir, open_drain, assignment, 120 has_irq); 121 return 0; 122 } 123 EXPORT_SYMBOL(par_io_config_pin); 124 125 int par_io_data_set(u8 port, u8 pin, u8 val) 126 { 127 u32 pin_mask, tmp_val; 128 129 if (port >= num_par_io_ports) 130 return -EINVAL; 131 if (pin >= QE_PIO_PINS) 132 return -EINVAL; 133 /* calculate pin location */ 134 pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin)); 135 136 tmp_val = in_be32(&par_io[port].cpdata); 137 138 if (val == 0) /* clear */ 139 out_be32(&par_io[port].cpdata, ~pin_mask & tmp_val); 140 else /* set */ 141 out_be32(&par_io[port].cpdata, pin_mask | tmp_val); 142 143 return 0; 144 } 145 EXPORT_SYMBOL(par_io_data_set); 146 147 int par_io_of_config(struct device_node *np) 148 { 149 struct device_node *pio; 150 const phandle *ph; 151 int pio_map_len; 152 const unsigned int *pio_map; 153 154 if (par_io == NULL) { 155 printk(KERN_ERR "par_io not initialized\n"); 156 return -1; 157 } 158 159 ph = of_get_property(np, "pio-handle", NULL); 160 if (ph == NULL) { 161 printk(KERN_ERR "pio-handle not available\n"); 162 return -1; 163 } 164 165 pio = of_find_node_by_phandle(*ph); 166 167 pio_map = of_get_property(pio, "pio-map", &pio_map_len); 168 if (pio_map == NULL) { 169 printk(KERN_ERR "pio-map is not set!\n"); 170 return -1; 171 } 172 pio_map_len /= sizeof(unsigned int); 173 if ((pio_map_len % 6) != 0) { 174 printk(KERN_ERR "pio-map format wrong!\n"); 175 return -1; 176 } 177 178 while (pio_map_len > 0) { 179 par_io_config_pin((u8) pio_map[0], (u8) pio_map[1], 180 (int) pio_map[2], (int) pio_map[3], 181 (int) pio_map[4], (int) pio_map[5]); 182 pio_map += 6; 183 pio_map_len -= 6; 184 } 185 of_node_put(pio); 186 return 0; 187 } 188 EXPORT_SYMBOL(par_io_of_config); 189