1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * arch/powerpc/sysdev/qe_lib/qe_io.c 4 * 5 * QE Parallel I/O ports configuration routines 6 * 7 * Copyright 2006 Freescale Semiconductor, Inc. All rights reserved. 8 * 9 * Author: Li Yang <LeoLi@freescale.com> 10 * Based on code from Shlomi Gridish <gridish@freescale.com> 11 */ 12 13 #include <linux/stddef.h> 14 #include <linux/kernel.h> 15 #include <linux/errno.h> 16 #include <linux/module.h> 17 #include <linux/ioport.h> 18 19 #include <asm/io.h> 20 #include <soc/fsl/qe/qe.h> 21 22 #undef DEBUG 23 24 static struct qe_pio_regs __iomem *par_io; 25 static int num_par_io_ports = 0; 26 27 int par_io_init(struct device_node *np) 28 { 29 struct resource res; 30 int ret; 31 const u32 *num_ports; 32 33 /* Map Parallel I/O ports registers */ 34 ret = of_address_to_resource(np, 0, &res); 35 if (ret) 36 return ret; 37 par_io = ioremap(res.start, resource_size(&res)); 38 39 num_ports = of_get_property(np, "num-ports", NULL); 40 if (num_ports) 41 num_par_io_ports = *num_ports; 42 43 return 0; 44 } 45 46 void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir, 47 int open_drain, int assignment, int has_irq) 48 { 49 u32 pin_mask1bit; 50 u32 pin_mask2bits; 51 u32 new_mask2bits; 52 u32 tmp_val; 53 54 /* calculate pin location for single and 2 bits information */ 55 pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1))); 56 57 /* Set open drain, if required */ 58 tmp_val = qe_ioread32be(&par_io->cpodr); 59 if (open_drain) 60 qe_iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr); 61 else 62 qe_iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr); 63 64 /* define direction */ 65 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? 66 qe_ioread32be(&par_io->cpdir2) : 67 qe_ioread32be(&par_io->cpdir1); 68 69 /* get all bits mask for 2 bit per port */ 70 pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS - 71 (pin % (QE_PIO_PINS / 2) + 1) * 2)); 72 73 /* Get the final mask we need for the right definition */ 74 new_mask2bits = (u32) (dir << (QE_PIO_PINS - 75 (pin % (QE_PIO_PINS / 2) + 1) * 2)); 76 77 /* clear and set 2 bits mask */ 78 if (pin > (QE_PIO_PINS / 2) - 1) { 79 qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2); 80 tmp_val &= ~pin_mask2bits; 81 qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2); 82 } else { 83 qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1); 84 tmp_val &= ~pin_mask2bits; 85 qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1); 86 } 87 /* define pin assignment */ 88 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? 89 qe_ioread32be(&par_io->cppar2) : 90 qe_ioread32be(&par_io->cppar1); 91 92 new_mask2bits = (u32) (assignment << (QE_PIO_PINS - 93 (pin % (QE_PIO_PINS / 2) + 1) * 2)); 94 /* clear and set 2 bits mask */ 95 if (pin > (QE_PIO_PINS / 2) - 1) { 96 qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2); 97 tmp_val &= ~pin_mask2bits; 98 qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cppar2); 99 } else { 100 qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1); 101 tmp_val &= ~pin_mask2bits; 102 qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cppar1); 103 } 104 } 105 EXPORT_SYMBOL(__par_io_config_pin); 106 107 int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, 108 int assignment, int has_irq) 109 { 110 if (!par_io || port >= num_par_io_ports) 111 return -EINVAL; 112 113 __par_io_config_pin(&par_io[port], pin, dir, open_drain, assignment, 114 has_irq); 115 return 0; 116 } 117 EXPORT_SYMBOL(par_io_config_pin); 118 119 int par_io_data_set(u8 port, u8 pin, u8 val) 120 { 121 u32 pin_mask, tmp_val; 122 123 if (port >= num_par_io_ports) 124 return -EINVAL; 125 if (pin >= QE_PIO_PINS) 126 return -EINVAL; 127 /* calculate pin location */ 128 pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin)); 129 130 tmp_val = qe_ioread32be(&par_io[port].cpdata); 131 132 if (val == 0) /* clear */ 133 qe_iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata); 134 else /* set */ 135 qe_iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata); 136 137 return 0; 138 } 139 EXPORT_SYMBOL(par_io_data_set); 140 141 int par_io_of_config(struct device_node *np) 142 { 143 struct device_node *pio; 144 const phandle *ph; 145 int pio_map_len; 146 const unsigned int *pio_map; 147 148 if (par_io == NULL) { 149 printk(KERN_ERR "par_io not initialized\n"); 150 return -1; 151 } 152 153 ph = of_get_property(np, "pio-handle", NULL); 154 if (ph == NULL) { 155 printk(KERN_ERR "pio-handle not available\n"); 156 return -1; 157 } 158 159 pio = of_find_node_by_phandle(*ph); 160 161 pio_map = of_get_property(pio, "pio-map", &pio_map_len); 162 if (pio_map == NULL) { 163 printk(KERN_ERR "pio-map is not set!\n"); 164 return -1; 165 } 166 pio_map_len /= sizeof(unsigned int); 167 if ((pio_map_len % 6) != 0) { 168 printk(KERN_ERR "pio-map format wrong!\n"); 169 return -1; 170 } 171 172 while (pio_map_len > 0) { 173 par_io_config_pin((u8) pio_map[0], (u8) pio_map[1], 174 (int) pio_map[2], (int) pio_map[3], 175 (int) pio_map[4], (int) pio_map[5]); 176 pio_map += 6; 177 pio_map_len -= 6; 178 } 179 of_node_put(pio); 180 return 0; 181 } 182 EXPORT_SYMBOL(par_io_of_config); 183