1 /* 2 * arch/powerpc/sysdev/qe_lib/qe_ic.c 3 * 4 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Li Yang <leoli@freescale.com> 7 * Based on code from Shlomi Gridish <gridish@freescale.com> 8 * 9 * QUICC ENGINE Interrupt Controller 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 */ 16 17 #include <linux/of_irq.h> 18 #include <linux/of_address.h> 19 #include <linux/kernel.h> 20 #include <linux/init.h> 21 #include <linux/errno.h> 22 #include <linux/reboot.h> 23 #include <linux/slab.h> 24 #include <linux/stddef.h> 25 #include <linux/sched.h> 26 #include <linux/signal.h> 27 #include <linux/device.h> 28 #include <linux/spinlock.h> 29 #include <asm/irq.h> 30 #include <asm/io.h> 31 #include <soc/fsl/qe/qe_ic.h> 32 33 #include "qe_ic.h" 34 35 static DEFINE_RAW_SPINLOCK(qe_ic_lock); 36 37 static struct qe_ic_info qe_ic_info[] = { 38 [1] = { 39 .mask = 0x00008000, 40 .mask_reg = QEIC_CIMR, 41 .pri_code = 0, 42 .pri_reg = QEIC_CIPWCC, 43 }, 44 [2] = { 45 .mask = 0x00004000, 46 .mask_reg = QEIC_CIMR, 47 .pri_code = 1, 48 .pri_reg = QEIC_CIPWCC, 49 }, 50 [3] = { 51 .mask = 0x00002000, 52 .mask_reg = QEIC_CIMR, 53 .pri_code = 2, 54 .pri_reg = QEIC_CIPWCC, 55 }, 56 [10] = { 57 .mask = 0x00000040, 58 .mask_reg = QEIC_CIMR, 59 .pri_code = 1, 60 .pri_reg = QEIC_CIPZCC, 61 }, 62 [11] = { 63 .mask = 0x00000020, 64 .mask_reg = QEIC_CIMR, 65 .pri_code = 2, 66 .pri_reg = QEIC_CIPZCC, 67 }, 68 [12] = { 69 .mask = 0x00000010, 70 .mask_reg = QEIC_CIMR, 71 .pri_code = 3, 72 .pri_reg = QEIC_CIPZCC, 73 }, 74 [13] = { 75 .mask = 0x00000008, 76 .mask_reg = QEIC_CIMR, 77 .pri_code = 4, 78 .pri_reg = QEIC_CIPZCC, 79 }, 80 [14] = { 81 .mask = 0x00000004, 82 .mask_reg = QEIC_CIMR, 83 .pri_code = 5, 84 .pri_reg = QEIC_CIPZCC, 85 }, 86 [15] = { 87 .mask = 0x00000002, 88 .mask_reg = QEIC_CIMR, 89 .pri_code = 6, 90 .pri_reg = QEIC_CIPZCC, 91 }, 92 [20] = { 93 .mask = 0x10000000, 94 .mask_reg = QEIC_CRIMR, 95 .pri_code = 3, 96 .pri_reg = QEIC_CIPRTA, 97 }, 98 [25] = { 99 .mask = 0x00800000, 100 .mask_reg = QEIC_CRIMR, 101 .pri_code = 0, 102 .pri_reg = QEIC_CIPRTB, 103 }, 104 [26] = { 105 .mask = 0x00400000, 106 .mask_reg = QEIC_CRIMR, 107 .pri_code = 1, 108 .pri_reg = QEIC_CIPRTB, 109 }, 110 [27] = { 111 .mask = 0x00200000, 112 .mask_reg = QEIC_CRIMR, 113 .pri_code = 2, 114 .pri_reg = QEIC_CIPRTB, 115 }, 116 [28] = { 117 .mask = 0x00100000, 118 .mask_reg = QEIC_CRIMR, 119 .pri_code = 3, 120 .pri_reg = QEIC_CIPRTB, 121 }, 122 [32] = { 123 .mask = 0x80000000, 124 .mask_reg = QEIC_CIMR, 125 .pri_code = 0, 126 .pri_reg = QEIC_CIPXCC, 127 }, 128 [33] = { 129 .mask = 0x40000000, 130 .mask_reg = QEIC_CIMR, 131 .pri_code = 1, 132 .pri_reg = QEIC_CIPXCC, 133 }, 134 [34] = { 135 .mask = 0x20000000, 136 .mask_reg = QEIC_CIMR, 137 .pri_code = 2, 138 .pri_reg = QEIC_CIPXCC, 139 }, 140 [35] = { 141 .mask = 0x10000000, 142 .mask_reg = QEIC_CIMR, 143 .pri_code = 3, 144 .pri_reg = QEIC_CIPXCC, 145 }, 146 [36] = { 147 .mask = 0x08000000, 148 .mask_reg = QEIC_CIMR, 149 .pri_code = 4, 150 .pri_reg = QEIC_CIPXCC, 151 }, 152 [40] = { 153 .mask = 0x00800000, 154 .mask_reg = QEIC_CIMR, 155 .pri_code = 0, 156 .pri_reg = QEIC_CIPYCC, 157 }, 158 [41] = { 159 .mask = 0x00400000, 160 .mask_reg = QEIC_CIMR, 161 .pri_code = 1, 162 .pri_reg = QEIC_CIPYCC, 163 }, 164 [42] = { 165 .mask = 0x00200000, 166 .mask_reg = QEIC_CIMR, 167 .pri_code = 2, 168 .pri_reg = QEIC_CIPYCC, 169 }, 170 [43] = { 171 .mask = 0x00100000, 172 .mask_reg = QEIC_CIMR, 173 .pri_code = 3, 174 .pri_reg = QEIC_CIPYCC, 175 }, 176 }; 177 178 static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg) 179 { 180 return in_be32(base + (reg >> 2)); 181 } 182 183 static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg, 184 u32 value) 185 { 186 out_be32(base + (reg >> 2), value); 187 } 188 189 static inline struct qe_ic *qe_ic_from_irq(unsigned int virq) 190 { 191 return irq_get_chip_data(virq); 192 } 193 194 static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d) 195 { 196 return irq_data_get_irq_chip_data(d); 197 } 198 199 static void qe_ic_unmask_irq(struct irq_data *d) 200 { 201 struct qe_ic *qe_ic = qe_ic_from_irq_data(d); 202 unsigned int src = irqd_to_hwirq(d); 203 unsigned long flags; 204 u32 temp; 205 206 raw_spin_lock_irqsave(&qe_ic_lock, flags); 207 208 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg); 209 qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg, 210 temp | qe_ic_info[src].mask); 211 212 raw_spin_unlock_irqrestore(&qe_ic_lock, flags); 213 } 214 215 static void qe_ic_mask_irq(struct irq_data *d) 216 { 217 struct qe_ic *qe_ic = qe_ic_from_irq_data(d); 218 unsigned int src = irqd_to_hwirq(d); 219 unsigned long flags; 220 u32 temp; 221 222 raw_spin_lock_irqsave(&qe_ic_lock, flags); 223 224 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg); 225 qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg, 226 temp & ~qe_ic_info[src].mask); 227 228 /* Flush the above write before enabling interrupts; otherwise, 229 * spurious interrupts will sometimes happen. To be 100% sure 230 * that the write has reached the device before interrupts are 231 * enabled, the mask register would have to be read back; however, 232 * this is not required for correctness, only to avoid wasting 233 * time on a large number of spurious interrupts. In testing, 234 * a sync reduced the observed spurious interrupts to zero. 235 */ 236 mb(); 237 238 raw_spin_unlock_irqrestore(&qe_ic_lock, flags); 239 } 240 241 static struct irq_chip qe_ic_irq_chip = { 242 .name = "QEIC", 243 .irq_unmask = qe_ic_unmask_irq, 244 .irq_mask = qe_ic_mask_irq, 245 .irq_mask_ack = qe_ic_mask_irq, 246 }; 247 248 static int qe_ic_host_match(struct irq_domain *h, struct device_node *node, 249 enum irq_domain_bus_token bus_token) 250 { 251 /* Exact match, unless qe_ic node is NULL */ 252 struct device_node *of_node = irq_domain_get_of_node(h); 253 return of_node == NULL || of_node == node; 254 } 255 256 static int qe_ic_host_map(struct irq_domain *h, unsigned int virq, 257 irq_hw_number_t hw) 258 { 259 struct qe_ic *qe_ic = h->host_data; 260 struct irq_chip *chip; 261 262 if (hw >= ARRAY_SIZE(qe_ic_info)) { 263 pr_err("%s: Invalid hw irq number for QEIC\n", __func__); 264 return -EINVAL; 265 } 266 267 if (qe_ic_info[hw].mask == 0) { 268 printk(KERN_ERR "Can't map reserved IRQ\n"); 269 return -EINVAL; 270 } 271 /* Default chip */ 272 chip = &qe_ic->hc_irq; 273 274 irq_set_chip_data(virq, qe_ic); 275 irq_set_status_flags(virq, IRQ_LEVEL); 276 277 irq_set_chip_and_handler(virq, chip, handle_level_irq); 278 279 return 0; 280 } 281 282 static const struct irq_domain_ops qe_ic_host_ops = { 283 .match = qe_ic_host_match, 284 .map = qe_ic_host_map, 285 .xlate = irq_domain_xlate_onetwocell, 286 }; 287 288 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */ 289 unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic) 290 { 291 int irq; 292 293 BUG_ON(qe_ic == NULL); 294 295 /* get the interrupt source vector. */ 296 irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26; 297 298 if (irq == 0) 299 return NO_IRQ; 300 301 return irq_linear_revmap(qe_ic->irqhost, irq); 302 } 303 304 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */ 305 unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic) 306 { 307 int irq; 308 309 BUG_ON(qe_ic == NULL); 310 311 /* get the interrupt source vector. */ 312 irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26; 313 314 if (irq == 0) 315 return NO_IRQ; 316 317 return irq_linear_revmap(qe_ic->irqhost, irq); 318 } 319 320 void __init qe_ic_init(struct device_node *node, unsigned int flags, 321 void (*low_handler)(struct irq_desc *desc), 322 void (*high_handler)(struct irq_desc *desc)) 323 { 324 struct qe_ic *qe_ic; 325 struct resource res; 326 u32 temp = 0, ret, high_active = 0; 327 328 ret = of_address_to_resource(node, 0, &res); 329 if (ret) 330 return; 331 332 qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL); 333 if (qe_ic == NULL) 334 return; 335 336 qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS, 337 &qe_ic_host_ops, qe_ic); 338 if (qe_ic->irqhost == NULL) { 339 kfree(qe_ic); 340 return; 341 } 342 343 qe_ic->regs = ioremap(res.start, resource_size(&res)); 344 345 qe_ic->hc_irq = qe_ic_irq_chip; 346 347 qe_ic->virq_high = irq_of_parse_and_map(node, 0); 348 qe_ic->virq_low = irq_of_parse_and_map(node, 1); 349 350 if (qe_ic->virq_low == NO_IRQ) { 351 printk(KERN_ERR "Failed to map QE_IC low IRQ\n"); 352 kfree(qe_ic); 353 return; 354 } 355 356 /* default priority scheme is grouped. If spread mode is */ 357 /* required, configure cicr accordingly. */ 358 if (flags & QE_IC_SPREADMODE_GRP_W) 359 temp |= CICR_GWCC; 360 if (flags & QE_IC_SPREADMODE_GRP_X) 361 temp |= CICR_GXCC; 362 if (flags & QE_IC_SPREADMODE_GRP_Y) 363 temp |= CICR_GYCC; 364 if (flags & QE_IC_SPREADMODE_GRP_Z) 365 temp |= CICR_GZCC; 366 if (flags & QE_IC_SPREADMODE_GRP_RISCA) 367 temp |= CICR_GRTA; 368 if (flags & QE_IC_SPREADMODE_GRP_RISCB) 369 temp |= CICR_GRTB; 370 371 /* choose destination signal for highest priority interrupt */ 372 if (flags & QE_IC_HIGH_SIGNAL) { 373 temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT); 374 high_active = 1; 375 } 376 377 qe_ic_write(qe_ic->regs, QEIC_CICR, temp); 378 379 irq_set_handler_data(qe_ic->virq_low, qe_ic); 380 irq_set_chained_handler(qe_ic->virq_low, low_handler); 381 382 if (qe_ic->virq_high != NO_IRQ && 383 qe_ic->virq_high != qe_ic->virq_low) { 384 irq_set_handler_data(qe_ic->virq_high, qe_ic); 385 irq_set_chained_handler(qe_ic->virq_high, high_handler); 386 } 387 } 388 389 void qe_ic_set_highest_priority(unsigned int virq, int high) 390 { 391 struct qe_ic *qe_ic = qe_ic_from_irq(virq); 392 unsigned int src = virq_to_hw(virq); 393 u32 temp = 0; 394 395 temp = qe_ic_read(qe_ic->regs, QEIC_CICR); 396 397 temp &= ~CICR_HP_MASK; 398 temp |= src << CICR_HP_SHIFT; 399 400 temp &= ~CICR_HPIT_MASK; 401 temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT; 402 403 qe_ic_write(qe_ic->regs, QEIC_CICR, temp); 404 } 405 406 /* Set Priority level within its group, from 1 to 8 */ 407 int qe_ic_set_priority(unsigned int virq, unsigned int priority) 408 { 409 struct qe_ic *qe_ic = qe_ic_from_irq(virq); 410 unsigned int src = virq_to_hw(virq); 411 u32 temp; 412 413 if (priority > 8 || priority == 0) 414 return -EINVAL; 415 if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info), 416 "%s: Invalid hw irq number for QEIC\n", __func__)) 417 return -EINVAL; 418 if (qe_ic_info[src].pri_reg == 0) 419 return -EINVAL; 420 421 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg); 422 423 if (priority < 4) { 424 temp &= ~(0x7 << (32 - priority * 3)); 425 temp |= qe_ic_info[src].pri_code << (32 - priority * 3); 426 } else { 427 temp &= ~(0x7 << (24 - priority * 3)); 428 temp |= qe_ic_info[src].pri_code << (24 - priority * 3); 429 } 430 431 qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp); 432 433 return 0; 434 } 435 436 /* Set a QE priority to use high irq, only priority 1~2 can use high irq */ 437 int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high) 438 { 439 struct qe_ic *qe_ic = qe_ic_from_irq(virq); 440 unsigned int src = virq_to_hw(virq); 441 u32 temp, control_reg = QEIC_CICNR, shift = 0; 442 443 if (priority > 2 || priority == 0) 444 return -EINVAL; 445 if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info), 446 "%s: Invalid hw irq number for QEIC\n", __func__)) 447 return -EINVAL; 448 449 switch (qe_ic_info[src].pri_reg) { 450 case QEIC_CIPZCC: 451 shift = CICNR_ZCC1T_SHIFT; 452 break; 453 case QEIC_CIPWCC: 454 shift = CICNR_WCC1T_SHIFT; 455 break; 456 case QEIC_CIPYCC: 457 shift = CICNR_YCC1T_SHIFT; 458 break; 459 case QEIC_CIPXCC: 460 shift = CICNR_XCC1T_SHIFT; 461 break; 462 case QEIC_CIPRTA: 463 shift = CRICR_RTA1T_SHIFT; 464 control_reg = QEIC_CRICR; 465 break; 466 case QEIC_CIPRTB: 467 shift = CRICR_RTB1T_SHIFT; 468 control_reg = QEIC_CRICR; 469 break; 470 default: 471 return -EINVAL; 472 } 473 474 shift += (2 - priority) * 2; 475 temp = qe_ic_read(qe_ic->regs, control_reg); 476 temp &= ~(SIGNAL_MASK << shift); 477 temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift; 478 qe_ic_write(qe_ic->regs, control_reg, temp); 479 480 return 0; 481 } 482 483 static struct bus_type qe_ic_subsys = { 484 .name = "qe_ic", 485 .dev_name = "qe_ic", 486 }; 487 488 static struct device device_qe_ic = { 489 .id = 0, 490 .bus = &qe_ic_subsys, 491 }; 492 493 static int __init init_qe_ic_sysfs(void) 494 { 495 int rc; 496 497 printk(KERN_DEBUG "Registering qe_ic with sysfs...\n"); 498 499 rc = subsys_system_register(&qe_ic_subsys, NULL); 500 if (rc) { 501 printk(KERN_ERR "Failed registering qe_ic sys class\n"); 502 return -ENODEV; 503 } 504 rc = device_register(&device_qe_ic); 505 if (rc) { 506 printk(KERN_ERR "Failed registering qe_ic sys device\n"); 507 return -ENODEV; 508 } 509 return 0; 510 } 511 512 subsys_initcall(init_qe_ic_sysfs); 513