1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * QUICC Engine GPIOs 4 * 5 * Copyright (c) MontaVista Software, Inc. 2008. 6 * 7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/spinlock.h> 13 #include <linux/err.h> 14 #include <linux/io.h> 15 #include <linux/of.h> 16 #include <linux/of_gpio.h> /* for of_mm_gpio_chip */ 17 #include <linux/gpio/consumer.h> 18 #include <linux/gpio/driver.h> 19 #include <linux/slab.h> 20 #include <linux/export.h> 21 #include <soc/fsl/qe/qe.h> 22 23 struct qe_gpio_chip { 24 struct of_mm_gpio_chip mm_gc; 25 spinlock_t lock; 26 27 /* shadowed data register to clear/set bits safely */ 28 u32 cpdata; 29 30 /* saved_regs used to restore dedicated functions */ 31 struct qe_pio_regs saved_regs; 32 }; 33 34 static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc) 35 { 36 struct qe_gpio_chip *qe_gc = 37 container_of(mm_gc, struct qe_gpio_chip, mm_gc); 38 struct qe_pio_regs __iomem *regs = mm_gc->regs; 39 40 qe_gc->cpdata = ioread32be(®s->cpdata); 41 qe_gc->saved_regs.cpdata = qe_gc->cpdata; 42 qe_gc->saved_regs.cpdir1 = ioread32be(®s->cpdir1); 43 qe_gc->saved_regs.cpdir2 = ioread32be(®s->cpdir2); 44 qe_gc->saved_regs.cppar1 = ioread32be(®s->cppar1); 45 qe_gc->saved_regs.cppar2 = ioread32be(®s->cppar2); 46 qe_gc->saved_regs.cpodr = ioread32be(®s->cpodr); 47 } 48 49 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio) 50 { 51 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 52 struct qe_pio_regs __iomem *regs = mm_gc->regs; 53 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); 54 55 return !!(ioread32be(®s->cpdata) & pin_mask); 56 } 57 58 static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 59 { 60 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 61 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc); 62 struct qe_pio_regs __iomem *regs = mm_gc->regs; 63 unsigned long flags; 64 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); 65 66 spin_lock_irqsave(&qe_gc->lock, flags); 67 68 if (val) 69 qe_gc->cpdata |= pin_mask; 70 else 71 qe_gc->cpdata &= ~pin_mask; 72 73 iowrite32be(qe_gc->cpdata, ®s->cpdata); 74 75 spin_unlock_irqrestore(&qe_gc->lock, flags); 76 } 77 78 static void qe_gpio_set_multiple(struct gpio_chip *gc, 79 unsigned long *mask, unsigned long *bits) 80 { 81 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 82 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc); 83 struct qe_pio_regs __iomem *regs = mm_gc->regs; 84 unsigned long flags; 85 int i; 86 87 spin_lock_irqsave(&qe_gc->lock, flags); 88 89 for (i = 0; i < gc->ngpio; i++) { 90 if (*mask == 0) 91 break; 92 if (__test_and_clear_bit(i, mask)) { 93 if (test_bit(i, bits)) 94 qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i)); 95 else 96 qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i)); 97 } 98 } 99 100 iowrite32be(qe_gc->cpdata, ®s->cpdata); 101 102 spin_unlock_irqrestore(&qe_gc->lock, flags); 103 } 104 105 static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 106 { 107 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 108 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc); 109 unsigned long flags; 110 111 spin_lock_irqsave(&qe_gc->lock, flags); 112 113 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0); 114 115 spin_unlock_irqrestore(&qe_gc->lock, flags); 116 117 return 0; 118 } 119 120 static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 121 { 122 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 123 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc); 124 unsigned long flags; 125 126 qe_gpio_set(gc, gpio, val); 127 128 spin_lock_irqsave(&qe_gc->lock, flags); 129 130 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0); 131 132 spin_unlock_irqrestore(&qe_gc->lock, flags); 133 134 return 0; 135 } 136 137 struct qe_pin { 138 /* 139 * The qe_gpio_chip name is unfortunate, we should change that to 140 * something like qe_pio_controller. Someday. 141 */ 142 struct qe_gpio_chip *controller; 143 int num; 144 }; 145 146 /** 147 * qe_pin_request - Request a QE pin 148 * @dev: device to get the pin from 149 * @index: index of the pin in the device tree 150 * Context: non-atomic 151 * 152 * This function return qe_pin so that you could use it with the rest of 153 * the QE Pin Multiplexing API. 154 */ 155 struct qe_pin *qe_pin_request(struct device *dev, int index) 156 { 157 struct qe_pin *qe_pin; 158 struct gpio_chip *gc; 159 struct gpio_desc *gpiod; 160 int gpio_num; 161 int err; 162 163 qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL); 164 if (!qe_pin) { 165 dev_dbg(dev, "%s: can't allocate memory\n", __func__); 166 return ERR_PTR(-ENOMEM); 167 } 168 169 /* 170 * Request gpio as nonexclusive as it was likely reserved by the 171 * caller, and we are not planning on controlling it, we only need 172 * the descriptor to the to the gpio chip structure. 173 */ 174 gpiod = gpiod_get_index(dev, NULL, index, 175 GPIOD_ASIS | GPIOD_FLAGS_BIT_NONEXCLUSIVE); 176 err = PTR_ERR_OR_ZERO(gpiod); 177 if (err) 178 goto err0; 179 180 gc = gpiod_to_chip(gpiod); 181 gpio_num = desc_to_gpio(gpiod); 182 /* We no longer need this descriptor */ 183 gpiod_put(gpiod); 184 185 if (WARN_ON(!gc)) { 186 err = -ENODEV; 187 goto err0; 188 } 189 190 qe_pin->controller = gpiochip_get_data(gc); 191 /* 192 * FIXME: this gets the local offset on the gpio_chip so that the driver 193 * can manipulate pin control settings through its custom API. The real 194 * solution is to create a real pin control driver for this. 195 */ 196 qe_pin->num = gpio_num - gc->base; 197 198 if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) { 199 dev_dbg(dev, "%s: tried to get a non-qe pin\n", __func__); 200 err = -EINVAL; 201 goto err0; 202 } 203 return qe_pin; 204 err0: 205 kfree(qe_pin); 206 dev_dbg(dev, "%s failed with status %d\n", __func__, err); 207 return ERR_PTR(err); 208 } 209 EXPORT_SYMBOL(qe_pin_request); 210 211 /** 212 * qe_pin_free - Free a pin 213 * @qe_pin: pointer to the qe_pin structure 214 * Context: any 215 * 216 * This function frees the qe_pin structure and makes a pin available 217 * for further qe_pin_request() calls. 218 */ 219 void qe_pin_free(struct qe_pin *qe_pin) 220 { 221 kfree(qe_pin); 222 } 223 EXPORT_SYMBOL(qe_pin_free); 224 225 /** 226 * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode 227 * @qe_pin: pointer to the qe_pin structure 228 * Context: any 229 * 230 * This function resets a pin to a dedicated peripheral function that 231 * has been set up by the firmware. 232 */ 233 void qe_pin_set_dedicated(struct qe_pin *qe_pin) 234 { 235 struct qe_gpio_chip *qe_gc = qe_pin->controller; 236 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs; 237 struct qe_pio_regs *sregs = &qe_gc->saved_regs; 238 int pin = qe_pin->num; 239 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1)); 240 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); 241 bool second_reg = pin > (QE_PIO_PINS / 2) - 1; 242 unsigned long flags; 243 244 spin_lock_irqsave(&qe_gc->lock, flags); 245 246 if (second_reg) { 247 qe_clrsetbits_be32(®s->cpdir2, mask2, 248 sregs->cpdir2 & mask2); 249 qe_clrsetbits_be32(®s->cppar2, mask2, 250 sregs->cppar2 & mask2); 251 } else { 252 qe_clrsetbits_be32(®s->cpdir1, mask2, 253 sregs->cpdir1 & mask2); 254 qe_clrsetbits_be32(®s->cppar1, mask2, 255 sregs->cppar1 & mask2); 256 } 257 258 if (sregs->cpdata & mask1) 259 qe_gc->cpdata |= mask1; 260 else 261 qe_gc->cpdata &= ~mask1; 262 263 iowrite32be(qe_gc->cpdata, ®s->cpdata); 264 qe_clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1); 265 266 spin_unlock_irqrestore(&qe_gc->lock, flags); 267 } 268 EXPORT_SYMBOL(qe_pin_set_dedicated); 269 270 /** 271 * qe_pin_set_gpio - Set a pin to the GPIO mode 272 * @qe_pin: pointer to the qe_pin structure 273 * Context: any 274 * 275 * This function sets a pin to the GPIO mode. 276 */ 277 void qe_pin_set_gpio(struct qe_pin *qe_pin) 278 { 279 struct qe_gpio_chip *qe_gc = qe_pin->controller; 280 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs; 281 unsigned long flags; 282 283 spin_lock_irqsave(&qe_gc->lock, flags); 284 285 /* Let's make it input by default, GPIO API is able to change that. */ 286 __par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0); 287 288 spin_unlock_irqrestore(&qe_gc->lock, flags); 289 } 290 EXPORT_SYMBOL(qe_pin_set_gpio); 291 292 static int __init qe_add_gpiochips(void) 293 { 294 struct device_node *np; 295 296 for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") { 297 int ret; 298 struct qe_gpio_chip *qe_gc; 299 struct of_mm_gpio_chip *mm_gc; 300 struct gpio_chip *gc; 301 302 qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL); 303 if (!qe_gc) { 304 ret = -ENOMEM; 305 goto err; 306 } 307 308 spin_lock_init(&qe_gc->lock); 309 310 mm_gc = &qe_gc->mm_gc; 311 gc = &mm_gc->gc; 312 313 mm_gc->save_regs = qe_gpio_save_regs; 314 gc->ngpio = QE_PIO_PINS; 315 gc->direction_input = qe_gpio_dir_in; 316 gc->direction_output = qe_gpio_dir_out; 317 gc->get = qe_gpio_get; 318 gc->set = qe_gpio_set; 319 gc->set_multiple = qe_gpio_set_multiple; 320 321 ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc); 322 if (ret) 323 goto err; 324 continue; 325 err: 326 pr_err("%pOF: registration failed with status %d\n", 327 np, ret); 328 kfree(qe_gc); 329 /* try others anyway */ 330 } 331 return 0; 332 } 333 arch_initcall(qe_add_gpiochips); 334