1 /* 2 * QUICC Engine GPIOs 3 * 4 * Copyright (c) MontaVista Software, Inc. 2008. 5 * 6 * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/init.h> 16 #include <linux/spinlock.h> 17 #include <linux/err.h> 18 #include <linux/io.h> 19 #include <linux/of.h> 20 #include <linux/of_gpio.h> 21 #include <linux/gpio/driver.h> 22 /* FIXME: needed for gpio_to_chip() get rid of this */ 23 #include <linux/gpio.h> 24 #include <linux/slab.h> 25 #include <linux/export.h> 26 #include <soc/fsl/qe/qe.h> 27 28 struct qe_gpio_chip { 29 struct of_mm_gpio_chip mm_gc; 30 spinlock_t lock; 31 32 unsigned long pin_flags[QE_PIO_PINS]; 33 #define QE_PIN_REQUESTED 0 34 35 /* shadowed data register to clear/set bits safely */ 36 u32 cpdata; 37 38 /* saved_regs used to restore dedicated functions */ 39 struct qe_pio_regs saved_regs; 40 }; 41 42 static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc) 43 { 44 struct qe_gpio_chip *qe_gc = 45 container_of(mm_gc, struct qe_gpio_chip, mm_gc); 46 struct qe_pio_regs __iomem *regs = mm_gc->regs; 47 48 qe_gc->cpdata = in_be32(®s->cpdata); 49 qe_gc->saved_regs.cpdata = qe_gc->cpdata; 50 qe_gc->saved_regs.cpdir1 = in_be32(®s->cpdir1); 51 qe_gc->saved_regs.cpdir2 = in_be32(®s->cpdir2); 52 qe_gc->saved_regs.cppar1 = in_be32(®s->cppar1); 53 qe_gc->saved_regs.cppar2 = in_be32(®s->cppar2); 54 qe_gc->saved_regs.cpodr = in_be32(®s->cpodr); 55 } 56 57 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio) 58 { 59 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 60 struct qe_pio_regs __iomem *regs = mm_gc->regs; 61 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); 62 63 return !!(in_be32(®s->cpdata) & pin_mask); 64 } 65 66 static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 67 { 68 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 69 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc); 70 struct qe_pio_regs __iomem *regs = mm_gc->regs; 71 unsigned long flags; 72 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); 73 74 spin_lock_irqsave(&qe_gc->lock, flags); 75 76 if (val) 77 qe_gc->cpdata |= pin_mask; 78 else 79 qe_gc->cpdata &= ~pin_mask; 80 81 out_be32(®s->cpdata, qe_gc->cpdata); 82 83 spin_unlock_irqrestore(&qe_gc->lock, flags); 84 } 85 86 static void qe_gpio_set_multiple(struct gpio_chip *gc, 87 unsigned long *mask, unsigned long *bits) 88 { 89 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 90 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc); 91 struct qe_pio_regs __iomem *regs = mm_gc->regs; 92 unsigned long flags; 93 int i; 94 95 spin_lock_irqsave(&qe_gc->lock, flags); 96 97 for (i = 0; i < gc->ngpio; i++) { 98 if (*mask == 0) 99 break; 100 if (__test_and_clear_bit(i, mask)) { 101 if (test_bit(i, bits)) 102 qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i)); 103 else 104 qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i)); 105 } 106 } 107 108 out_be32(®s->cpdata, qe_gc->cpdata); 109 110 spin_unlock_irqrestore(&qe_gc->lock, flags); 111 } 112 113 static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 114 { 115 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 116 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc); 117 unsigned long flags; 118 119 spin_lock_irqsave(&qe_gc->lock, flags); 120 121 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0); 122 123 spin_unlock_irqrestore(&qe_gc->lock, flags); 124 125 return 0; 126 } 127 128 static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 129 { 130 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 131 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc); 132 unsigned long flags; 133 134 qe_gpio_set(gc, gpio, val); 135 136 spin_lock_irqsave(&qe_gc->lock, flags); 137 138 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0); 139 140 spin_unlock_irqrestore(&qe_gc->lock, flags); 141 142 return 0; 143 } 144 145 struct qe_pin { 146 /* 147 * The qe_gpio_chip name is unfortunate, we should change that to 148 * something like qe_pio_controller. Someday. 149 */ 150 struct qe_gpio_chip *controller; 151 int num; 152 }; 153 154 /** 155 * qe_pin_request - Request a QE pin 156 * @np: device node to get a pin from 157 * @index: index of a pin in the device tree 158 * Context: non-atomic 159 * 160 * This function return qe_pin so that you could use it with the rest of 161 * the QE Pin Multiplexing API. 162 */ 163 struct qe_pin *qe_pin_request(struct device_node *np, int index) 164 { 165 struct qe_pin *qe_pin; 166 struct gpio_chip *gc; 167 struct of_mm_gpio_chip *mm_gc; 168 struct qe_gpio_chip *qe_gc; 169 int err; 170 unsigned long flags; 171 172 qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL); 173 if (!qe_pin) { 174 pr_debug("%s: can't allocate memory\n", __func__); 175 return ERR_PTR(-ENOMEM); 176 } 177 178 err = of_get_gpio(np, index); 179 if (err < 0) 180 goto err0; 181 gc = gpio_to_chip(err); 182 if (WARN_ON(!gc)) { 183 err = -ENODEV; 184 goto err0; 185 } 186 187 if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) { 188 pr_debug("%s: tried to get a non-qe pin\n", __func__); 189 err = -EINVAL; 190 goto err0; 191 } 192 193 mm_gc = to_of_mm_gpio_chip(gc); 194 qe_gc = gpiochip_get_data(gc); 195 196 spin_lock_irqsave(&qe_gc->lock, flags); 197 198 err -= gc->base; 199 if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) { 200 qe_pin->controller = qe_gc; 201 qe_pin->num = err; 202 err = 0; 203 } else { 204 err = -EBUSY; 205 } 206 207 spin_unlock_irqrestore(&qe_gc->lock, flags); 208 209 if (!err) 210 return qe_pin; 211 err0: 212 kfree(qe_pin); 213 pr_debug("%s failed with status %d\n", __func__, err); 214 return ERR_PTR(err); 215 } 216 EXPORT_SYMBOL(qe_pin_request); 217 218 /** 219 * qe_pin_free - Free a pin 220 * @qe_pin: pointer to the qe_pin structure 221 * Context: any 222 * 223 * This function frees the qe_pin structure and makes a pin available 224 * for further qe_pin_request() calls. 225 */ 226 void qe_pin_free(struct qe_pin *qe_pin) 227 { 228 struct qe_gpio_chip *qe_gc = qe_pin->controller; 229 unsigned long flags; 230 const int pin = qe_pin->num; 231 232 spin_lock_irqsave(&qe_gc->lock, flags); 233 test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]); 234 spin_unlock_irqrestore(&qe_gc->lock, flags); 235 236 kfree(qe_pin); 237 } 238 EXPORT_SYMBOL(qe_pin_free); 239 240 /** 241 * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode 242 * @qe_pin: pointer to the qe_pin structure 243 * Context: any 244 * 245 * This function resets a pin to a dedicated peripheral function that 246 * has been set up by the firmware. 247 */ 248 void qe_pin_set_dedicated(struct qe_pin *qe_pin) 249 { 250 struct qe_gpio_chip *qe_gc = qe_pin->controller; 251 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs; 252 struct qe_pio_regs *sregs = &qe_gc->saved_regs; 253 int pin = qe_pin->num; 254 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1)); 255 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); 256 bool second_reg = pin > (QE_PIO_PINS / 2) - 1; 257 unsigned long flags; 258 259 spin_lock_irqsave(&qe_gc->lock, flags); 260 261 if (second_reg) { 262 clrsetbits_be32(®s->cpdir2, mask2, sregs->cpdir2 & mask2); 263 clrsetbits_be32(®s->cppar2, mask2, sregs->cppar2 & mask2); 264 } else { 265 clrsetbits_be32(®s->cpdir1, mask2, sregs->cpdir1 & mask2); 266 clrsetbits_be32(®s->cppar1, mask2, sregs->cppar1 & mask2); 267 } 268 269 if (sregs->cpdata & mask1) 270 qe_gc->cpdata |= mask1; 271 else 272 qe_gc->cpdata &= ~mask1; 273 274 out_be32(®s->cpdata, qe_gc->cpdata); 275 clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1); 276 277 spin_unlock_irqrestore(&qe_gc->lock, flags); 278 } 279 EXPORT_SYMBOL(qe_pin_set_dedicated); 280 281 /** 282 * qe_pin_set_gpio - Set a pin to the GPIO mode 283 * @qe_pin: pointer to the qe_pin structure 284 * Context: any 285 * 286 * This function sets a pin to the GPIO mode. 287 */ 288 void qe_pin_set_gpio(struct qe_pin *qe_pin) 289 { 290 struct qe_gpio_chip *qe_gc = qe_pin->controller; 291 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs; 292 unsigned long flags; 293 294 spin_lock_irqsave(&qe_gc->lock, flags); 295 296 /* Let's make it input by default, GPIO API is able to change that. */ 297 __par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0); 298 299 spin_unlock_irqrestore(&qe_gc->lock, flags); 300 } 301 EXPORT_SYMBOL(qe_pin_set_gpio); 302 303 static int __init qe_add_gpiochips(void) 304 { 305 struct device_node *np; 306 307 for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") { 308 int ret; 309 struct qe_gpio_chip *qe_gc; 310 struct of_mm_gpio_chip *mm_gc; 311 struct gpio_chip *gc; 312 313 qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL); 314 if (!qe_gc) { 315 ret = -ENOMEM; 316 goto err; 317 } 318 319 spin_lock_init(&qe_gc->lock); 320 321 mm_gc = &qe_gc->mm_gc; 322 gc = &mm_gc->gc; 323 324 mm_gc->save_regs = qe_gpio_save_regs; 325 gc->ngpio = QE_PIO_PINS; 326 gc->direction_input = qe_gpio_dir_in; 327 gc->direction_output = qe_gpio_dir_out; 328 gc->get = qe_gpio_get; 329 gc->set = qe_gpio_set; 330 gc->set_multiple = qe_gpio_set_multiple; 331 332 ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc); 333 if (ret) 334 goto err; 335 continue; 336 err: 337 pr_err("%pOF: registration failed with status %d\n", 338 np, ret); 339 kfree(qe_gc); 340 /* try others anyway */ 341 } 342 return 0; 343 } 344 arch_initcall(qe_add_gpiochips); 345