1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc. 2 * 3 * Redistribution and use in source and binary forms, with or without 4 * modification, are permitted provided that the following conditions are met: 5 * * Redistributions of source code must retain the above copyright 6 * notice, this list of conditions and the following disclaimer. 7 * * Redistributions in binary form must reproduce the above copyright 8 * notice, this list of conditions and the following disclaimer in the 9 * documentation and/or other materials provided with the distribution. 10 * * Neither the name of Freescale Semiconductor nor the 11 * names of its contributors may be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * ALTERNATIVELY, this software may be distributed under the terms of the 15 * GNU General Public License ("GPL") as published by the Free Software 16 * Foundation, either version 2 of that License or (at your option) any 17 * later version. 18 * 19 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "qman_priv.h" 32 33 u16 qman_ip_rev; 34 EXPORT_SYMBOL(qman_ip_rev); 35 u16 qm_channel_pool1 = QMAN_CHANNEL_POOL1; 36 EXPORT_SYMBOL(qm_channel_pool1); 37 38 /* Register offsets */ 39 #define REG_QCSP_LIO_CFG(n) (0x0000 + ((n) * 0x10)) 40 #define REG_QCSP_IO_CFG(n) (0x0004 + ((n) * 0x10)) 41 #define REG_QCSP_DD_CFG(n) (0x000c + ((n) * 0x10)) 42 #define REG_DD_CFG 0x0200 43 #define REG_DCP_CFG(n) (0x0300 + ((n) * 0x10)) 44 #define REG_DCP_DD_CFG(n) (0x0304 + ((n) * 0x10)) 45 #define REG_DCP_DLM_AVG(n) (0x030c + ((n) * 0x10)) 46 #define REG_PFDR_FPC 0x0400 47 #define REG_PFDR_FP_HEAD 0x0404 48 #define REG_PFDR_FP_TAIL 0x0408 49 #define REG_PFDR_FP_LWIT 0x0410 50 #define REG_PFDR_CFG 0x0414 51 #define REG_SFDR_CFG 0x0500 52 #define REG_SFDR_IN_USE 0x0504 53 #define REG_WQ_CS_CFG(n) (0x0600 + ((n) * 0x04)) 54 #define REG_WQ_DEF_ENC_WQID 0x0630 55 #define REG_WQ_SC_DD_CFG(n) (0x640 + ((n) * 0x04)) 56 #define REG_WQ_PC_DD_CFG(n) (0x680 + ((n) * 0x04)) 57 #define REG_WQ_DC0_DD_CFG(n) (0x6c0 + ((n) * 0x04)) 58 #define REG_WQ_DC1_DD_CFG(n) (0x700 + ((n) * 0x04)) 59 #define REG_WQ_DCn_DD_CFG(n) (0x6c0 + ((n) * 0x40)) /* n=2,3 */ 60 #define REG_CM_CFG 0x0800 61 #define REG_ECSR 0x0a00 62 #define REG_ECIR 0x0a04 63 #define REG_EADR 0x0a08 64 #define REG_ECIR2 0x0a0c 65 #define REG_EDATA(n) (0x0a10 + ((n) * 0x04)) 66 #define REG_SBEC(n) (0x0a80 + ((n) * 0x04)) 67 #define REG_MCR 0x0b00 68 #define REG_MCP(n) (0x0b04 + ((n) * 0x04)) 69 #define REG_MISC_CFG 0x0be0 70 #define REG_HID_CFG 0x0bf0 71 #define REG_IDLE_STAT 0x0bf4 72 #define REG_IP_REV_1 0x0bf8 73 #define REG_IP_REV_2 0x0bfc 74 #define REG_FQD_BARE 0x0c00 75 #define REG_PFDR_BARE 0x0c20 76 #define REG_offset_BAR 0x0004 /* relative to REG_[FQD|PFDR]_BARE */ 77 #define REG_offset_AR 0x0010 /* relative to REG_[FQD|PFDR]_BARE */ 78 #define REG_QCSP_BARE 0x0c80 79 #define REG_QCSP_BAR 0x0c84 80 #define REG_CI_SCHED_CFG 0x0d00 81 #define REG_SRCIDR 0x0d04 82 #define REG_LIODNR 0x0d08 83 #define REG_CI_RLM_AVG 0x0d14 84 #define REG_ERR_ISR 0x0e00 85 #define REG_ERR_IER 0x0e04 86 #define REG_REV3_QCSP_LIO_CFG(n) (0x1000 + ((n) * 0x10)) 87 #define REG_REV3_QCSP_IO_CFG(n) (0x1004 + ((n) * 0x10)) 88 #define REG_REV3_QCSP_DD_CFG(n) (0x100c + ((n) * 0x10)) 89 90 /* Assists for QMAN_MCR */ 91 #define MCR_INIT_PFDR 0x01000000 92 #define MCR_get_rslt(v) (u8)((v) >> 24) 93 #define MCR_rslt_idle(r) (!(r) || ((r) >= 0xf0)) 94 #define MCR_rslt_ok(r) ((r) == 0xf0) 95 #define MCR_rslt_eaccess(r) ((r) == 0xf8) 96 #define MCR_rslt_inval(r) ((r) == 0xff) 97 98 /* 99 * Corenet initiator settings. Stash request queues are 4-deep to match cores 100 * ability to snarf. Stash priority is 3, other priorities are 2. 101 */ 102 #define QM_CI_SCHED_CFG_SRCCIV 4 103 #define QM_CI_SCHED_CFG_SRQ_W 3 104 #define QM_CI_SCHED_CFG_RW_W 2 105 #define QM_CI_SCHED_CFG_BMAN_W 2 106 /* write SRCCIV enable */ 107 #define QM_CI_SCHED_CFG_SRCCIV_EN BIT(31) 108 109 /* Follows WQ_CS_CFG0-5 */ 110 enum qm_wq_class { 111 qm_wq_portal = 0, 112 qm_wq_pool = 1, 113 qm_wq_fman0 = 2, 114 qm_wq_fman1 = 3, 115 qm_wq_caam = 4, 116 qm_wq_pme = 5, 117 qm_wq_first = qm_wq_portal, 118 qm_wq_last = qm_wq_pme 119 }; 120 121 /* Follows FQD_[BARE|BAR|AR] and PFDR_[BARE|BAR|AR] */ 122 enum qm_memory { 123 qm_memory_fqd, 124 qm_memory_pfdr 125 }; 126 127 /* Used by all error interrupt registers except 'inhibit' */ 128 #define QM_EIRQ_CIDE 0x20000000 /* Corenet Initiator Data Error */ 129 #define QM_EIRQ_CTDE 0x10000000 /* Corenet Target Data Error */ 130 #define QM_EIRQ_CITT 0x08000000 /* Corenet Invalid Target Transaction */ 131 #define QM_EIRQ_PLWI 0x04000000 /* PFDR Low Watermark */ 132 #define QM_EIRQ_MBEI 0x02000000 /* Multi-bit ECC Error */ 133 #define QM_EIRQ_SBEI 0x01000000 /* Single-bit ECC Error */ 134 #define QM_EIRQ_PEBI 0x00800000 /* PFDR Enqueues Blocked Interrupt */ 135 #define QM_EIRQ_IFSI 0x00020000 /* Invalid FQ Flow Control State */ 136 #define QM_EIRQ_ICVI 0x00010000 /* Invalid Command Verb */ 137 #define QM_EIRQ_IDDI 0x00000800 /* Invalid Dequeue (Direct-connect) */ 138 #define QM_EIRQ_IDFI 0x00000400 /* Invalid Dequeue FQ */ 139 #define QM_EIRQ_IDSI 0x00000200 /* Invalid Dequeue Source */ 140 #define QM_EIRQ_IDQI 0x00000100 /* Invalid Dequeue Queue */ 141 #define QM_EIRQ_IECE 0x00000010 /* Invalid Enqueue Configuration */ 142 #define QM_EIRQ_IEOI 0x00000008 /* Invalid Enqueue Overflow */ 143 #define QM_EIRQ_IESI 0x00000004 /* Invalid Enqueue State */ 144 #define QM_EIRQ_IECI 0x00000002 /* Invalid Enqueue Channel */ 145 #define QM_EIRQ_IEQI 0x00000001 /* Invalid Enqueue Queue */ 146 147 /* QMAN_ECIR valid error bit */ 148 #define PORTAL_ECSR_ERR (QM_EIRQ_IEQI | QM_EIRQ_IESI | QM_EIRQ_IEOI | \ 149 QM_EIRQ_IDQI | QM_EIRQ_IDSI | QM_EIRQ_IDFI | \ 150 QM_EIRQ_IDDI | QM_EIRQ_ICVI | QM_EIRQ_IFSI) 151 #define FQID_ECSR_ERR (QM_EIRQ_IEQI | QM_EIRQ_IECI | QM_EIRQ_IESI | \ 152 QM_EIRQ_IEOI | QM_EIRQ_IDQI | QM_EIRQ_IDFI | \ 153 QM_EIRQ_IFSI) 154 155 struct qm_ecir { 156 u32 info; /* res[30-31], ptyp[29], pnum[24-28], fqid[0-23] */ 157 }; 158 159 static bool qm_ecir_is_dcp(const struct qm_ecir *p) 160 { 161 return p->info & BIT(29); 162 } 163 164 static int qm_ecir_get_pnum(const struct qm_ecir *p) 165 { 166 return (p->info >> 24) & 0x1f; 167 } 168 169 static int qm_ecir_get_fqid(const struct qm_ecir *p) 170 { 171 return p->info & (BIT(24) - 1); 172 } 173 174 struct qm_ecir2 { 175 u32 info; /* ptyp[31], res[10-30], pnum[0-9] */ 176 }; 177 178 static bool qm_ecir2_is_dcp(const struct qm_ecir2 *p) 179 { 180 return p->info & BIT(31); 181 } 182 183 static int qm_ecir2_get_pnum(const struct qm_ecir2 *p) 184 { 185 return p->info & (BIT(10) - 1); 186 } 187 188 struct qm_eadr { 189 u32 info; /* memid[24-27], eadr[0-11] */ 190 /* v3: memid[24-28], eadr[0-15] */ 191 }; 192 193 static int qm_eadr_get_memid(const struct qm_eadr *p) 194 { 195 return (p->info >> 24) & 0xf; 196 } 197 198 static int qm_eadr_get_eadr(const struct qm_eadr *p) 199 { 200 return p->info & (BIT(12) - 1); 201 } 202 203 static int qm_eadr_v3_get_memid(const struct qm_eadr *p) 204 { 205 return (p->info >> 24) & 0x1f; 206 } 207 208 static int qm_eadr_v3_get_eadr(const struct qm_eadr *p) 209 { 210 return p->info & (BIT(16) - 1); 211 } 212 213 struct qman_hwerr_txt { 214 u32 mask; 215 const char *txt; 216 }; 217 218 219 static const struct qman_hwerr_txt qman_hwerr_txts[] = { 220 { QM_EIRQ_CIDE, "Corenet Initiator Data Error" }, 221 { QM_EIRQ_CTDE, "Corenet Target Data Error" }, 222 { QM_EIRQ_CITT, "Corenet Invalid Target Transaction" }, 223 { QM_EIRQ_PLWI, "PFDR Low Watermark" }, 224 { QM_EIRQ_MBEI, "Multi-bit ECC Error" }, 225 { QM_EIRQ_SBEI, "Single-bit ECC Error" }, 226 { QM_EIRQ_PEBI, "PFDR Enqueues Blocked Interrupt" }, 227 { QM_EIRQ_ICVI, "Invalid Command Verb" }, 228 { QM_EIRQ_IFSI, "Invalid Flow Control State" }, 229 { QM_EIRQ_IDDI, "Invalid Dequeue (Direct-connect)" }, 230 { QM_EIRQ_IDFI, "Invalid Dequeue FQ" }, 231 { QM_EIRQ_IDSI, "Invalid Dequeue Source" }, 232 { QM_EIRQ_IDQI, "Invalid Dequeue Queue" }, 233 { QM_EIRQ_IECE, "Invalid Enqueue Configuration" }, 234 { QM_EIRQ_IEOI, "Invalid Enqueue Overflow" }, 235 { QM_EIRQ_IESI, "Invalid Enqueue State" }, 236 { QM_EIRQ_IECI, "Invalid Enqueue Channel" }, 237 { QM_EIRQ_IEQI, "Invalid Enqueue Queue" }, 238 }; 239 240 struct qman_error_info_mdata { 241 u16 addr_mask; 242 u16 bits; 243 const char *txt; 244 }; 245 246 static const struct qman_error_info_mdata error_mdata[] = { 247 { 0x01FF, 24, "FQD cache tag memory 0" }, 248 { 0x01FF, 24, "FQD cache tag memory 1" }, 249 { 0x01FF, 24, "FQD cache tag memory 2" }, 250 { 0x01FF, 24, "FQD cache tag memory 3" }, 251 { 0x0FFF, 512, "FQD cache memory" }, 252 { 0x07FF, 128, "SFDR memory" }, 253 { 0x01FF, 72, "WQ context memory" }, 254 { 0x00FF, 240, "CGR memory" }, 255 { 0x00FF, 302, "Internal Order Restoration List memory" }, 256 { 0x01FF, 256, "SW portal ring memory" }, 257 }; 258 259 #define QMAN_ERRS_TO_DISABLE (QM_EIRQ_PLWI | QM_EIRQ_PEBI) 260 261 /* 262 * TODO: unimplemented registers 263 * 264 * Keeping a list here of QMan registers I have not yet covered; 265 * QCSP_DD_IHRSR, QCSP_DD_IHRFR, QCSP_DD_HASR, 266 * DCP_DD_IHRSR, DCP_DD_IHRFR, DCP_DD_HASR, CM_CFG, 267 * QMAN_EECC, QMAN_SBET, QMAN_EINJ, QMAN_SBEC0-12 268 */ 269 270 /* Pointer to the start of the QMan's CCSR space */ 271 static u32 __iomem *qm_ccsr_start; 272 /* A SDQCR mask comprising all the available/visible pool channels */ 273 static u32 qm_pools_sdqcr; 274 275 static inline u32 qm_ccsr_in(u32 offset) 276 { 277 return ioread32be(qm_ccsr_start + offset/4); 278 } 279 280 static inline void qm_ccsr_out(u32 offset, u32 val) 281 { 282 iowrite32be(val, qm_ccsr_start + offset/4); 283 } 284 285 u32 qm_get_pools_sdqcr(void) 286 { 287 return qm_pools_sdqcr; 288 } 289 290 enum qm_dc_portal { 291 qm_dc_portal_fman0 = 0, 292 qm_dc_portal_fman1 = 1 293 }; 294 295 static void qm_set_dc(enum qm_dc_portal portal, int ed, u8 sernd) 296 { 297 DPAA_ASSERT(!ed || portal == qm_dc_portal_fman0 || 298 portal == qm_dc_portal_fman1); 299 if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) 300 qm_ccsr_out(REG_DCP_CFG(portal), 301 (ed ? 0x1000 : 0) | (sernd & 0x3ff)); 302 else 303 qm_ccsr_out(REG_DCP_CFG(portal), 304 (ed ? 0x100 : 0) | (sernd & 0x1f)); 305 } 306 307 static void qm_set_wq_scheduling(enum qm_wq_class wq_class, 308 u8 cs_elev, u8 csw2, u8 csw3, u8 csw4, 309 u8 csw5, u8 csw6, u8 csw7) 310 { 311 qm_ccsr_out(REG_WQ_CS_CFG(wq_class), ((cs_elev & 0xff) << 24) | 312 ((csw2 & 0x7) << 20) | ((csw3 & 0x7) << 16) | 313 ((csw4 & 0x7) << 12) | ((csw5 & 0x7) << 8) | 314 ((csw6 & 0x7) << 4) | (csw7 & 0x7)); 315 } 316 317 static void qm_set_hid(void) 318 { 319 qm_ccsr_out(REG_HID_CFG, 0); 320 } 321 322 static void qm_set_corenet_initiator(void) 323 { 324 qm_ccsr_out(REG_CI_SCHED_CFG, QM_CI_SCHED_CFG_SRCCIV_EN | 325 (QM_CI_SCHED_CFG_SRCCIV << 24) | 326 (QM_CI_SCHED_CFG_SRQ_W << 8) | 327 (QM_CI_SCHED_CFG_RW_W << 4) | 328 QM_CI_SCHED_CFG_BMAN_W); 329 } 330 331 static void qm_get_version(u16 *id, u8 *major, u8 *minor) 332 { 333 u32 v = qm_ccsr_in(REG_IP_REV_1); 334 *id = (v >> 16); 335 *major = (v >> 8) & 0xff; 336 *minor = v & 0xff; 337 } 338 339 #define PFDR_AR_EN BIT(31) 340 static void qm_set_memory(enum qm_memory memory, u64 ba, u32 size) 341 { 342 u32 offset = (memory == qm_memory_fqd) ? REG_FQD_BARE : REG_PFDR_BARE; 343 u32 exp = ilog2(size); 344 345 /* choke if size isn't within range */ 346 DPAA_ASSERT((size >= 4096) && (size <= 1024*1024*1024) && 347 is_power_of_2(size)); 348 /* choke if 'ba' has lower-alignment than 'size' */ 349 DPAA_ASSERT(!(ba & (size - 1))); 350 qm_ccsr_out(offset, upper_32_bits(ba)); 351 qm_ccsr_out(offset + REG_offset_BAR, lower_32_bits(ba)); 352 qm_ccsr_out(offset + REG_offset_AR, PFDR_AR_EN | (exp - 1)); 353 } 354 355 static void qm_set_pfdr_threshold(u32 th, u8 k) 356 { 357 qm_ccsr_out(REG_PFDR_FP_LWIT, th & 0xffffff); 358 qm_ccsr_out(REG_PFDR_CFG, k); 359 } 360 361 static void qm_set_sfdr_threshold(u16 th) 362 { 363 qm_ccsr_out(REG_SFDR_CFG, th & 0x3ff); 364 } 365 366 static int qm_init_pfdr(struct device *dev, u32 pfdr_start, u32 num) 367 { 368 u8 rslt = MCR_get_rslt(qm_ccsr_in(REG_MCR)); 369 370 DPAA_ASSERT(pfdr_start && !(pfdr_start & 7) && !(num & 7) && num); 371 /* Make sure the command interface is 'idle' */ 372 if (!MCR_rslt_idle(rslt)) { 373 dev_crit(dev, "QMAN_MCR isn't idle"); 374 WARN_ON(1); 375 } 376 377 /* Write the MCR command params then the verb */ 378 qm_ccsr_out(REG_MCP(0), pfdr_start); 379 /* 380 * TODO: remove this - it's a workaround for a model bug that is 381 * corrected in more recent versions. We use the workaround until 382 * everyone has upgraded. 383 */ 384 qm_ccsr_out(REG_MCP(1), pfdr_start + num - 16); 385 dma_wmb(); 386 qm_ccsr_out(REG_MCR, MCR_INIT_PFDR); 387 /* Poll for the result */ 388 do { 389 rslt = MCR_get_rslt(qm_ccsr_in(REG_MCR)); 390 } while (!MCR_rslt_idle(rslt)); 391 if (MCR_rslt_ok(rslt)) 392 return 0; 393 if (MCR_rslt_eaccess(rslt)) 394 return -EACCES; 395 if (MCR_rslt_inval(rslt)) 396 return -EINVAL; 397 dev_crit(dev, "Unexpected result from MCR_INIT_PFDR: %02x\n", rslt); 398 return -ENODEV; 399 } 400 401 /* 402 * Ideally we would use the DMA API to turn rmem->base into a DMA address 403 * (especially if iommu translations ever get involved). Unfortunately, the 404 * DMA API currently does not allow mapping anything that is not backed with 405 * a struct page. 406 */ 407 static dma_addr_t fqd_a, pfdr_a; 408 static size_t fqd_sz, pfdr_sz; 409 410 static int qman_fqd(struct reserved_mem *rmem) 411 { 412 fqd_a = rmem->base; 413 fqd_sz = rmem->size; 414 415 WARN_ON(!(fqd_a && fqd_sz)); 416 417 return 0; 418 } 419 RESERVEDMEM_OF_DECLARE(qman_fqd, "fsl,qman-fqd", qman_fqd); 420 421 static int qman_pfdr(struct reserved_mem *rmem) 422 { 423 pfdr_a = rmem->base; 424 pfdr_sz = rmem->size; 425 426 WARN_ON(!(pfdr_a && pfdr_sz)); 427 428 return 0; 429 } 430 RESERVEDMEM_OF_DECLARE(qman_pfdr, "fsl,qman-pfdr", qman_pfdr); 431 432 static unsigned int qm_get_fqid_maxcnt(void) 433 { 434 return fqd_sz / 64; 435 } 436 437 /* 438 * Flush this memory range from data cache so that QMAN originated 439 * transactions for this memory region could be marked non-coherent. 440 */ 441 static int zero_priv_mem(struct device *dev, struct device_node *node, 442 phys_addr_t addr, size_t sz) 443 { 444 /* map as cacheable, non-guarded */ 445 void __iomem *tmpp = ioremap_prot(addr, sz, 0); 446 447 memset_io(tmpp, 0, sz); 448 flush_dcache_range((unsigned long)tmpp, 449 (unsigned long)tmpp + sz); 450 iounmap(tmpp); 451 452 return 0; 453 } 454 455 static void log_edata_bits(struct device *dev, u32 bit_count) 456 { 457 u32 i, j, mask = 0xffffffff; 458 459 dev_warn(dev, "ErrInt, EDATA:\n"); 460 i = bit_count / 32; 461 if (bit_count % 32) { 462 i++; 463 mask = ~(mask << bit_count % 32); 464 } 465 j = 16 - i; 466 dev_warn(dev, " 0x%08x\n", qm_ccsr_in(REG_EDATA(j)) & mask); 467 j++; 468 for (; j < 16; j++) 469 dev_warn(dev, " 0x%08x\n", qm_ccsr_in(REG_EDATA(j))); 470 } 471 472 static void log_additional_error_info(struct device *dev, u32 isr_val, 473 u32 ecsr_val) 474 { 475 struct qm_ecir ecir_val; 476 struct qm_eadr eadr_val; 477 int memid; 478 479 ecir_val.info = qm_ccsr_in(REG_ECIR); 480 /* Is portal info valid */ 481 if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) { 482 struct qm_ecir2 ecir2_val; 483 484 ecir2_val.info = qm_ccsr_in(REG_ECIR2); 485 if (ecsr_val & PORTAL_ECSR_ERR) { 486 dev_warn(dev, "ErrInt: %s id %d\n", 487 qm_ecir2_is_dcp(&ecir2_val) ? "DCP" : "SWP", 488 qm_ecir2_get_pnum(&ecir2_val)); 489 } 490 if (ecsr_val & (FQID_ECSR_ERR | QM_EIRQ_IECE)) 491 dev_warn(dev, "ErrInt: ecir.fqid 0x%x\n", 492 qm_ecir_get_fqid(&ecir_val)); 493 494 if (ecsr_val & (QM_EIRQ_SBEI|QM_EIRQ_MBEI)) { 495 eadr_val.info = qm_ccsr_in(REG_EADR); 496 memid = qm_eadr_v3_get_memid(&eadr_val); 497 dev_warn(dev, "ErrInt: EADR Memory: %s, 0x%x\n", 498 error_mdata[memid].txt, 499 error_mdata[memid].addr_mask 500 & qm_eadr_v3_get_eadr(&eadr_val)); 501 log_edata_bits(dev, error_mdata[memid].bits); 502 } 503 } else { 504 if (ecsr_val & PORTAL_ECSR_ERR) { 505 dev_warn(dev, "ErrInt: %s id %d\n", 506 qm_ecir_is_dcp(&ecir_val) ? "DCP" : "SWP", 507 qm_ecir_get_pnum(&ecir_val)); 508 } 509 if (ecsr_val & FQID_ECSR_ERR) 510 dev_warn(dev, "ErrInt: ecir.fqid 0x%x\n", 511 qm_ecir_get_fqid(&ecir_val)); 512 513 if (ecsr_val & (QM_EIRQ_SBEI|QM_EIRQ_MBEI)) { 514 eadr_val.info = qm_ccsr_in(REG_EADR); 515 memid = qm_eadr_get_memid(&eadr_val); 516 dev_warn(dev, "ErrInt: EADR Memory: %s, 0x%x\n", 517 error_mdata[memid].txt, 518 error_mdata[memid].addr_mask 519 & qm_eadr_get_eadr(&eadr_val)); 520 log_edata_bits(dev, error_mdata[memid].bits); 521 } 522 } 523 } 524 525 static irqreturn_t qman_isr(int irq, void *ptr) 526 { 527 u32 isr_val, ier_val, ecsr_val, isr_mask, i; 528 struct device *dev = ptr; 529 530 ier_val = qm_ccsr_in(REG_ERR_IER); 531 isr_val = qm_ccsr_in(REG_ERR_ISR); 532 ecsr_val = qm_ccsr_in(REG_ECSR); 533 isr_mask = isr_val & ier_val; 534 535 if (!isr_mask) 536 return IRQ_NONE; 537 538 for (i = 0; i < ARRAY_SIZE(qman_hwerr_txts); i++) { 539 if (qman_hwerr_txts[i].mask & isr_mask) { 540 dev_err_ratelimited(dev, "ErrInt: %s\n", 541 qman_hwerr_txts[i].txt); 542 if (qman_hwerr_txts[i].mask & ecsr_val) { 543 log_additional_error_info(dev, isr_mask, 544 ecsr_val); 545 /* Re-arm error capture registers */ 546 qm_ccsr_out(REG_ECSR, ecsr_val); 547 } 548 if (qman_hwerr_txts[i].mask & QMAN_ERRS_TO_DISABLE) { 549 dev_dbg(dev, "Disabling error 0x%x\n", 550 qman_hwerr_txts[i].mask); 551 ier_val &= ~qman_hwerr_txts[i].mask; 552 qm_ccsr_out(REG_ERR_IER, ier_val); 553 } 554 } 555 } 556 qm_ccsr_out(REG_ERR_ISR, isr_val); 557 558 return IRQ_HANDLED; 559 } 560 561 static int qman_init_ccsr(struct device *dev) 562 { 563 int i, err; 564 565 /* FQD memory */ 566 qm_set_memory(qm_memory_fqd, fqd_a, fqd_sz); 567 /* PFDR memory */ 568 qm_set_memory(qm_memory_pfdr, pfdr_a, pfdr_sz); 569 err = qm_init_pfdr(dev, 8, pfdr_sz / 64 - 8); 570 if (err) 571 return err; 572 /* thresholds */ 573 qm_set_pfdr_threshold(512, 64); 574 qm_set_sfdr_threshold(128); 575 /* clear stale PEBI bit from interrupt status register */ 576 qm_ccsr_out(REG_ERR_ISR, QM_EIRQ_PEBI); 577 /* corenet initiator settings */ 578 qm_set_corenet_initiator(); 579 /* HID settings */ 580 qm_set_hid(); 581 /* Set scheduling weights to defaults */ 582 for (i = qm_wq_first; i <= qm_wq_last; i++) 583 qm_set_wq_scheduling(i, 0, 0, 0, 0, 0, 0, 0); 584 /* We are not prepared to accept ERNs for hardware enqueues */ 585 qm_set_dc(qm_dc_portal_fman0, 1, 0); 586 qm_set_dc(qm_dc_portal_fman1, 1, 0); 587 return 0; 588 } 589 590 #define LIO_CFG_LIODN_MASK 0x0fff0000 591 void qman_liodn_fixup(u16 channel) 592 { 593 static int done; 594 static u32 liodn_offset; 595 u32 before, after; 596 int idx = channel - QM_CHANNEL_SWPORTAL0; 597 598 if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) 599 before = qm_ccsr_in(REG_REV3_QCSP_LIO_CFG(idx)); 600 else 601 before = qm_ccsr_in(REG_QCSP_LIO_CFG(idx)); 602 if (!done) { 603 liodn_offset = before & LIO_CFG_LIODN_MASK; 604 done = 1; 605 return; 606 } 607 after = (before & (~LIO_CFG_LIODN_MASK)) | liodn_offset; 608 if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) 609 qm_ccsr_out(REG_REV3_QCSP_LIO_CFG(idx), after); 610 else 611 qm_ccsr_out(REG_QCSP_LIO_CFG(idx), after); 612 } 613 614 #define IO_CFG_SDEST_MASK 0x00ff0000 615 void qman_set_sdest(u16 channel, unsigned int cpu_idx) 616 { 617 int idx = channel - QM_CHANNEL_SWPORTAL0; 618 u32 before, after; 619 620 if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) { 621 before = qm_ccsr_in(REG_REV3_QCSP_IO_CFG(idx)); 622 /* Each pair of vcpu share the same SRQ(SDEST) */ 623 cpu_idx /= 2; 624 after = (before & (~IO_CFG_SDEST_MASK)) | (cpu_idx << 16); 625 qm_ccsr_out(REG_REV3_QCSP_IO_CFG(idx), after); 626 } else { 627 before = qm_ccsr_in(REG_QCSP_IO_CFG(idx)); 628 after = (before & (~IO_CFG_SDEST_MASK)) | (cpu_idx << 16); 629 qm_ccsr_out(REG_QCSP_IO_CFG(idx), after); 630 } 631 } 632 633 static int qman_resource_init(struct device *dev) 634 { 635 int pool_chan_num, cgrid_num; 636 int ret, i; 637 638 switch (qman_ip_rev >> 8) { 639 case 1: 640 pool_chan_num = 15; 641 cgrid_num = 256; 642 break; 643 case 2: 644 pool_chan_num = 3; 645 cgrid_num = 64; 646 break; 647 case 3: 648 pool_chan_num = 15; 649 cgrid_num = 256; 650 break; 651 default: 652 return -ENODEV; 653 } 654 655 ret = gen_pool_add(qm_qpalloc, qm_channel_pool1 | DPAA_GENALLOC_OFF, 656 pool_chan_num, -1); 657 if (ret) { 658 dev_err(dev, "Failed to seed pool channels (%d)\n", ret); 659 return ret; 660 } 661 662 ret = gen_pool_add(qm_cgralloc, DPAA_GENALLOC_OFF, cgrid_num, -1); 663 if (ret) { 664 dev_err(dev, "Failed to seed CGRID range (%d)\n", ret); 665 return ret; 666 } 667 668 /* parse pool channels into the SDQCR mask */ 669 for (i = 0; i < cgrid_num; i++) 670 qm_pools_sdqcr |= QM_SDQCR_CHANNELS_POOL_CONV(i); 671 672 ret = gen_pool_add(qm_fqalloc, QM_FQID_RANGE_START | DPAA_GENALLOC_OFF, 673 qm_get_fqid_maxcnt() - QM_FQID_RANGE_START, -1); 674 if (ret) { 675 dev_err(dev, "Failed to seed FQID range (%d)\n", ret); 676 return ret; 677 } 678 679 return 0; 680 } 681 682 static int fsl_qman_probe(struct platform_device *pdev) 683 { 684 struct device *dev = &pdev->dev; 685 struct device_node *node = dev->of_node; 686 struct resource *res; 687 int ret, err_irq; 688 u16 id; 689 u8 major, minor; 690 691 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 692 if (!res) { 693 dev_err(dev, "Can't get %s property 'IORESOURCE_MEM'\n", 694 node->full_name); 695 return -ENXIO; 696 } 697 qm_ccsr_start = devm_ioremap(dev, res->start, resource_size(res)); 698 if (!qm_ccsr_start) 699 return -ENXIO; 700 701 qm_get_version(&id, &major, &minor); 702 if (major == 1 && minor == 0) { 703 dev_err(dev, "Rev1.0 on P4080 rev1 is not supported!\n"); 704 return -ENODEV; 705 } else if (major == 1 && minor == 1) 706 qman_ip_rev = QMAN_REV11; 707 else if (major == 1 && minor == 2) 708 qman_ip_rev = QMAN_REV12; 709 else if (major == 2 && minor == 0) 710 qman_ip_rev = QMAN_REV20; 711 else if (major == 3 && minor == 0) 712 qman_ip_rev = QMAN_REV30; 713 else if (major == 3 && minor == 1) 714 qman_ip_rev = QMAN_REV31; 715 else { 716 dev_err(dev, "Unknown QMan version\n"); 717 return -ENODEV; 718 } 719 720 if ((qman_ip_rev & 0xff00) >= QMAN_REV30) 721 qm_channel_pool1 = QMAN_CHANNEL_POOL1_REV3; 722 723 ret = zero_priv_mem(dev, node, fqd_a, fqd_sz); 724 WARN_ON(ret); 725 if (ret) 726 return -ENODEV; 727 728 ret = qman_init_ccsr(dev); 729 if (ret) { 730 dev_err(dev, "CCSR setup failed\n"); 731 return ret; 732 } 733 734 err_irq = platform_get_irq(pdev, 0); 735 if (err_irq <= 0) { 736 dev_info(dev, "Can't get %s property 'interrupts'\n", 737 node->full_name); 738 return -ENODEV; 739 } 740 ret = devm_request_irq(dev, err_irq, qman_isr, IRQF_SHARED, "qman-err", 741 dev); 742 if (ret) { 743 dev_err(dev, "devm_request_irq() failed %d for '%s'\n", 744 ret, node->full_name); 745 return ret; 746 } 747 748 /* 749 * Write-to-clear any stale bits, (eg. starvation being asserted prior 750 * to resource allocation during driver init). 751 */ 752 qm_ccsr_out(REG_ERR_ISR, 0xffffffff); 753 /* Enable Error Interrupts */ 754 qm_ccsr_out(REG_ERR_IER, 0xffffffff); 755 756 qm_fqalloc = devm_gen_pool_create(dev, 0, -1, "qman-fqalloc"); 757 if (IS_ERR(qm_fqalloc)) { 758 ret = PTR_ERR(qm_fqalloc); 759 dev_err(dev, "qman-fqalloc pool init failed (%d)\n", ret); 760 return ret; 761 } 762 763 qm_qpalloc = devm_gen_pool_create(dev, 0, -1, "qman-qpalloc"); 764 if (IS_ERR(qm_qpalloc)) { 765 ret = PTR_ERR(qm_qpalloc); 766 dev_err(dev, "qman-qpalloc pool init failed (%d)\n", ret); 767 return ret; 768 } 769 770 qm_cgralloc = devm_gen_pool_create(dev, 0, -1, "qman-cgralloc"); 771 if (IS_ERR(qm_cgralloc)) { 772 ret = PTR_ERR(qm_cgralloc); 773 dev_err(dev, "qman-cgralloc pool init failed (%d)\n", ret); 774 return ret; 775 } 776 777 ret = qman_resource_init(dev); 778 if (ret) 779 return ret; 780 781 ret = qman_alloc_fq_table(qm_get_fqid_maxcnt()); 782 if (ret) 783 return ret; 784 785 ret = qman_wq_alloc(); 786 if (ret) 787 return ret; 788 789 return 0; 790 } 791 792 static const struct of_device_id fsl_qman_ids[] = { 793 { 794 .compatible = "fsl,qman", 795 }, 796 {} 797 }; 798 799 static struct platform_driver fsl_qman_driver = { 800 .driver = { 801 .name = KBUILD_MODNAME, 802 .of_match_table = fsl_qman_ids, 803 .suppress_bind_attrs = true, 804 }, 805 .probe = fsl_qman_probe, 806 }; 807 808 builtin_platform_driver(fsl_qman_driver); 809