1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc. 2 * 3 * Redistribution and use in source and binary forms, with or without 4 * modification, are permitted provided that the following conditions are met: 5 * * Redistributions of source code must retain the above copyright 6 * notice, this list of conditions and the following disclaimer. 7 * * Redistributions in binary form must reproduce the above copyright 8 * notice, this list of conditions and the following disclaimer in the 9 * documentation and/or other materials provided with the distribution. 10 * * Neither the name of Freescale Semiconductor nor the 11 * names of its contributors may be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * ALTERNATIVELY, this software may be distributed under the terms of the 15 * GNU General Public License ("GPL") as published by the Free Software 16 * Foundation, either version 2 of that License or (at your option) any 17 * later version. 18 * 19 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "qman_priv.h" 32 33 #define DQRR_MAXFILL 15 34 #define EQCR_ITHRESH 4 /* if EQCR congests, interrupt threshold */ 35 #define IRQNAME "QMan portal %d" 36 #define MAX_IRQNAME 16 /* big enough for "QMan portal %d" */ 37 #define QMAN_POLL_LIMIT 32 38 #define QMAN_PIRQ_DQRR_ITHRESH 12 39 #define QMAN_PIRQ_MR_ITHRESH 4 40 #define QMAN_PIRQ_IPERIOD 100 41 42 /* Portal register assists */ 43 44 /* Cache-inhibited register offsets */ 45 #define QM_REG_EQCR_PI_CINH 0x0000 46 #define QM_REG_EQCR_CI_CINH 0x0004 47 #define QM_REG_EQCR_ITR 0x0008 48 #define QM_REG_DQRR_PI_CINH 0x0040 49 #define QM_REG_DQRR_CI_CINH 0x0044 50 #define QM_REG_DQRR_ITR 0x0048 51 #define QM_REG_DQRR_DCAP 0x0050 52 #define QM_REG_DQRR_SDQCR 0x0054 53 #define QM_REG_DQRR_VDQCR 0x0058 54 #define QM_REG_DQRR_PDQCR 0x005c 55 #define QM_REG_MR_PI_CINH 0x0080 56 #define QM_REG_MR_CI_CINH 0x0084 57 #define QM_REG_MR_ITR 0x0088 58 #define QM_REG_CFG 0x0100 59 #define QM_REG_ISR 0x0e00 60 #define QM_REG_IER 0x0e04 61 #define QM_REG_ISDR 0x0e08 62 #define QM_REG_IIR 0x0e0c 63 #define QM_REG_ITPR 0x0e14 64 65 /* Cache-enabled register offsets */ 66 #define QM_CL_EQCR 0x0000 67 #define QM_CL_DQRR 0x1000 68 #define QM_CL_MR 0x2000 69 #define QM_CL_EQCR_PI_CENA 0x3000 70 #define QM_CL_EQCR_CI_CENA 0x3100 71 #define QM_CL_DQRR_PI_CENA 0x3200 72 #define QM_CL_DQRR_CI_CENA 0x3300 73 #define QM_CL_MR_PI_CENA 0x3400 74 #define QM_CL_MR_CI_CENA 0x3500 75 #define QM_CL_CR 0x3800 76 #define QM_CL_RR0 0x3900 77 #define QM_CL_RR1 0x3940 78 79 /* 80 * BTW, the drivers (and h/w programming model) already obtain the required 81 * synchronisation for portal accesses and data-dependencies. Use of barrier()s 82 * or other order-preserving primitives simply degrade performance. Hence the 83 * use of the __raw_*() interfaces, which simply ensure that the compiler treats 84 * the portal registers as volatile 85 */ 86 87 /* Cache-enabled ring access */ 88 #define qm_cl(base, idx) ((void *)base + ((idx) << 6)) 89 90 /* 91 * Portal modes. 92 * Enum types; 93 * pmode == production mode 94 * cmode == consumption mode, 95 * dmode == h/w dequeue mode. 96 * Enum values use 3 letter codes. First letter matches the portal mode, 97 * remaining two letters indicate; 98 * ci == cache-inhibited portal register 99 * ce == cache-enabled portal register 100 * vb == in-band valid-bit (cache-enabled) 101 * dc == DCA (Discrete Consumption Acknowledgment), DQRR-only 102 * As for "enum qm_dqrr_dmode", it should be self-explanatory. 103 */ 104 enum qm_eqcr_pmode { /* matches QCSP_CFG::EPM */ 105 qm_eqcr_pci = 0, /* PI index, cache-inhibited */ 106 qm_eqcr_pce = 1, /* PI index, cache-enabled */ 107 qm_eqcr_pvb = 2 /* valid-bit */ 108 }; 109 enum qm_dqrr_dmode { /* matches QCSP_CFG::DP */ 110 qm_dqrr_dpush = 0, /* SDQCR + VDQCR */ 111 qm_dqrr_dpull = 1 /* PDQCR */ 112 }; 113 enum qm_dqrr_pmode { /* s/w-only */ 114 qm_dqrr_pci, /* reads DQRR_PI_CINH */ 115 qm_dqrr_pce, /* reads DQRR_PI_CENA */ 116 qm_dqrr_pvb /* reads valid-bit */ 117 }; 118 enum qm_dqrr_cmode { /* matches QCSP_CFG::DCM */ 119 qm_dqrr_cci = 0, /* CI index, cache-inhibited */ 120 qm_dqrr_cce = 1, /* CI index, cache-enabled */ 121 qm_dqrr_cdc = 2 /* Discrete Consumption Acknowledgment */ 122 }; 123 enum qm_mr_pmode { /* s/w-only */ 124 qm_mr_pci, /* reads MR_PI_CINH */ 125 qm_mr_pce, /* reads MR_PI_CENA */ 126 qm_mr_pvb /* reads valid-bit */ 127 }; 128 enum qm_mr_cmode { /* matches QCSP_CFG::MM */ 129 qm_mr_cci = 0, /* CI index, cache-inhibited */ 130 qm_mr_cce = 1 /* CI index, cache-enabled */ 131 }; 132 133 /* --- Portal structures --- */ 134 135 #define QM_EQCR_SIZE 8 136 #define QM_DQRR_SIZE 16 137 #define QM_MR_SIZE 8 138 139 /* "Enqueue Command" */ 140 struct qm_eqcr_entry { 141 u8 _ncw_verb; /* writes to this are non-coherent */ 142 u8 dca; 143 __be16 seqnum; 144 u8 __reserved[4]; 145 __be32 fqid; /* 24-bit */ 146 __be32 tag; 147 struct qm_fd fd; 148 u8 __reserved3[32]; 149 } __packed; 150 #define QM_EQCR_VERB_VBIT 0x80 151 #define QM_EQCR_VERB_CMD_MASK 0x61 /* but only one value; */ 152 #define QM_EQCR_VERB_CMD_ENQUEUE 0x01 153 #define QM_EQCR_SEQNUM_NESN 0x8000 /* Advance NESN */ 154 #define QM_EQCR_SEQNUM_NLIS 0x4000 /* More fragments to come */ 155 #define QM_EQCR_SEQNUM_SEQMASK 0x3fff /* sequence number goes here */ 156 157 struct qm_eqcr { 158 struct qm_eqcr_entry *ring, *cursor; 159 u8 ci, available, ithresh, vbit; 160 #ifdef CONFIG_FSL_DPAA_CHECKING 161 u32 busy; 162 enum qm_eqcr_pmode pmode; 163 #endif 164 }; 165 166 struct qm_dqrr { 167 const struct qm_dqrr_entry *ring, *cursor; 168 u8 pi, ci, fill, ithresh, vbit; 169 #ifdef CONFIG_FSL_DPAA_CHECKING 170 enum qm_dqrr_dmode dmode; 171 enum qm_dqrr_pmode pmode; 172 enum qm_dqrr_cmode cmode; 173 #endif 174 }; 175 176 struct qm_mr { 177 union qm_mr_entry *ring, *cursor; 178 u8 pi, ci, fill, ithresh, vbit; 179 #ifdef CONFIG_FSL_DPAA_CHECKING 180 enum qm_mr_pmode pmode; 181 enum qm_mr_cmode cmode; 182 #endif 183 }; 184 185 /* MC (Management Command) command */ 186 /* "FQ" command layout */ 187 struct qm_mcc_fq { 188 u8 _ncw_verb; 189 u8 __reserved1[3]; 190 __be32 fqid; /* 24-bit */ 191 u8 __reserved2[56]; 192 } __packed; 193 194 /* "CGR" command layout */ 195 struct qm_mcc_cgr { 196 u8 _ncw_verb; 197 u8 __reserved1[30]; 198 u8 cgid; 199 u8 __reserved2[32]; 200 }; 201 202 #define QM_MCC_VERB_VBIT 0x80 203 #define QM_MCC_VERB_MASK 0x7f /* where the verb contains; */ 204 #define QM_MCC_VERB_INITFQ_PARKED 0x40 205 #define QM_MCC_VERB_INITFQ_SCHED 0x41 206 #define QM_MCC_VERB_QUERYFQ 0x44 207 #define QM_MCC_VERB_QUERYFQ_NP 0x45 /* "non-programmable" fields */ 208 #define QM_MCC_VERB_QUERYWQ 0x46 209 #define QM_MCC_VERB_QUERYWQ_DEDICATED 0x47 210 #define QM_MCC_VERB_ALTER_SCHED 0x48 /* Schedule FQ */ 211 #define QM_MCC_VERB_ALTER_FE 0x49 /* Force Eligible FQ */ 212 #define QM_MCC_VERB_ALTER_RETIRE 0x4a /* Retire FQ */ 213 #define QM_MCC_VERB_ALTER_OOS 0x4b /* Take FQ out of service */ 214 #define QM_MCC_VERB_ALTER_FQXON 0x4d /* FQ XON */ 215 #define QM_MCC_VERB_ALTER_FQXOFF 0x4e /* FQ XOFF */ 216 #define QM_MCC_VERB_INITCGR 0x50 217 #define QM_MCC_VERB_MODIFYCGR 0x51 218 #define QM_MCC_VERB_CGRTESTWRITE 0x52 219 #define QM_MCC_VERB_QUERYCGR 0x58 220 #define QM_MCC_VERB_QUERYCONGESTION 0x59 221 union qm_mc_command { 222 struct { 223 u8 _ncw_verb; /* writes to this are non-coherent */ 224 u8 __reserved[63]; 225 }; 226 struct qm_mcc_initfq initfq; 227 struct qm_mcc_initcgr initcgr; 228 struct qm_mcc_fq fq; 229 struct qm_mcc_cgr cgr; 230 }; 231 232 /* MC (Management Command) result */ 233 /* "Query FQ" */ 234 struct qm_mcr_queryfq { 235 u8 verb; 236 u8 result; 237 u8 __reserved1[8]; 238 struct qm_fqd fqd; /* the FQD fields are here */ 239 u8 __reserved2[30]; 240 } __packed; 241 242 /* "Alter FQ State Commands" */ 243 struct qm_mcr_alterfq { 244 u8 verb; 245 u8 result; 246 u8 fqs; /* Frame Queue Status */ 247 u8 __reserved1[61]; 248 }; 249 #define QM_MCR_VERB_RRID 0x80 250 #define QM_MCR_VERB_MASK QM_MCC_VERB_MASK 251 #define QM_MCR_VERB_INITFQ_PARKED QM_MCC_VERB_INITFQ_PARKED 252 #define QM_MCR_VERB_INITFQ_SCHED QM_MCC_VERB_INITFQ_SCHED 253 #define QM_MCR_VERB_QUERYFQ QM_MCC_VERB_QUERYFQ 254 #define QM_MCR_VERB_QUERYFQ_NP QM_MCC_VERB_QUERYFQ_NP 255 #define QM_MCR_VERB_QUERYWQ QM_MCC_VERB_QUERYWQ 256 #define QM_MCR_VERB_QUERYWQ_DEDICATED QM_MCC_VERB_QUERYWQ_DEDICATED 257 #define QM_MCR_VERB_ALTER_SCHED QM_MCC_VERB_ALTER_SCHED 258 #define QM_MCR_VERB_ALTER_FE QM_MCC_VERB_ALTER_FE 259 #define QM_MCR_VERB_ALTER_RETIRE QM_MCC_VERB_ALTER_RETIRE 260 #define QM_MCR_VERB_ALTER_OOS QM_MCC_VERB_ALTER_OOS 261 #define QM_MCR_RESULT_NULL 0x00 262 #define QM_MCR_RESULT_OK 0xf0 263 #define QM_MCR_RESULT_ERR_FQID 0xf1 264 #define QM_MCR_RESULT_ERR_FQSTATE 0xf2 265 #define QM_MCR_RESULT_ERR_NOTEMPTY 0xf3 /* OOS fails if FQ is !empty */ 266 #define QM_MCR_RESULT_ERR_BADCHANNEL 0xf4 267 #define QM_MCR_RESULT_PENDING 0xf8 268 #define QM_MCR_RESULT_ERR_BADCOMMAND 0xff 269 #define QM_MCR_FQS_ORLPRESENT 0x02 /* ORL fragments to come */ 270 #define QM_MCR_FQS_NOTEMPTY 0x01 /* FQ has enqueued frames */ 271 #define QM_MCR_TIMEOUT 10000 /* us */ 272 union qm_mc_result { 273 struct { 274 u8 verb; 275 u8 result; 276 u8 __reserved1[62]; 277 }; 278 struct qm_mcr_queryfq queryfq; 279 struct qm_mcr_alterfq alterfq; 280 struct qm_mcr_querycgr querycgr; 281 struct qm_mcr_querycongestion querycongestion; 282 struct qm_mcr_querywq querywq; 283 struct qm_mcr_queryfq_np queryfq_np; 284 }; 285 286 struct qm_mc { 287 union qm_mc_command *cr; 288 union qm_mc_result *rr; 289 u8 rridx, vbit; 290 #ifdef CONFIG_FSL_DPAA_CHECKING 291 enum { 292 /* Can be _mc_start()ed */ 293 qman_mc_idle, 294 /* Can be _mc_commit()ed or _mc_abort()ed */ 295 qman_mc_user, 296 /* Can only be _mc_retry()ed */ 297 qman_mc_hw 298 } state; 299 #endif 300 }; 301 302 struct qm_addr { 303 void __iomem *ce; /* cache-enabled */ 304 void __iomem *ci; /* cache-inhibited */ 305 }; 306 307 struct qm_portal { 308 /* 309 * In the non-CONFIG_FSL_DPAA_CHECKING case, the following stuff up to 310 * and including 'mc' fits within a cacheline (yay!). The 'config' part 311 * is setup-only, so isn't a cause for a concern. In other words, don't 312 * rearrange this structure on a whim, there be dragons ... 313 */ 314 struct qm_addr addr; 315 struct qm_eqcr eqcr; 316 struct qm_dqrr dqrr; 317 struct qm_mr mr; 318 struct qm_mc mc; 319 } ____cacheline_aligned; 320 321 /* Cache-inhibited register access. */ 322 static inline u32 qm_in(struct qm_portal *p, u32 offset) 323 { 324 return be32_to_cpu(__raw_readl(p->addr.ci + offset)); 325 } 326 327 static inline void qm_out(struct qm_portal *p, u32 offset, u32 val) 328 { 329 __raw_writel(cpu_to_be32(val), p->addr.ci + offset); 330 } 331 332 /* Cache Enabled Portal Access */ 333 static inline void qm_cl_invalidate(struct qm_portal *p, u32 offset) 334 { 335 dpaa_invalidate(p->addr.ce + offset); 336 } 337 338 static inline void qm_cl_touch_ro(struct qm_portal *p, u32 offset) 339 { 340 dpaa_touch_ro(p->addr.ce + offset); 341 } 342 343 static inline u32 qm_ce_in(struct qm_portal *p, u32 offset) 344 { 345 return be32_to_cpu(__raw_readl(p->addr.ce + offset)); 346 } 347 348 /* --- EQCR API --- */ 349 350 #define EQCR_SHIFT ilog2(sizeof(struct qm_eqcr_entry)) 351 #define EQCR_CARRY (uintptr_t)(QM_EQCR_SIZE << EQCR_SHIFT) 352 353 /* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */ 354 static struct qm_eqcr_entry *eqcr_carryclear(struct qm_eqcr_entry *p) 355 { 356 uintptr_t addr = (uintptr_t)p; 357 358 addr &= ~EQCR_CARRY; 359 360 return (struct qm_eqcr_entry *)addr; 361 } 362 363 /* Bit-wise logic to convert a ring pointer to a ring index */ 364 static int eqcr_ptr2idx(struct qm_eqcr_entry *e) 365 { 366 return ((uintptr_t)e >> EQCR_SHIFT) & (QM_EQCR_SIZE - 1); 367 } 368 369 /* Increment the 'cursor' ring pointer, taking 'vbit' into account */ 370 static inline void eqcr_inc(struct qm_eqcr *eqcr) 371 { 372 /* increment to the next EQCR pointer and handle overflow and 'vbit' */ 373 struct qm_eqcr_entry *partial = eqcr->cursor + 1; 374 375 eqcr->cursor = eqcr_carryclear(partial); 376 if (partial != eqcr->cursor) 377 eqcr->vbit ^= QM_EQCR_VERB_VBIT; 378 } 379 380 static inline int qm_eqcr_init(struct qm_portal *portal, 381 enum qm_eqcr_pmode pmode, 382 unsigned int eq_stash_thresh, 383 int eq_stash_prio) 384 { 385 struct qm_eqcr *eqcr = &portal->eqcr; 386 u32 cfg; 387 u8 pi; 388 389 eqcr->ring = portal->addr.ce + QM_CL_EQCR; 390 eqcr->ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1); 391 qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA); 392 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1); 393 eqcr->cursor = eqcr->ring + pi; 394 eqcr->vbit = (qm_in(portal, QM_REG_EQCR_PI_CINH) & QM_EQCR_SIZE) ? 395 QM_EQCR_VERB_VBIT : 0; 396 eqcr->available = QM_EQCR_SIZE - 1 - 397 dpaa_cyc_diff(QM_EQCR_SIZE, eqcr->ci, pi); 398 eqcr->ithresh = qm_in(portal, QM_REG_EQCR_ITR); 399 #ifdef CONFIG_FSL_DPAA_CHECKING 400 eqcr->busy = 0; 401 eqcr->pmode = pmode; 402 #endif 403 cfg = (qm_in(portal, QM_REG_CFG) & 0x00ffffff) | 404 (eq_stash_thresh << 28) | /* QCSP_CFG: EST */ 405 (eq_stash_prio << 26) | /* QCSP_CFG: EP */ 406 ((pmode & 0x3) << 24); /* QCSP_CFG::EPM */ 407 qm_out(portal, QM_REG_CFG, cfg); 408 return 0; 409 } 410 411 static inline unsigned int qm_eqcr_get_ci_stashing(struct qm_portal *portal) 412 { 413 return (qm_in(portal, QM_REG_CFG) >> 28) & 0x7; 414 } 415 416 static inline void qm_eqcr_finish(struct qm_portal *portal) 417 { 418 struct qm_eqcr *eqcr = &portal->eqcr; 419 u8 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1); 420 u8 ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1); 421 422 DPAA_ASSERT(!eqcr->busy); 423 if (pi != eqcr_ptr2idx(eqcr->cursor)) 424 pr_crit("losing uncommitted EQCR entries\n"); 425 if (ci != eqcr->ci) 426 pr_crit("missing existing EQCR completions\n"); 427 if (eqcr->ci != eqcr_ptr2idx(eqcr->cursor)) 428 pr_crit("EQCR destroyed unquiesced\n"); 429 } 430 431 static inline struct qm_eqcr_entry *qm_eqcr_start_no_stash(struct qm_portal 432 *portal) 433 { 434 struct qm_eqcr *eqcr = &portal->eqcr; 435 436 DPAA_ASSERT(!eqcr->busy); 437 if (!eqcr->available) 438 return NULL; 439 440 #ifdef CONFIG_FSL_DPAA_CHECKING 441 eqcr->busy = 1; 442 #endif 443 dpaa_zero(eqcr->cursor); 444 return eqcr->cursor; 445 } 446 447 static inline struct qm_eqcr_entry *qm_eqcr_start_stash(struct qm_portal 448 *portal) 449 { 450 struct qm_eqcr *eqcr = &portal->eqcr; 451 u8 diff, old_ci; 452 453 DPAA_ASSERT(!eqcr->busy); 454 if (!eqcr->available) { 455 old_ci = eqcr->ci; 456 eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) & 457 (QM_EQCR_SIZE - 1); 458 diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci); 459 eqcr->available += diff; 460 if (!diff) 461 return NULL; 462 } 463 #ifdef CONFIG_FSL_DPAA_CHECKING 464 eqcr->busy = 1; 465 #endif 466 dpaa_zero(eqcr->cursor); 467 return eqcr->cursor; 468 } 469 470 static inline void eqcr_commit_checks(struct qm_eqcr *eqcr) 471 { 472 DPAA_ASSERT(eqcr->busy); 473 DPAA_ASSERT(!(be32_to_cpu(eqcr->cursor->fqid) & ~QM_FQID_MASK)); 474 DPAA_ASSERT(eqcr->available >= 1); 475 } 476 477 static inline void qm_eqcr_pvb_commit(struct qm_portal *portal, u8 myverb) 478 { 479 struct qm_eqcr *eqcr = &portal->eqcr; 480 struct qm_eqcr_entry *eqcursor; 481 482 eqcr_commit_checks(eqcr); 483 DPAA_ASSERT(eqcr->pmode == qm_eqcr_pvb); 484 dma_wmb(); 485 eqcursor = eqcr->cursor; 486 eqcursor->_ncw_verb = myverb | eqcr->vbit; 487 dpaa_flush(eqcursor); 488 eqcr_inc(eqcr); 489 eqcr->available--; 490 #ifdef CONFIG_FSL_DPAA_CHECKING 491 eqcr->busy = 0; 492 #endif 493 } 494 495 static inline void qm_eqcr_cce_prefetch(struct qm_portal *portal) 496 { 497 qm_cl_touch_ro(portal, QM_CL_EQCR_CI_CENA); 498 } 499 500 static inline u8 qm_eqcr_cce_update(struct qm_portal *portal) 501 { 502 struct qm_eqcr *eqcr = &portal->eqcr; 503 u8 diff, old_ci = eqcr->ci; 504 505 eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) & (QM_EQCR_SIZE - 1); 506 qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA); 507 diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci); 508 eqcr->available += diff; 509 return diff; 510 } 511 512 static inline void qm_eqcr_set_ithresh(struct qm_portal *portal, u8 ithresh) 513 { 514 struct qm_eqcr *eqcr = &portal->eqcr; 515 516 eqcr->ithresh = ithresh; 517 qm_out(portal, QM_REG_EQCR_ITR, ithresh); 518 } 519 520 static inline u8 qm_eqcr_get_avail(struct qm_portal *portal) 521 { 522 struct qm_eqcr *eqcr = &portal->eqcr; 523 524 return eqcr->available; 525 } 526 527 static inline u8 qm_eqcr_get_fill(struct qm_portal *portal) 528 { 529 struct qm_eqcr *eqcr = &portal->eqcr; 530 531 return QM_EQCR_SIZE - 1 - eqcr->available; 532 } 533 534 /* --- DQRR API --- */ 535 536 #define DQRR_SHIFT ilog2(sizeof(struct qm_dqrr_entry)) 537 #define DQRR_CARRY (uintptr_t)(QM_DQRR_SIZE << DQRR_SHIFT) 538 539 static const struct qm_dqrr_entry *dqrr_carryclear( 540 const struct qm_dqrr_entry *p) 541 { 542 uintptr_t addr = (uintptr_t)p; 543 544 addr &= ~DQRR_CARRY; 545 546 return (const struct qm_dqrr_entry *)addr; 547 } 548 549 static inline int dqrr_ptr2idx(const struct qm_dqrr_entry *e) 550 { 551 return ((uintptr_t)e >> DQRR_SHIFT) & (QM_DQRR_SIZE - 1); 552 } 553 554 static const struct qm_dqrr_entry *dqrr_inc(const struct qm_dqrr_entry *e) 555 { 556 return dqrr_carryclear(e + 1); 557 } 558 559 static inline void qm_dqrr_set_maxfill(struct qm_portal *portal, u8 mf) 560 { 561 qm_out(portal, QM_REG_CFG, (qm_in(portal, QM_REG_CFG) & 0xff0fffff) | 562 ((mf & (QM_DQRR_SIZE - 1)) << 20)); 563 } 564 565 static inline int qm_dqrr_init(struct qm_portal *portal, 566 const struct qm_portal_config *config, 567 enum qm_dqrr_dmode dmode, 568 enum qm_dqrr_pmode pmode, 569 enum qm_dqrr_cmode cmode, u8 max_fill) 570 { 571 struct qm_dqrr *dqrr = &portal->dqrr; 572 u32 cfg; 573 574 /* Make sure the DQRR will be idle when we enable */ 575 qm_out(portal, QM_REG_DQRR_SDQCR, 0); 576 qm_out(portal, QM_REG_DQRR_VDQCR, 0); 577 qm_out(portal, QM_REG_DQRR_PDQCR, 0); 578 dqrr->ring = portal->addr.ce + QM_CL_DQRR; 579 dqrr->pi = qm_in(portal, QM_REG_DQRR_PI_CINH) & (QM_DQRR_SIZE - 1); 580 dqrr->ci = qm_in(portal, QM_REG_DQRR_CI_CINH) & (QM_DQRR_SIZE - 1); 581 dqrr->cursor = dqrr->ring + dqrr->ci; 582 dqrr->fill = dpaa_cyc_diff(QM_DQRR_SIZE, dqrr->ci, dqrr->pi); 583 dqrr->vbit = (qm_in(portal, QM_REG_DQRR_PI_CINH) & QM_DQRR_SIZE) ? 584 QM_DQRR_VERB_VBIT : 0; 585 dqrr->ithresh = qm_in(portal, QM_REG_DQRR_ITR); 586 #ifdef CONFIG_FSL_DPAA_CHECKING 587 dqrr->dmode = dmode; 588 dqrr->pmode = pmode; 589 dqrr->cmode = cmode; 590 #endif 591 /* Invalidate every ring entry before beginning */ 592 for (cfg = 0; cfg < QM_DQRR_SIZE; cfg++) 593 dpaa_invalidate(qm_cl(dqrr->ring, cfg)); 594 cfg = (qm_in(portal, QM_REG_CFG) & 0xff000f00) | 595 ((max_fill & (QM_DQRR_SIZE - 1)) << 20) | /* DQRR_MF */ 596 ((dmode & 1) << 18) | /* DP */ 597 ((cmode & 3) << 16) | /* DCM */ 598 0xa0 | /* RE+SE */ 599 (0 ? 0x40 : 0) | /* Ignore RP */ 600 (0 ? 0x10 : 0); /* Ignore SP */ 601 qm_out(portal, QM_REG_CFG, cfg); 602 qm_dqrr_set_maxfill(portal, max_fill); 603 return 0; 604 } 605 606 static inline void qm_dqrr_finish(struct qm_portal *portal) 607 { 608 #ifdef CONFIG_FSL_DPAA_CHECKING 609 struct qm_dqrr *dqrr = &portal->dqrr; 610 611 if (dqrr->cmode != qm_dqrr_cdc && 612 dqrr->ci != dqrr_ptr2idx(dqrr->cursor)) 613 pr_crit("Ignoring completed DQRR entries\n"); 614 #endif 615 } 616 617 static inline const struct qm_dqrr_entry *qm_dqrr_current( 618 struct qm_portal *portal) 619 { 620 struct qm_dqrr *dqrr = &portal->dqrr; 621 622 if (!dqrr->fill) 623 return NULL; 624 return dqrr->cursor; 625 } 626 627 static inline u8 qm_dqrr_next(struct qm_portal *portal) 628 { 629 struct qm_dqrr *dqrr = &portal->dqrr; 630 631 DPAA_ASSERT(dqrr->fill); 632 dqrr->cursor = dqrr_inc(dqrr->cursor); 633 return --dqrr->fill; 634 } 635 636 static inline void qm_dqrr_pvb_update(struct qm_portal *portal) 637 { 638 struct qm_dqrr *dqrr = &portal->dqrr; 639 struct qm_dqrr_entry *res = qm_cl(dqrr->ring, dqrr->pi); 640 641 DPAA_ASSERT(dqrr->pmode == qm_dqrr_pvb); 642 #ifndef CONFIG_FSL_PAMU 643 /* 644 * If PAMU is not available we need to invalidate the cache. 645 * When PAMU is available the cache is updated by stash 646 */ 647 dpaa_invalidate_touch_ro(res); 648 #endif 649 /* 650 * when accessing 'verb', use __raw_readb() to ensure that compiler 651 * inlining doesn't try to optimise out "excess reads". 652 */ 653 if ((__raw_readb(&res->verb) & QM_DQRR_VERB_VBIT) == dqrr->vbit) { 654 dqrr->pi = (dqrr->pi + 1) & (QM_DQRR_SIZE - 1); 655 if (!dqrr->pi) 656 dqrr->vbit ^= QM_DQRR_VERB_VBIT; 657 dqrr->fill++; 658 } 659 } 660 661 static inline void qm_dqrr_cdc_consume_1ptr(struct qm_portal *portal, 662 const struct qm_dqrr_entry *dq, 663 int park) 664 { 665 __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr; 666 int idx = dqrr_ptr2idx(dq); 667 668 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc); 669 DPAA_ASSERT((dqrr->ring + idx) == dq); 670 DPAA_ASSERT(idx < QM_DQRR_SIZE); 671 qm_out(portal, QM_REG_DQRR_DCAP, (0 << 8) | /* DQRR_DCAP::S */ 672 ((park ? 1 : 0) << 6) | /* DQRR_DCAP::PK */ 673 idx); /* DQRR_DCAP::DCAP_CI */ 674 } 675 676 static inline void qm_dqrr_cdc_consume_n(struct qm_portal *portal, u32 bitmask) 677 { 678 __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr; 679 680 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc); 681 qm_out(portal, QM_REG_DQRR_DCAP, (1 << 8) | /* DQRR_DCAP::S */ 682 (bitmask << 16)); /* DQRR_DCAP::DCAP_CI */ 683 } 684 685 static inline void qm_dqrr_sdqcr_set(struct qm_portal *portal, u32 sdqcr) 686 { 687 qm_out(portal, QM_REG_DQRR_SDQCR, sdqcr); 688 } 689 690 static inline void qm_dqrr_vdqcr_set(struct qm_portal *portal, u32 vdqcr) 691 { 692 qm_out(portal, QM_REG_DQRR_VDQCR, vdqcr); 693 } 694 695 static inline void qm_dqrr_set_ithresh(struct qm_portal *portal, u8 ithresh) 696 { 697 qm_out(portal, QM_REG_DQRR_ITR, ithresh); 698 } 699 700 /* --- MR API --- */ 701 702 #define MR_SHIFT ilog2(sizeof(union qm_mr_entry)) 703 #define MR_CARRY (uintptr_t)(QM_MR_SIZE << MR_SHIFT) 704 705 static union qm_mr_entry *mr_carryclear(union qm_mr_entry *p) 706 { 707 uintptr_t addr = (uintptr_t)p; 708 709 addr &= ~MR_CARRY; 710 711 return (union qm_mr_entry *)addr; 712 } 713 714 static inline int mr_ptr2idx(const union qm_mr_entry *e) 715 { 716 return ((uintptr_t)e >> MR_SHIFT) & (QM_MR_SIZE - 1); 717 } 718 719 static inline union qm_mr_entry *mr_inc(union qm_mr_entry *e) 720 { 721 return mr_carryclear(e + 1); 722 } 723 724 static inline int qm_mr_init(struct qm_portal *portal, enum qm_mr_pmode pmode, 725 enum qm_mr_cmode cmode) 726 { 727 struct qm_mr *mr = &portal->mr; 728 u32 cfg; 729 730 mr->ring = portal->addr.ce + QM_CL_MR; 731 mr->pi = qm_in(portal, QM_REG_MR_PI_CINH) & (QM_MR_SIZE - 1); 732 mr->ci = qm_in(portal, QM_REG_MR_CI_CINH) & (QM_MR_SIZE - 1); 733 mr->cursor = mr->ring + mr->ci; 734 mr->fill = dpaa_cyc_diff(QM_MR_SIZE, mr->ci, mr->pi); 735 mr->vbit = (qm_in(portal, QM_REG_MR_PI_CINH) & QM_MR_SIZE) 736 ? QM_MR_VERB_VBIT : 0; 737 mr->ithresh = qm_in(portal, QM_REG_MR_ITR); 738 #ifdef CONFIG_FSL_DPAA_CHECKING 739 mr->pmode = pmode; 740 mr->cmode = cmode; 741 #endif 742 cfg = (qm_in(portal, QM_REG_CFG) & 0xfffff0ff) | 743 ((cmode & 1) << 8); /* QCSP_CFG:MM */ 744 qm_out(portal, QM_REG_CFG, cfg); 745 return 0; 746 } 747 748 static inline void qm_mr_finish(struct qm_portal *portal) 749 { 750 struct qm_mr *mr = &portal->mr; 751 752 if (mr->ci != mr_ptr2idx(mr->cursor)) 753 pr_crit("Ignoring completed MR entries\n"); 754 } 755 756 static inline const union qm_mr_entry *qm_mr_current(struct qm_portal *portal) 757 { 758 struct qm_mr *mr = &portal->mr; 759 760 if (!mr->fill) 761 return NULL; 762 return mr->cursor; 763 } 764 765 static inline int qm_mr_next(struct qm_portal *portal) 766 { 767 struct qm_mr *mr = &portal->mr; 768 769 DPAA_ASSERT(mr->fill); 770 mr->cursor = mr_inc(mr->cursor); 771 return --mr->fill; 772 } 773 774 static inline void qm_mr_pvb_update(struct qm_portal *portal) 775 { 776 struct qm_mr *mr = &portal->mr; 777 union qm_mr_entry *res = qm_cl(mr->ring, mr->pi); 778 779 DPAA_ASSERT(mr->pmode == qm_mr_pvb); 780 /* 781 * when accessing 'verb', use __raw_readb() to ensure that compiler 782 * inlining doesn't try to optimise out "excess reads". 783 */ 784 if ((__raw_readb(&res->verb) & QM_MR_VERB_VBIT) == mr->vbit) { 785 mr->pi = (mr->pi + 1) & (QM_MR_SIZE - 1); 786 if (!mr->pi) 787 mr->vbit ^= QM_MR_VERB_VBIT; 788 mr->fill++; 789 res = mr_inc(res); 790 } 791 dpaa_invalidate_touch_ro(res); 792 } 793 794 static inline void qm_mr_cci_consume(struct qm_portal *portal, u8 num) 795 { 796 struct qm_mr *mr = &portal->mr; 797 798 DPAA_ASSERT(mr->cmode == qm_mr_cci); 799 mr->ci = (mr->ci + num) & (QM_MR_SIZE - 1); 800 qm_out(portal, QM_REG_MR_CI_CINH, mr->ci); 801 } 802 803 static inline void qm_mr_cci_consume_to_current(struct qm_portal *portal) 804 { 805 struct qm_mr *mr = &portal->mr; 806 807 DPAA_ASSERT(mr->cmode == qm_mr_cci); 808 mr->ci = mr_ptr2idx(mr->cursor); 809 qm_out(portal, QM_REG_MR_CI_CINH, mr->ci); 810 } 811 812 static inline void qm_mr_set_ithresh(struct qm_portal *portal, u8 ithresh) 813 { 814 qm_out(portal, QM_REG_MR_ITR, ithresh); 815 } 816 817 /* --- Management command API --- */ 818 819 static inline int qm_mc_init(struct qm_portal *portal) 820 { 821 struct qm_mc *mc = &portal->mc; 822 823 mc->cr = portal->addr.ce + QM_CL_CR; 824 mc->rr = portal->addr.ce + QM_CL_RR0; 825 mc->rridx = (__raw_readb(&mc->cr->_ncw_verb) & QM_MCC_VERB_VBIT) 826 ? 0 : 1; 827 mc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0; 828 #ifdef CONFIG_FSL_DPAA_CHECKING 829 mc->state = qman_mc_idle; 830 #endif 831 return 0; 832 } 833 834 static inline void qm_mc_finish(struct qm_portal *portal) 835 { 836 #ifdef CONFIG_FSL_DPAA_CHECKING 837 struct qm_mc *mc = &portal->mc; 838 839 DPAA_ASSERT(mc->state == qman_mc_idle); 840 if (mc->state != qman_mc_idle) 841 pr_crit("Losing incomplete MC command\n"); 842 #endif 843 } 844 845 static inline union qm_mc_command *qm_mc_start(struct qm_portal *portal) 846 { 847 struct qm_mc *mc = &portal->mc; 848 849 DPAA_ASSERT(mc->state == qman_mc_idle); 850 #ifdef CONFIG_FSL_DPAA_CHECKING 851 mc->state = qman_mc_user; 852 #endif 853 dpaa_zero(mc->cr); 854 return mc->cr; 855 } 856 857 static inline void qm_mc_commit(struct qm_portal *portal, u8 myverb) 858 { 859 struct qm_mc *mc = &portal->mc; 860 union qm_mc_result *rr = mc->rr + mc->rridx; 861 862 DPAA_ASSERT(mc->state == qman_mc_user); 863 dma_wmb(); 864 mc->cr->_ncw_verb = myverb | mc->vbit; 865 dpaa_flush(mc->cr); 866 dpaa_invalidate_touch_ro(rr); 867 #ifdef CONFIG_FSL_DPAA_CHECKING 868 mc->state = qman_mc_hw; 869 #endif 870 } 871 872 static inline union qm_mc_result *qm_mc_result(struct qm_portal *portal) 873 { 874 struct qm_mc *mc = &portal->mc; 875 union qm_mc_result *rr = mc->rr + mc->rridx; 876 877 DPAA_ASSERT(mc->state == qman_mc_hw); 878 /* 879 * The inactive response register's verb byte always returns zero until 880 * its command is submitted and completed. This includes the valid-bit, 881 * in case you were wondering... 882 */ 883 if (!__raw_readb(&rr->verb)) { 884 dpaa_invalidate_touch_ro(rr); 885 return NULL; 886 } 887 mc->rridx ^= 1; 888 mc->vbit ^= QM_MCC_VERB_VBIT; 889 #ifdef CONFIG_FSL_DPAA_CHECKING 890 mc->state = qman_mc_idle; 891 #endif 892 return rr; 893 } 894 895 static inline int qm_mc_result_timeout(struct qm_portal *portal, 896 union qm_mc_result **mcr) 897 { 898 int timeout = QM_MCR_TIMEOUT; 899 900 do { 901 *mcr = qm_mc_result(portal); 902 if (*mcr) 903 break; 904 udelay(1); 905 } while (--timeout); 906 907 return timeout; 908 } 909 910 static inline void fq_set(struct qman_fq *fq, u32 mask) 911 { 912 set_bits(mask, &fq->flags); 913 } 914 915 static inline void fq_clear(struct qman_fq *fq, u32 mask) 916 { 917 clear_bits(mask, &fq->flags); 918 } 919 920 static inline int fq_isset(struct qman_fq *fq, u32 mask) 921 { 922 return fq->flags & mask; 923 } 924 925 static inline int fq_isclear(struct qman_fq *fq, u32 mask) 926 { 927 return !(fq->flags & mask); 928 } 929 930 struct qman_portal { 931 struct qm_portal p; 932 /* PORTAL_BITS_*** - dynamic, strictly internal */ 933 unsigned long bits; 934 /* interrupt sources processed by portal_isr(), configurable */ 935 unsigned long irq_sources; 936 u32 use_eqcr_ci_stashing; 937 /* only 1 volatile dequeue at a time */ 938 struct qman_fq *vdqcr_owned; 939 u32 sdqcr; 940 /* probing time config params for cpu-affine portals */ 941 const struct qm_portal_config *config; 942 /* 2-element array. cgrs[0] is mask, cgrs[1] is snapshot. */ 943 struct qman_cgrs *cgrs; 944 /* linked-list of CSCN handlers. */ 945 struct list_head cgr_cbs; 946 /* list lock */ 947 spinlock_t cgr_lock; 948 struct work_struct congestion_work; 949 struct work_struct mr_work; 950 char irqname[MAX_IRQNAME]; 951 }; 952 953 static cpumask_t affine_mask; 954 static DEFINE_SPINLOCK(affine_mask_lock); 955 static u16 affine_channels[NR_CPUS]; 956 static DEFINE_PER_CPU(struct qman_portal, qman_affine_portal); 957 struct qman_portal *affine_portals[NR_CPUS]; 958 959 static inline struct qman_portal *get_affine_portal(void) 960 { 961 return &get_cpu_var(qman_affine_portal); 962 } 963 964 static inline void put_affine_portal(void) 965 { 966 put_cpu_var(qman_affine_portal); 967 } 968 969 static struct workqueue_struct *qm_portal_wq; 970 971 int qman_wq_alloc(void) 972 { 973 qm_portal_wq = alloc_workqueue("qman_portal_wq", 0, 1); 974 if (!qm_portal_wq) 975 return -ENOMEM; 976 return 0; 977 } 978 979 /* 980 * This is what everything can wait on, even if it migrates to a different cpu 981 * to the one whose affine portal it is waiting on. 982 */ 983 static DECLARE_WAIT_QUEUE_HEAD(affine_queue); 984 985 static struct qman_fq **fq_table; 986 static u32 num_fqids; 987 988 int qman_alloc_fq_table(u32 _num_fqids) 989 { 990 num_fqids = _num_fqids; 991 992 fq_table = vzalloc(num_fqids * 2 * sizeof(struct qman_fq *)); 993 if (!fq_table) 994 return -ENOMEM; 995 996 pr_debug("Allocated fq lookup table at %p, entry count %u\n", 997 fq_table, num_fqids * 2); 998 return 0; 999 } 1000 1001 static struct qman_fq *idx_to_fq(u32 idx) 1002 { 1003 struct qman_fq *fq; 1004 1005 #ifdef CONFIG_FSL_DPAA_CHECKING 1006 if (WARN_ON(idx >= num_fqids * 2)) 1007 return NULL; 1008 #endif 1009 fq = fq_table[idx]; 1010 DPAA_ASSERT(!fq || idx == fq->idx); 1011 1012 return fq; 1013 } 1014 1015 /* 1016 * Only returns full-service fq objects, not enqueue-only 1017 * references (QMAN_FQ_FLAG_NO_MODIFY). 1018 */ 1019 static struct qman_fq *fqid_to_fq(u32 fqid) 1020 { 1021 return idx_to_fq(fqid * 2); 1022 } 1023 1024 static struct qman_fq *tag_to_fq(u32 tag) 1025 { 1026 #if BITS_PER_LONG == 64 1027 return idx_to_fq(tag); 1028 #else 1029 return (struct qman_fq *)tag; 1030 #endif 1031 } 1032 1033 static u32 fq_to_tag(struct qman_fq *fq) 1034 { 1035 #if BITS_PER_LONG == 64 1036 return fq->idx; 1037 #else 1038 return (u32)fq; 1039 #endif 1040 } 1041 1042 static u32 __poll_portal_slow(struct qman_portal *p, u32 is); 1043 static inline unsigned int __poll_portal_fast(struct qman_portal *p, 1044 unsigned int poll_limit); 1045 static void qm_congestion_task(struct work_struct *work); 1046 static void qm_mr_process_task(struct work_struct *work); 1047 1048 static irqreturn_t portal_isr(int irq, void *ptr) 1049 { 1050 struct qman_portal *p = ptr; 1051 1052 u32 clear = QM_DQAVAIL_MASK | p->irq_sources; 1053 u32 is = qm_in(&p->p, QM_REG_ISR) & p->irq_sources; 1054 1055 if (unlikely(!is)) 1056 return IRQ_NONE; 1057 1058 /* DQRR-handling if it's interrupt-driven */ 1059 if (is & QM_PIRQ_DQRI) 1060 __poll_portal_fast(p, QMAN_POLL_LIMIT); 1061 /* Handling of anything else that's interrupt-driven */ 1062 clear |= __poll_portal_slow(p, is); 1063 qm_out(&p->p, QM_REG_ISR, clear); 1064 return IRQ_HANDLED; 1065 } 1066 1067 static int drain_mr_fqrni(struct qm_portal *p) 1068 { 1069 const union qm_mr_entry *msg; 1070 loop: 1071 msg = qm_mr_current(p); 1072 if (!msg) { 1073 /* 1074 * if MR was full and h/w had other FQRNI entries to produce, we 1075 * need to allow it time to produce those entries once the 1076 * existing entries are consumed. A worst-case situation 1077 * (fully-loaded system) means h/w sequencers may have to do 3-4 1078 * other things before servicing the portal's MR pump, each of 1079 * which (if slow) may take ~50 qman cycles (which is ~200 1080 * processor cycles). So rounding up and then multiplying this 1081 * worst-case estimate by a factor of 10, just to be 1082 * ultra-paranoid, goes as high as 10,000 cycles. NB, we consume 1083 * one entry at a time, so h/w has an opportunity to produce new 1084 * entries well before the ring has been fully consumed, so 1085 * we're being *really* paranoid here. 1086 */ 1087 u64 now, then = jiffies; 1088 1089 do { 1090 now = jiffies; 1091 } while ((then + 10000) > now); 1092 msg = qm_mr_current(p); 1093 if (!msg) 1094 return 0; 1095 } 1096 if ((msg->verb & QM_MR_VERB_TYPE_MASK) != QM_MR_VERB_FQRNI) { 1097 /* We aren't draining anything but FQRNIs */ 1098 pr_err("Found verb 0x%x in MR\n", msg->verb); 1099 return -1; 1100 } 1101 qm_mr_next(p); 1102 qm_mr_cci_consume(p, 1); 1103 goto loop; 1104 } 1105 1106 static int qman_create_portal(struct qman_portal *portal, 1107 const struct qm_portal_config *c, 1108 const struct qman_cgrs *cgrs) 1109 { 1110 struct qm_portal *p; 1111 int ret; 1112 u32 isdr; 1113 1114 p = &portal->p; 1115 1116 #ifdef CONFIG_FSL_PAMU 1117 /* PAMU is required for stashing */ 1118 portal->use_eqcr_ci_stashing = ((qman_ip_rev >= QMAN_REV30) ? 1 : 0); 1119 #else 1120 portal->use_eqcr_ci_stashing = 0; 1121 #endif 1122 /* 1123 * prep the low-level portal struct with the mapped addresses from the 1124 * config, everything that follows depends on it and "config" is more 1125 * for (de)reference 1126 */ 1127 p->addr.ce = c->addr_virt[DPAA_PORTAL_CE]; 1128 p->addr.ci = c->addr_virt[DPAA_PORTAL_CI]; 1129 /* 1130 * If CI-stashing is used, the current defaults use a threshold of 3, 1131 * and stash with high-than-DQRR priority. 1132 */ 1133 if (qm_eqcr_init(p, qm_eqcr_pvb, 1134 portal->use_eqcr_ci_stashing ? 3 : 0, 1)) { 1135 dev_err(c->dev, "EQCR initialisation failed\n"); 1136 goto fail_eqcr; 1137 } 1138 if (qm_dqrr_init(p, c, qm_dqrr_dpush, qm_dqrr_pvb, 1139 qm_dqrr_cdc, DQRR_MAXFILL)) { 1140 dev_err(c->dev, "DQRR initialisation failed\n"); 1141 goto fail_dqrr; 1142 } 1143 if (qm_mr_init(p, qm_mr_pvb, qm_mr_cci)) { 1144 dev_err(c->dev, "MR initialisation failed\n"); 1145 goto fail_mr; 1146 } 1147 if (qm_mc_init(p)) { 1148 dev_err(c->dev, "MC initialisation failed\n"); 1149 goto fail_mc; 1150 } 1151 /* static interrupt-gating controls */ 1152 qm_dqrr_set_ithresh(p, QMAN_PIRQ_DQRR_ITHRESH); 1153 qm_mr_set_ithresh(p, QMAN_PIRQ_MR_ITHRESH); 1154 qm_out(p, QM_REG_ITPR, QMAN_PIRQ_IPERIOD); 1155 portal->cgrs = kmalloc(2 * sizeof(*cgrs), GFP_KERNEL); 1156 if (!portal->cgrs) 1157 goto fail_cgrs; 1158 /* initial snapshot is no-depletion */ 1159 qman_cgrs_init(&portal->cgrs[1]); 1160 if (cgrs) 1161 portal->cgrs[0] = *cgrs; 1162 else 1163 /* if the given mask is NULL, assume all CGRs can be seen */ 1164 qman_cgrs_fill(&portal->cgrs[0]); 1165 INIT_LIST_HEAD(&portal->cgr_cbs); 1166 spin_lock_init(&portal->cgr_lock); 1167 INIT_WORK(&portal->congestion_work, qm_congestion_task); 1168 INIT_WORK(&portal->mr_work, qm_mr_process_task); 1169 portal->bits = 0; 1170 portal->sdqcr = QM_SDQCR_SOURCE_CHANNELS | QM_SDQCR_COUNT_UPTO3 | 1171 QM_SDQCR_DEDICATED_PRECEDENCE | QM_SDQCR_TYPE_PRIO_QOS | 1172 QM_SDQCR_TOKEN_SET(0xab) | QM_SDQCR_CHANNELS_DEDICATED; 1173 isdr = 0xffffffff; 1174 qm_out(p, QM_REG_ISDR, isdr); 1175 portal->irq_sources = 0; 1176 qm_out(p, QM_REG_IER, 0); 1177 qm_out(p, QM_REG_ISR, 0xffffffff); 1178 snprintf(portal->irqname, MAX_IRQNAME, IRQNAME, c->cpu); 1179 if (request_irq(c->irq, portal_isr, 0, portal->irqname, portal)) { 1180 dev_err(c->dev, "request_irq() failed\n"); 1181 goto fail_irq; 1182 } 1183 if (c->cpu != -1 && irq_can_set_affinity(c->irq) && 1184 irq_set_affinity(c->irq, cpumask_of(c->cpu))) { 1185 dev_err(c->dev, "irq_set_affinity() failed\n"); 1186 goto fail_affinity; 1187 } 1188 1189 /* Need EQCR to be empty before continuing */ 1190 isdr &= ~QM_PIRQ_EQCI; 1191 qm_out(p, QM_REG_ISDR, isdr); 1192 ret = qm_eqcr_get_fill(p); 1193 if (ret) { 1194 dev_err(c->dev, "EQCR unclean\n"); 1195 goto fail_eqcr_empty; 1196 } 1197 isdr &= ~(QM_PIRQ_DQRI | QM_PIRQ_MRI); 1198 qm_out(p, QM_REG_ISDR, isdr); 1199 if (qm_dqrr_current(p)) { 1200 dev_err(c->dev, "DQRR unclean\n"); 1201 qm_dqrr_cdc_consume_n(p, 0xffff); 1202 } 1203 if (qm_mr_current(p) && drain_mr_fqrni(p)) { 1204 /* special handling, drain just in case it's a few FQRNIs */ 1205 const union qm_mr_entry *e = qm_mr_current(p); 1206 1207 dev_err(c->dev, "MR dirty, VB 0x%x, rc 0x%x, addr 0x%llx\n", 1208 e->verb, e->ern.rc, qm_fd_addr_get64(&e->ern.fd)); 1209 goto fail_dqrr_mr_empty; 1210 } 1211 /* Success */ 1212 portal->config = c; 1213 qm_out(p, QM_REG_ISDR, 0); 1214 qm_out(p, QM_REG_IIR, 0); 1215 /* Write a sane SDQCR */ 1216 qm_dqrr_sdqcr_set(p, portal->sdqcr); 1217 return 0; 1218 1219 fail_dqrr_mr_empty: 1220 fail_eqcr_empty: 1221 fail_affinity: 1222 free_irq(c->irq, portal); 1223 fail_irq: 1224 kfree(portal->cgrs); 1225 fail_cgrs: 1226 qm_mc_finish(p); 1227 fail_mc: 1228 qm_mr_finish(p); 1229 fail_mr: 1230 qm_dqrr_finish(p); 1231 fail_dqrr: 1232 qm_eqcr_finish(p); 1233 fail_eqcr: 1234 return -EIO; 1235 } 1236 1237 struct qman_portal *qman_create_affine_portal(const struct qm_portal_config *c, 1238 const struct qman_cgrs *cgrs) 1239 { 1240 struct qman_portal *portal; 1241 int err; 1242 1243 portal = &per_cpu(qman_affine_portal, c->cpu); 1244 err = qman_create_portal(portal, c, cgrs); 1245 if (err) 1246 return NULL; 1247 1248 spin_lock(&affine_mask_lock); 1249 cpumask_set_cpu(c->cpu, &affine_mask); 1250 affine_channels[c->cpu] = c->channel; 1251 affine_portals[c->cpu] = portal; 1252 spin_unlock(&affine_mask_lock); 1253 1254 return portal; 1255 } 1256 1257 static void qman_destroy_portal(struct qman_portal *qm) 1258 { 1259 const struct qm_portal_config *pcfg; 1260 1261 /* Stop dequeues on the portal */ 1262 qm_dqrr_sdqcr_set(&qm->p, 0); 1263 1264 /* 1265 * NB we do this to "quiesce" EQCR. If we add enqueue-completions or 1266 * something related to QM_PIRQ_EQCI, this may need fixing. 1267 * Also, due to the prefetching model used for CI updates in the enqueue 1268 * path, this update will only invalidate the CI cacheline *after* 1269 * working on it, so we need to call this twice to ensure a full update 1270 * irrespective of where the enqueue processing was at when the teardown 1271 * began. 1272 */ 1273 qm_eqcr_cce_update(&qm->p); 1274 qm_eqcr_cce_update(&qm->p); 1275 pcfg = qm->config; 1276 1277 free_irq(pcfg->irq, qm); 1278 1279 kfree(qm->cgrs); 1280 qm_mc_finish(&qm->p); 1281 qm_mr_finish(&qm->p); 1282 qm_dqrr_finish(&qm->p); 1283 qm_eqcr_finish(&qm->p); 1284 1285 qm->config = NULL; 1286 } 1287 1288 const struct qm_portal_config *qman_destroy_affine_portal(void) 1289 { 1290 struct qman_portal *qm = get_affine_portal(); 1291 const struct qm_portal_config *pcfg; 1292 int cpu; 1293 1294 pcfg = qm->config; 1295 cpu = pcfg->cpu; 1296 1297 qman_destroy_portal(qm); 1298 1299 spin_lock(&affine_mask_lock); 1300 cpumask_clear_cpu(cpu, &affine_mask); 1301 spin_unlock(&affine_mask_lock); 1302 put_affine_portal(); 1303 return pcfg; 1304 } 1305 1306 /* Inline helper to reduce nesting in __poll_portal_slow() */ 1307 static inline void fq_state_change(struct qman_portal *p, struct qman_fq *fq, 1308 const union qm_mr_entry *msg, u8 verb) 1309 { 1310 switch (verb) { 1311 case QM_MR_VERB_FQRL: 1312 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_ORL)); 1313 fq_clear(fq, QMAN_FQ_STATE_ORL); 1314 break; 1315 case QM_MR_VERB_FQRN: 1316 DPAA_ASSERT(fq->state == qman_fq_state_parked || 1317 fq->state == qman_fq_state_sched); 1318 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_CHANGING)); 1319 fq_clear(fq, QMAN_FQ_STATE_CHANGING); 1320 if (msg->fq.fqs & QM_MR_FQS_NOTEMPTY) 1321 fq_set(fq, QMAN_FQ_STATE_NE); 1322 if (msg->fq.fqs & QM_MR_FQS_ORLPRESENT) 1323 fq_set(fq, QMAN_FQ_STATE_ORL); 1324 fq->state = qman_fq_state_retired; 1325 break; 1326 case QM_MR_VERB_FQPN: 1327 DPAA_ASSERT(fq->state == qman_fq_state_sched); 1328 DPAA_ASSERT(fq_isclear(fq, QMAN_FQ_STATE_CHANGING)); 1329 fq->state = qman_fq_state_parked; 1330 } 1331 } 1332 1333 static void qm_congestion_task(struct work_struct *work) 1334 { 1335 struct qman_portal *p = container_of(work, struct qman_portal, 1336 congestion_work); 1337 struct qman_cgrs rr, c; 1338 union qm_mc_result *mcr; 1339 struct qman_cgr *cgr; 1340 1341 spin_lock(&p->cgr_lock); 1342 qm_mc_start(&p->p); 1343 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCONGESTION); 1344 if (!qm_mc_result_timeout(&p->p, &mcr)) { 1345 spin_unlock(&p->cgr_lock); 1346 dev_crit(p->config->dev, "QUERYCONGESTION timeout\n"); 1347 qman_p_irqsource_add(p, QM_PIRQ_CSCI); 1348 return; 1349 } 1350 /* mask out the ones I'm not interested in */ 1351 qman_cgrs_and(&rr, (struct qman_cgrs *)&mcr->querycongestion.state, 1352 &p->cgrs[0]); 1353 /* check previous snapshot for delta, enter/exit congestion */ 1354 qman_cgrs_xor(&c, &rr, &p->cgrs[1]); 1355 /* update snapshot */ 1356 qman_cgrs_cp(&p->cgrs[1], &rr); 1357 /* Invoke callback */ 1358 list_for_each_entry(cgr, &p->cgr_cbs, node) 1359 if (cgr->cb && qman_cgrs_get(&c, cgr->cgrid)) 1360 cgr->cb(p, cgr, qman_cgrs_get(&rr, cgr->cgrid)); 1361 spin_unlock(&p->cgr_lock); 1362 qman_p_irqsource_add(p, QM_PIRQ_CSCI); 1363 } 1364 1365 static void qm_mr_process_task(struct work_struct *work) 1366 { 1367 struct qman_portal *p = container_of(work, struct qman_portal, 1368 mr_work); 1369 const union qm_mr_entry *msg; 1370 struct qman_fq *fq; 1371 u8 verb, num = 0; 1372 1373 preempt_disable(); 1374 1375 while (1) { 1376 qm_mr_pvb_update(&p->p); 1377 msg = qm_mr_current(&p->p); 1378 if (!msg) 1379 break; 1380 1381 verb = msg->verb & QM_MR_VERB_TYPE_MASK; 1382 /* The message is a software ERN iff the 0x20 bit is clear */ 1383 if (verb & 0x20) { 1384 switch (verb) { 1385 case QM_MR_VERB_FQRNI: 1386 /* nada, we drop FQRNIs on the floor */ 1387 break; 1388 case QM_MR_VERB_FQRN: 1389 case QM_MR_VERB_FQRL: 1390 /* Lookup in the retirement table */ 1391 fq = fqid_to_fq(qm_fqid_get(&msg->fq)); 1392 if (WARN_ON(!fq)) 1393 break; 1394 fq_state_change(p, fq, msg, verb); 1395 if (fq->cb.fqs) 1396 fq->cb.fqs(p, fq, msg); 1397 break; 1398 case QM_MR_VERB_FQPN: 1399 /* Parked */ 1400 fq = tag_to_fq(be32_to_cpu(msg->fq.context_b)); 1401 fq_state_change(p, fq, msg, verb); 1402 if (fq->cb.fqs) 1403 fq->cb.fqs(p, fq, msg); 1404 break; 1405 case QM_MR_VERB_DC_ERN: 1406 /* DCP ERN */ 1407 pr_crit_once("Leaking DCP ERNs!\n"); 1408 break; 1409 default: 1410 pr_crit("Invalid MR verb 0x%02x\n", verb); 1411 } 1412 } else { 1413 /* Its a software ERN */ 1414 fq = tag_to_fq(be32_to_cpu(msg->ern.tag)); 1415 fq->cb.ern(p, fq, msg); 1416 } 1417 num++; 1418 qm_mr_next(&p->p); 1419 } 1420 1421 qm_mr_cci_consume(&p->p, num); 1422 qman_p_irqsource_add(p, QM_PIRQ_MRI); 1423 preempt_enable(); 1424 } 1425 1426 static u32 __poll_portal_slow(struct qman_portal *p, u32 is) 1427 { 1428 if (is & QM_PIRQ_CSCI) { 1429 qman_p_irqsource_remove(p, QM_PIRQ_CSCI); 1430 queue_work_on(smp_processor_id(), qm_portal_wq, 1431 &p->congestion_work); 1432 } 1433 1434 if (is & QM_PIRQ_EQRI) { 1435 qm_eqcr_cce_update(&p->p); 1436 qm_eqcr_set_ithresh(&p->p, 0); 1437 wake_up(&affine_queue); 1438 } 1439 1440 if (is & QM_PIRQ_MRI) { 1441 qman_p_irqsource_remove(p, QM_PIRQ_MRI); 1442 queue_work_on(smp_processor_id(), qm_portal_wq, 1443 &p->mr_work); 1444 } 1445 1446 return is; 1447 } 1448 1449 /* 1450 * remove some slowish-path stuff from the "fast path" and make sure it isn't 1451 * inlined. 1452 */ 1453 static noinline void clear_vdqcr(struct qman_portal *p, struct qman_fq *fq) 1454 { 1455 p->vdqcr_owned = NULL; 1456 fq_clear(fq, QMAN_FQ_STATE_VDQCR); 1457 wake_up(&affine_queue); 1458 } 1459 1460 /* 1461 * The only states that would conflict with other things if they ran at the 1462 * same time on the same cpu are: 1463 * 1464 * (i) setting/clearing vdqcr_owned, and 1465 * (ii) clearing the NE (Not Empty) flag. 1466 * 1467 * Both are safe. Because; 1468 * 1469 * (i) this clearing can only occur after qman_volatile_dequeue() has set the 1470 * vdqcr_owned field (which it does before setting VDQCR), and 1471 * qman_volatile_dequeue() blocks interrupts and preemption while this is 1472 * done so that we can't interfere. 1473 * (ii) the NE flag is only cleared after qman_retire_fq() has set it, and as 1474 * with (i) that API prevents us from interfering until it's safe. 1475 * 1476 * The good thing is that qman_volatile_dequeue() and qman_retire_fq() run far 1477 * less frequently (ie. per-FQ) than __poll_portal_fast() does, so the nett 1478 * advantage comes from this function not having to "lock" anything at all. 1479 * 1480 * Note also that the callbacks are invoked at points which are safe against the 1481 * above potential conflicts, but that this function itself is not re-entrant 1482 * (this is because the function tracks one end of each FIFO in the portal and 1483 * we do *not* want to lock that). So the consequence is that it is safe for 1484 * user callbacks to call into any QMan API. 1485 */ 1486 static inline unsigned int __poll_portal_fast(struct qman_portal *p, 1487 unsigned int poll_limit) 1488 { 1489 const struct qm_dqrr_entry *dq; 1490 struct qman_fq *fq; 1491 enum qman_cb_dqrr_result res; 1492 unsigned int limit = 0; 1493 1494 do { 1495 qm_dqrr_pvb_update(&p->p); 1496 dq = qm_dqrr_current(&p->p); 1497 if (!dq) 1498 break; 1499 1500 if (dq->stat & QM_DQRR_STAT_UNSCHEDULED) { 1501 /* 1502 * VDQCR: don't trust context_b as the FQ may have 1503 * been configured for h/w consumption and we're 1504 * draining it post-retirement. 1505 */ 1506 fq = p->vdqcr_owned; 1507 /* 1508 * We only set QMAN_FQ_STATE_NE when retiring, so we 1509 * only need to check for clearing it when doing 1510 * volatile dequeues. It's one less thing to check 1511 * in the critical path (SDQCR). 1512 */ 1513 if (dq->stat & QM_DQRR_STAT_FQ_EMPTY) 1514 fq_clear(fq, QMAN_FQ_STATE_NE); 1515 /* 1516 * This is duplicated from the SDQCR code, but we 1517 * have stuff to do before *and* after this callback, 1518 * and we don't want multiple if()s in the critical 1519 * path (SDQCR). 1520 */ 1521 res = fq->cb.dqrr(p, fq, dq); 1522 if (res == qman_cb_dqrr_stop) 1523 break; 1524 /* Check for VDQCR completion */ 1525 if (dq->stat & QM_DQRR_STAT_DQCR_EXPIRED) 1526 clear_vdqcr(p, fq); 1527 } else { 1528 /* SDQCR: context_b points to the FQ */ 1529 fq = tag_to_fq(be32_to_cpu(dq->context_b)); 1530 /* Now let the callback do its stuff */ 1531 res = fq->cb.dqrr(p, fq, dq); 1532 /* 1533 * The callback can request that we exit without 1534 * consuming this entry nor advancing; 1535 */ 1536 if (res == qman_cb_dqrr_stop) 1537 break; 1538 } 1539 /* Interpret 'dq' from a driver perspective. */ 1540 /* 1541 * Parking isn't possible unless HELDACTIVE was set. NB, 1542 * FORCEELIGIBLE implies HELDACTIVE, so we only need to 1543 * check for HELDACTIVE to cover both. 1544 */ 1545 DPAA_ASSERT((dq->stat & QM_DQRR_STAT_FQ_HELDACTIVE) || 1546 (res != qman_cb_dqrr_park)); 1547 /* just means "skip it, I'll consume it myself later on" */ 1548 if (res != qman_cb_dqrr_defer) 1549 qm_dqrr_cdc_consume_1ptr(&p->p, dq, 1550 res == qman_cb_dqrr_park); 1551 /* Move forward */ 1552 qm_dqrr_next(&p->p); 1553 /* 1554 * Entry processed and consumed, increment our counter. The 1555 * callback can request that we exit after consuming the 1556 * entry, and we also exit if we reach our processing limit, 1557 * so loop back only if neither of these conditions is met. 1558 */ 1559 } while (++limit < poll_limit && res != qman_cb_dqrr_consume_stop); 1560 1561 return limit; 1562 } 1563 1564 void qman_p_irqsource_add(struct qman_portal *p, u32 bits) 1565 { 1566 unsigned long irqflags; 1567 1568 local_irq_save(irqflags); 1569 set_bits(bits & QM_PIRQ_VISIBLE, &p->irq_sources); 1570 qm_out(&p->p, QM_REG_IER, p->irq_sources); 1571 local_irq_restore(irqflags); 1572 } 1573 EXPORT_SYMBOL(qman_p_irqsource_add); 1574 1575 void qman_p_irqsource_remove(struct qman_portal *p, u32 bits) 1576 { 1577 unsigned long irqflags; 1578 u32 ier; 1579 1580 /* 1581 * Our interrupt handler only processes+clears status register bits that 1582 * are in p->irq_sources. As we're trimming that mask, if one of them 1583 * were to assert in the status register just before we remove it from 1584 * the enable register, there would be an interrupt-storm when we 1585 * release the IRQ lock. So we wait for the enable register update to 1586 * take effect in h/w (by reading it back) and then clear all other bits 1587 * in the status register. Ie. we clear them from ISR once it's certain 1588 * IER won't allow them to reassert. 1589 */ 1590 local_irq_save(irqflags); 1591 bits &= QM_PIRQ_VISIBLE; 1592 clear_bits(bits, &p->irq_sources); 1593 qm_out(&p->p, QM_REG_IER, p->irq_sources); 1594 ier = qm_in(&p->p, QM_REG_IER); 1595 /* 1596 * Using "~ier" (rather than "bits" or "~p->irq_sources") creates a 1597 * data-dependency, ie. to protect against re-ordering. 1598 */ 1599 qm_out(&p->p, QM_REG_ISR, ~ier); 1600 local_irq_restore(irqflags); 1601 } 1602 EXPORT_SYMBOL(qman_p_irqsource_remove); 1603 1604 const cpumask_t *qman_affine_cpus(void) 1605 { 1606 return &affine_mask; 1607 } 1608 EXPORT_SYMBOL(qman_affine_cpus); 1609 1610 u16 qman_affine_channel(int cpu) 1611 { 1612 if (cpu < 0) { 1613 struct qman_portal *portal = get_affine_portal(); 1614 1615 cpu = portal->config->cpu; 1616 put_affine_portal(); 1617 } 1618 WARN_ON(!cpumask_test_cpu(cpu, &affine_mask)); 1619 return affine_channels[cpu]; 1620 } 1621 EXPORT_SYMBOL(qman_affine_channel); 1622 1623 struct qman_portal *qman_get_affine_portal(int cpu) 1624 { 1625 return affine_portals[cpu]; 1626 } 1627 EXPORT_SYMBOL(qman_get_affine_portal); 1628 1629 int qman_p_poll_dqrr(struct qman_portal *p, unsigned int limit) 1630 { 1631 return __poll_portal_fast(p, limit); 1632 } 1633 EXPORT_SYMBOL(qman_p_poll_dqrr); 1634 1635 void qman_p_static_dequeue_add(struct qman_portal *p, u32 pools) 1636 { 1637 unsigned long irqflags; 1638 1639 local_irq_save(irqflags); 1640 pools &= p->config->pools; 1641 p->sdqcr |= pools; 1642 qm_dqrr_sdqcr_set(&p->p, p->sdqcr); 1643 local_irq_restore(irqflags); 1644 } 1645 EXPORT_SYMBOL(qman_p_static_dequeue_add); 1646 1647 /* Frame queue API */ 1648 1649 static const char *mcr_result_str(u8 result) 1650 { 1651 switch (result) { 1652 case QM_MCR_RESULT_NULL: 1653 return "QM_MCR_RESULT_NULL"; 1654 case QM_MCR_RESULT_OK: 1655 return "QM_MCR_RESULT_OK"; 1656 case QM_MCR_RESULT_ERR_FQID: 1657 return "QM_MCR_RESULT_ERR_FQID"; 1658 case QM_MCR_RESULT_ERR_FQSTATE: 1659 return "QM_MCR_RESULT_ERR_FQSTATE"; 1660 case QM_MCR_RESULT_ERR_NOTEMPTY: 1661 return "QM_MCR_RESULT_ERR_NOTEMPTY"; 1662 case QM_MCR_RESULT_PENDING: 1663 return "QM_MCR_RESULT_PENDING"; 1664 case QM_MCR_RESULT_ERR_BADCOMMAND: 1665 return "QM_MCR_RESULT_ERR_BADCOMMAND"; 1666 } 1667 return "<unknown MCR result>"; 1668 } 1669 1670 int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq) 1671 { 1672 if (flags & QMAN_FQ_FLAG_DYNAMIC_FQID) { 1673 int ret = qman_alloc_fqid(&fqid); 1674 1675 if (ret) 1676 return ret; 1677 } 1678 fq->fqid = fqid; 1679 fq->flags = flags; 1680 fq->state = qman_fq_state_oos; 1681 fq->cgr_groupid = 0; 1682 1683 /* A context_b of 0 is allegedly special, so don't use that fqid */ 1684 if (fqid == 0 || fqid >= num_fqids) { 1685 WARN(1, "bad fqid %d\n", fqid); 1686 return -EINVAL; 1687 } 1688 1689 fq->idx = fqid * 2; 1690 if (flags & QMAN_FQ_FLAG_NO_MODIFY) 1691 fq->idx++; 1692 1693 WARN_ON(fq_table[fq->idx]); 1694 fq_table[fq->idx] = fq; 1695 1696 return 0; 1697 } 1698 EXPORT_SYMBOL(qman_create_fq); 1699 1700 void qman_destroy_fq(struct qman_fq *fq) 1701 { 1702 /* 1703 * We don't need to lock the FQ as it is a pre-condition that the FQ be 1704 * quiesced. Instead, run some checks. 1705 */ 1706 switch (fq->state) { 1707 case qman_fq_state_parked: 1708 case qman_fq_state_oos: 1709 if (fq_isset(fq, QMAN_FQ_FLAG_DYNAMIC_FQID)) 1710 qman_release_fqid(fq->fqid); 1711 1712 DPAA_ASSERT(fq_table[fq->idx]); 1713 fq_table[fq->idx] = NULL; 1714 return; 1715 default: 1716 break; 1717 } 1718 DPAA_ASSERT(NULL == "qman_free_fq() on unquiesced FQ!"); 1719 } 1720 EXPORT_SYMBOL(qman_destroy_fq); 1721 1722 u32 qman_fq_fqid(struct qman_fq *fq) 1723 { 1724 return fq->fqid; 1725 } 1726 EXPORT_SYMBOL(qman_fq_fqid); 1727 1728 int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts) 1729 { 1730 union qm_mc_command *mcc; 1731 union qm_mc_result *mcr; 1732 struct qman_portal *p; 1733 u8 res, myverb; 1734 int ret = 0; 1735 1736 myverb = (flags & QMAN_INITFQ_FLAG_SCHED) 1737 ? QM_MCC_VERB_INITFQ_SCHED : QM_MCC_VERB_INITFQ_PARKED; 1738 1739 if (fq->state != qman_fq_state_oos && 1740 fq->state != qman_fq_state_parked) 1741 return -EINVAL; 1742 #ifdef CONFIG_FSL_DPAA_CHECKING 1743 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)) 1744 return -EINVAL; 1745 #endif 1746 if (opts && (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_OAC)) { 1747 /* And can't be set at the same time as TDTHRESH */ 1748 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_TDTHRESH) 1749 return -EINVAL; 1750 } 1751 /* Issue an INITFQ_[PARKED|SCHED] management command */ 1752 p = get_affine_portal(); 1753 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) || 1754 (fq->state != qman_fq_state_oos && 1755 fq->state != qman_fq_state_parked)) { 1756 ret = -EBUSY; 1757 goto out; 1758 } 1759 mcc = qm_mc_start(&p->p); 1760 if (opts) 1761 mcc->initfq = *opts; 1762 qm_fqid_set(&mcc->fq, fq->fqid); 1763 mcc->initfq.count = 0; 1764 /* 1765 * If the FQ does *not* have the TO_DCPORTAL flag, context_b is set as a 1766 * demux pointer. Otherwise, the caller-provided value is allowed to 1767 * stand, don't overwrite it. 1768 */ 1769 if (fq_isclear(fq, QMAN_FQ_FLAG_TO_DCPORTAL)) { 1770 dma_addr_t phys_fq; 1771 1772 mcc->initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTB); 1773 mcc->initfq.fqd.context_b = cpu_to_be32(fq_to_tag(fq)); 1774 /* 1775 * and the physical address - NB, if the user wasn't trying to 1776 * set CONTEXTA, clear the stashing settings. 1777 */ 1778 if (!(be16_to_cpu(mcc->initfq.we_mask) & 1779 QM_INITFQ_WE_CONTEXTA)) { 1780 mcc->initfq.we_mask |= 1781 cpu_to_be16(QM_INITFQ_WE_CONTEXTA); 1782 memset(&mcc->initfq.fqd.context_a, 0, 1783 sizeof(mcc->initfq.fqd.context_a)); 1784 } else { 1785 struct qman_portal *p = qman_dma_portal; 1786 1787 phys_fq = dma_map_single(p->config->dev, fq, 1788 sizeof(*fq), DMA_TO_DEVICE); 1789 if (dma_mapping_error(p->config->dev, phys_fq)) { 1790 dev_err(p->config->dev, "dma_mapping failed\n"); 1791 ret = -EIO; 1792 goto out; 1793 } 1794 1795 qm_fqd_stashing_set64(&mcc->initfq.fqd, phys_fq); 1796 } 1797 } 1798 if (flags & QMAN_INITFQ_FLAG_LOCAL) { 1799 int wq = 0; 1800 1801 if (!(be16_to_cpu(mcc->initfq.we_mask) & 1802 QM_INITFQ_WE_DESTWQ)) { 1803 mcc->initfq.we_mask |= 1804 cpu_to_be16(QM_INITFQ_WE_DESTWQ); 1805 wq = 4; 1806 } 1807 qm_fqd_set_destwq(&mcc->initfq.fqd, p->config->channel, wq); 1808 } 1809 qm_mc_commit(&p->p, myverb); 1810 if (!qm_mc_result_timeout(&p->p, &mcr)) { 1811 dev_err(p->config->dev, "MCR timeout\n"); 1812 ret = -ETIMEDOUT; 1813 goto out; 1814 } 1815 1816 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb); 1817 res = mcr->result; 1818 if (res != QM_MCR_RESULT_OK) { 1819 ret = -EIO; 1820 goto out; 1821 } 1822 if (opts) { 1823 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_FQCTRL) { 1824 if (be16_to_cpu(opts->fqd.fq_ctrl) & QM_FQCTRL_CGE) 1825 fq_set(fq, QMAN_FQ_STATE_CGR_EN); 1826 else 1827 fq_clear(fq, QMAN_FQ_STATE_CGR_EN); 1828 } 1829 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_CGID) 1830 fq->cgr_groupid = opts->fqd.cgid; 1831 } 1832 fq->state = (flags & QMAN_INITFQ_FLAG_SCHED) ? 1833 qman_fq_state_sched : qman_fq_state_parked; 1834 1835 out: 1836 put_affine_portal(); 1837 return ret; 1838 } 1839 EXPORT_SYMBOL(qman_init_fq); 1840 1841 int qman_schedule_fq(struct qman_fq *fq) 1842 { 1843 union qm_mc_command *mcc; 1844 union qm_mc_result *mcr; 1845 struct qman_portal *p; 1846 int ret = 0; 1847 1848 if (fq->state != qman_fq_state_parked) 1849 return -EINVAL; 1850 #ifdef CONFIG_FSL_DPAA_CHECKING 1851 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)) 1852 return -EINVAL; 1853 #endif 1854 /* Issue a ALTERFQ_SCHED management command */ 1855 p = get_affine_portal(); 1856 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) || 1857 fq->state != qman_fq_state_parked) { 1858 ret = -EBUSY; 1859 goto out; 1860 } 1861 mcc = qm_mc_start(&p->p); 1862 qm_fqid_set(&mcc->fq, fq->fqid); 1863 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_SCHED); 1864 if (!qm_mc_result_timeout(&p->p, &mcr)) { 1865 dev_err(p->config->dev, "ALTER_SCHED timeout\n"); 1866 ret = -ETIMEDOUT; 1867 goto out; 1868 } 1869 1870 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_SCHED); 1871 if (mcr->result != QM_MCR_RESULT_OK) { 1872 ret = -EIO; 1873 goto out; 1874 } 1875 fq->state = qman_fq_state_sched; 1876 out: 1877 put_affine_portal(); 1878 return ret; 1879 } 1880 EXPORT_SYMBOL(qman_schedule_fq); 1881 1882 int qman_retire_fq(struct qman_fq *fq, u32 *flags) 1883 { 1884 union qm_mc_command *mcc; 1885 union qm_mc_result *mcr; 1886 struct qman_portal *p; 1887 int ret; 1888 u8 res; 1889 1890 if (fq->state != qman_fq_state_parked && 1891 fq->state != qman_fq_state_sched) 1892 return -EINVAL; 1893 #ifdef CONFIG_FSL_DPAA_CHECKING 1894 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)) 1895 return -EINVAL; 1896 #endif 1897 p = get_affine_portal(); 1898 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) || 1899 fq->state == qman_fq_state_retired || 1900 fq->state == qman_fq_state_oos) { 1901 ret = -EBUSY; 1902 goto out; 1903 } 1904 mcc = qm_mc_start(&p->p); 1905 qm_fqid_set(&mcc->fq, fq->fqid); 1906 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE); 1907 if (!qm_mc_result_timeout(&p->p, &mcr)) { 1908 dev_crit(p->config->dev, "ALTER_RETIRE timeout\n"); 1909 ret = -ETIMEDOUT; 1910 goto out; 1911 } 1912 1913 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_RETIRE); 1914 res = mcr->result; 1915 /* 1916 * "Elegant" would be to treat OK/PENDING the same way; set CHANGING, 1917 * and defer the flags until FQRNI or FQRN (respectively) show up. But 1918 * "Friendly" is to process OK immediately, and not set CHANGING. We do 1919 * friendly, otherwise the caller doesn't necessarily have a fully 1920 * "retired" FQ on return even if the retirement was immediate. However 1921 * this does mean some code duplication between here and 1922 * fq_state_change(). 1923 */ 1924 if (res == QM_MCR_RESULT_OK) { 1925 ret = 0; 1926 /* Process 'fq' right away, we'll ignore FQRNI */ 1927 if (mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY) 1928 fq_set(fq, QMAN_FQ_STATE_NE); 1929 if (mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT) 1930 fq_set(fq, QMAN_FQ_STATE_ORL); 1931 if (flags) 1932 *flags = fq->flags; 1933 fq->state = qman_fq_state_retired; 1934 if (fq->cb.fqs) { 1935 /* 1936 * Another issue with supporting "immediate" retirement 1937 * is that we're forced to drop FQRNIs, because by the 1938 * time they're seen it may already be "too late" (the 1939 * fq may have been OOS'd and free()'d already). But if 1940 * the upper layer wants a callback whether it's 1941 * immediate or not, we have to fake a "MR" entry to 1942 * look like an FQRNI... 1943 */ 1944 union qm_mr_entry msg; 1945 1946 msg.verb = QM_MR_VERB_FQRNI; 1947 msg.fq.fqs = mcr->alterfq.fqs; 1948 qm_fqid_set(&msg.fq, fq->fqid); 1949 msg.fq.context_b = cpu_to_be32(fq_to_tag(fq)); 1950 fq->cb.fqs(p, fq, &msg); 1951 } 1952 } else if (res == QM_MCR_RESULT_PENDING) { 1953 ret = 1; 1954 fq_set(fq, QMAN_FQ_STATE_CHANGING); 1955 } else { 1956 ret = -EIO; 1957 } 1958 out: 1959 put_affine_portal(); 1960 return ret; 1961 } 1962 EXPORT_SYMBOL(qman_retire_fq); 1963 1964 int qman_oos_fq(struct qman_fq *fq) 1965 { 1966 union qm_mc_command *mcc; 1967 union qm_mc_result *mcr; 1968 struct qman_portal *p; 1969 int ret = 0; 1970 1971 if (fq->state != qman_fq_state_retired) 1972 return -EINVAL; 1973 #ifdef CONFIG_FSL_DPAA_CHECKING 1974 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)) 1975 return -EINVAL; 1976 #endif 1977 p = get_affine_portal(); 1978 if (fq_isset(fq, QMAN_FQ_STATE_BLOCKOOS) || 1979 fq->state != qman_fq_state_retired) { 1980 ret = -EBUSY; 1981 goto out; 1982 } 1983 mcc = qm_mc_start(&p->p); 1984 qm_fqid_set(&mcc->fq, fq->fqid); 1985 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS); 1986 if (!qm_mc_result_timeout(&p->p, &mcr)) { 1987 ret = -ETIMEDOUT; 1988 goto out; 1989 } 1990 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_OOS); 1991 if (mcr->result != QM_MCR_RESULT_OK) { 1992 ret = -EIO; 1993 goto out; 1994 } 1995 fq->state = qman_fq_state_oos; 1996 out: 1997 put_affine_portal(); 1998 return ret; 1999 } 2000 EXPORT_SYMBOL(qman_oos_fq); 2001 2002 int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd) 2003 { 2004 union qm_mc_command *mcc; 2005 union qm_mc_result *mcr; 2006 struct qman_portal *p = get_affine_portal(); 2007 int ret = 0; 2008 2009 mcc = qm_mc_start(&p->p); 2010 qm_fqid_set(&mcc->fq, fq->fqid); 2011 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ); 2012 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2013 ret = -ETIMEDOUT; 2014 goto out; 2015 } 2016 2017 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ); 2018 if (mcr->result == QM_MCR_RESULT_OK) 2019 *fqd = mcr->queryfq.fqd; 2020 else 2021 ret = -EIO; 2022 out: 2023 put_affine_portal(); 2024 return ret; 2025 } 2026 2027 int qman_query_fq_np(struct qman_fq *fq, struct qm_mcr_queryfq_np *np) 2028 { 2029 union qm_mc_command *mcc; 2030 union qm_mc_result *mcr; 2031 struct qman_portal *p = get_affine_portal(); 2032 int ret = 0; 2033 2034 mcc = qm_mc_start(&p->p); 2035 qm_fqid_set(&mcc->fq, fq->fqid); 2036 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP); 2037 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2038 ret = -ETIMEDOUT; 2039 goto out; 2040 } 2041 2042 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP); 2043 if (mcr->result == QM_MCR_RESULT_OK) 2044 *np = mcr->queryfq_np; 2045 else if (mcr->result == QM_MCR_RESULT_ERR_FQID) 2046 ret = -ERANGE; 2047 else 2048 ret = -EIO; 2049 out: 2050 put_affine_portal(); 2051 return ret; 2052 } 2053 EXPORT_SYMBOL(qman_query_fq_np); 2054 2055 static int qman_query_cgr(struct qman_cgr *cgr, 2056 struct qm_mcr_querycgr *cgrd) 2057 { 2058 union qm_mc_command *mcc; 2059 union qm_mc_result *mcr; 2060 struct qman_portal *p = get_affine_portal(); 2061 int ret = 0; 2062 2063 mcc = qm_mc_start(&p->p); 2064 mcc->cgr.cgid = cgr->cgrid; 2065 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCGR); 2066 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2067 ret = -ETIMEDOUT; 2068 goto out; 2069 } 2070 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYCGR); 2071 if (mcr->result == QM_MCR_RESULT_OK) 2072 *cgrd = mcr->querycgr; 2073 else { 2074 dev_err(p->config->dev, "QUERY_CGR failed: %s\n", 2075 mcr_result_str(mcr->result)); 2076 ret = -EIO; 2077 } 2078 out: 2079 put_affine_portal(); 2080 return ret; 2081 } 2082 2083 int qman_query_cgr_congested(struct qman_cgr *cgr, bool *result) 2084 { 2085 struct qm_mcr_querycgr query_cgr; 2086 int err; 2087 2088 err = qman_query_cgr(cgr, &query_cgr); 2089 if (err) 2090 return err; 2091 2092 *result = !!query_cgr.cgr.cs; 2093 return 0; 2094 } 2095 EXPORT_SYMBOL(qman_query_cgr_congested); 2096 2097 /* internal function used as a wait_event() expression */ 2098 static int set_p_vdqcr(struct qman_portal *p, struct qman_fq *fq, u32 vdqcr) 2099 { 2100 unsigned long irqflags; 2101 int ret = -EBUSY; 2102 2103 local_irq_save(irqflags); 2104 if (p->vdqcr_owned) 2105 goto out; 2106 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR)) 2107 goto out; 2108 2109 fq_set(fq, QMAN_FQ_STATE_VDQCR); 2110 p->vdqcr_owned = fq; 2111 qm_dqrr_vdqcr_set(&p->p, vdqcr); 2112 ret = 0; 2113 out: 2114 local_irq_restore(irqflags); 2115 return ret; 2116 } 2117 2118 static int set_vdqcr(struct qman_portal **p, struct qman_fq *fq, u32 vdqcr) 2119 { 2120 int ret; 2121 2122 *p = get_affine_portal(); 2123 ret = set_p_vdqcr(*p, fq, vdqcr); 2124 put_affine_portal(); 2125 return ret; 2126 } 2127 2128 static int wait_vdqcr_start(struct qman_portal **p, struct qman_fq *fq, 2129 u32 vdqcr, u32 flags) 2130 { 2131 int ret = 0; 2132 2133 if (flags & QMAN_VOLATILE_FLAG_WAIT_INT) 2134 ret = wait_event_interruptible(affine_queue, 2135 !set_vdqcr(p, fq, vdqcr)); 2136 else 2137 wait_event(affine_queue, !set_vdqcr(p, fq, vdqcr)); 2138 return ret; 2139 } 2140 2141 int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr) 2142 { 2143 struct qman_portal *p; 2144 int ret; 2145 2146 if (fq->state != qman_fq_state_parked && 2147 fq->state != qman_fq_state_retired) 2148 return -EINVAL; 2149 if (vdqcr & QM_VDQCR_FQID_MASK) 2150 return -EINVAL; 2151 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR)) 2152 return -EBUSY; 2153 vdqcr = (vdqcr & ~QM_VDQCR_FQID_MASK) | fq->fqid; 2154 if (flags & QMAN_VOLATILE_FLAG_WAIT) 2155 ret = wait_vdqcr_start(&p, fq, vdqcr, flags); 2156 else 2157 ret = set_vdqcr(&p, fq, vdqcr); 2158 if (ret) 2159 return ret; 2160 /* VDQCR is set */ 2161 if (flags & QMAN_VOLATILE_FLAG_FINISH) { 2162 if (flags & QMAN_VOLATILE_FLAG_WAIT_INT) 2163 /* 2164 * NB: don't propagate any error - the caller wouldn't 2165 * know whether the VDQCR was issued or not. A signal 2166 * could arrive after returning anyway, so the caller 2167 * can check signal_pending() if that's an issue. 2168 */ 2169 wait_event_interruptible(affine_queue, 2170 !fq_isset(fq, QMAN_FQ_STATE_VDQCR)); 2171 else 2172 wait_event(affine_queue, 2173 !fq_isset(fq, QMAN_FQ_STATE_VDQCR)); 2174 } 2175 return 0; 2176 } 2177 EXPORT_SYMBOL(qman_volatile_dequeue); 2178 2179 static void update_eqcr_ci(struct qman_portal *p, u8 avail) 2180 { 2181 if (avail) 2182 qm_eqcr_cce_prefetch(&p->p); 2183 else 2184 qm_eqcr_cce_update(&p->p); 2185 } 2186 2187 int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd) 2188 { 2189 struct qman_portal *p; 2190 struct qm_eqcr_entry *eq; 2191 unsigned long irqflags; 2192 u8 avail; 2193 2194 p = get_affine_portal(); 2195 local_irq_save(irqflags); 2196 2197 if (p->use_eqcr_ci_stashing) { 2198 /* 2199 * The stashing case is easy, only update if we need to in 2200 * order to try and liberate ring entries. 2201 */ 2202 eq = qm_eqcr_start_stash(&p->p); 2203 } else { 2204 /* 2205 * The non-stashing case is harder, need to prefetch ahead of 2206 * time. 2207 */ 2208 avail = qm_eqcr_get_avail(&p->p); 2209 if (avail < 2) 2210 update_eqcr_ci(p, avail); 2211 eq = qm_eqcr_start_no_stash(&p->p); 2212 } 2213 2214 if (unlikely(!eq)) 2215 goto out; 2216 2217 qm_fqid_set(eq, fq->fqid); 2218 eq->tag = cpu_to_be32(fq_to_tag(fq)); 2219 eq->fd = *fd; 2220 2221 qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_CMD_ENQUEUE); 2222 out: 2223 local_irq_restore(irqflags); 2224 put_affine_portal(); 2225 return 0; 2226 } 2227 EXPORT_SYMBOL(qman_enqueue); 2228 2229 static int qm_modify_cgr(struct qman_cgr *cgr, u32 flags, 2230 struct qm_mcc_initcgr *opts) 2231 { 2232 union qm_mc_command *mcc; 2233 union qm_mc_result *mcr; 2234 struct qman_portal *p = get_affine_portal(); 2235 u8 verb = QM_MCC_VERB_MODIFYCGR; 2236 int ret = 0; 2237 2238 mcc = qm_mc_start(&p->p); 2239 if (opts) 2240 mcc->initcgr = *opts; 2241 mcc->initcgr.cgid = cgr->cgrid; 2242 if (flags & QMAN_CGR_FLAG_USE_INIT) 2243 verb = QM_MCC_VERB_INITCGR; 2244 qm_mc_commit(&p->p, verb); 2245 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2246 ret = -ETIMEDOUT; 2247 goto out; 2248 } 2249 2250 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == verb); 2251 if (mcr->result != QM_MCR_RESULT_OK) 2252 ret = -EIO; 2253 2254 out: 2255 put_affine_portal(); 2256 return ret; 2257 } 2258 2259 #define PORTAL_IDX(n) (n->config->channel - QM_CHANNEL_SWPORTAL0) 2260 2261 /* congestion state change notification target update control */ 2262 static void qm_cgr_cscn_targ_set(struct __qm_mc_cgr *cgr, int pi, u32 val) 2263 { 2264 if (qman_ip_rev >= QMAN_REV30) 2265 cgr->cscn_targ_upd_ctrl = cpu_to_be16(pi | 2266 QM_CGR_TARG_UDP_CTRL_WRITE_BIT); 2267 else 2268 cgr->cscn_targ = cpu_to_be32(val | QM_CGR_TARG_PORTAL(pi)); 2269 } 2270 2271 static void qm_cgr_cscn_targ_clear(struct __qm_mc_cgr *cgr, int pi, u32 val) 2272 { 2273 if (qman_ip_rev >= QMAN_REV30) 2274 cgr->cscn_targ_upd_ctrl = cpu_to_be16(pi); 2275 else 2276 cgr->cscn_targ = cpu_to_be32(val & ~QM_CGR_TARG_PORTAL(pi)); 2277 } 2278 2279 static u8 qman_cgr_cpus[CGR_NUM]; 2280 2281 void qman_init_cgr_all(void) 2282 { 2283 struct qman_cgr cgr; 2284 int err_cnt = 0; 2285 2286 for (cgr.cgrid = 0; cgr.cgrid < CGR_NUM; cgr.cgrid++) { 2287 if (qm_modify_cgr(&cgr, QMAN_CGR_FLAG_USE_INIT, NULL)) 2288 err_cnt++; 2289 } 2290 2291 if (err_cnt) 2292 pr_err("Warning: %d error%s while initialising CGR h/w\n", 2293 err_cnt, (err_cnt > 1) ? "s" : ""); 2294 } 2295 2296 int qman_create_cgr(struct qman_cgr *cgr, u32 flags, 2297 struct qm_mcc_initcgr *opts) 2298 { 2299 struct qm_mcr_querycgr cgr_state; 2300 int ret; 2301 struct qman_portal *p; 2302 2303 /* 2304 * We have to check that the provided CGRID is within the limits of the 2305 * data-structures, for obvious reasons. However we'll let h/w take 2306 * care of determining whether it's within the limits of what exists on 2307 * the SoC. 2308 */ 2309 if (cgr->cgrid >= CGR_NUM) 2310 return -EINVAL; 2311 2312 preempt_disable(); 2313 p = get_affine_portal(); 2314 qman_cgr_cpus[cgr->cgrid] = smp_processor_id(); 2315 preempt_enable(); 2316 2317 cgr->chan = p->config->channel; 2318 spin_lock(&p->cgr_lock); 2319 2320 if (opts) { 2321 struct qm_mcc_initcgr local_opts = *opts; 2322 2323 ret = qman_query_cgr(cgr, &cgr_state); 2324 if (ret) 2325 goto out; 2326 2327 qm_cgr_cscn_targ_set(&local_opts.cgr, PORTAL_IDX(p), 2328 be32_to_cpu(cgr_state.cgr.cscn_targ)); 2329 local_opts.we_mask |= cpu_to_be16(QM_CGR_WE_CSCN_TARG); 2330 2331 /* send init if flags indicate so */ 2332 if (flags & QMAN_CGR_FLAG_USE_INIT) 2333 ret = qm_modify_cgr(cgr, QMAN_CGR_FLAG_USE_INIT, 2334 &local_opts); 2335 else 2336 ret = qm_modify_cgr(cgr, 0, &local_opts); 2337 if (ret) 2338 goto out; 2339 } 2340 2341 list_add(&cgr->node, &p->cgr_cbs); 2342 2343 /* Determine if newly added object requires its callback to be called */ 2344 ret = qman_query_cgr(cgr, &cgr_state); 2345 if (ret) { 2346 /* we can't go back, so proceed and return success */ 2347 dev_err(p->config->dev, "CGR HW state partially modified\n"); 2348 ret = 0; 2349 goto out; 2350 } 2351 if (cgr->cb && cgr_state.cgr.cscn_en && 2352 qman_cgrs_get(&p->cgrs[1], cgr->cgrid)) 2353 cgr->cb(p, cgr, 1); 2354 out: 2355 spin_unlock(&p->cgr_lock); 2356 put_affine_portal(); 2357 return ret; 2358 } 2359 EXPORT_SYMBOL(qman_create_cgr); 2360 2361 int qman_delete_cgr(struct qman_cgr *cgr) 2362 { 2363 unsigned long irqflags; 2364 struct qm_mcr_querycgr cgr_state; 2365 struct qm_mcc_initcgr local_opts; 2366 int ret = 0; 2367 struct qman_cgr *i; 2368 struct qman_portal *p = get_affine_portal(); 2369 2370 if (cgr->chan != p->config->channel) { 2371 /* attempt to delete from other portal than creator */ 2372 dev_err(p->config->dev, "CGR not owned by current portal"); 2373 dev_dbg(p->config->dev, " create 0x%x, delete 0x%x\n", 2374 cgr->chan, p->config->channel); 2375 2376 ret = -EINVAL; 2377 goto put_portal; 2378 } 2379 memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr)); 2380 spin_lock_irqsave(&p->cgr_lock, irqflags); 2381 list_del(&cgr->node); 2382 /* 2383 * If there are no other CGR objects for this CGRID in the list, 2384 * update CSCN_TARG accordingly 2385 */ 2386 list_for_each_entry(i, &p->cgr_cbs, node) 2387 if (i->cgrid == cgr->cgrid && i->cb) 2388 goto release_lock; 2389 ret = qman_query_cgr(cgr, &cgr_state); 2390 if (ret) { 2391 /* add back to the list */ 2392 list_add(&cgr->node, &p->cgr_cbs); 2393 goto release_lock; 2394 } 2395 2396 local_opts.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_TARG); 2397 qm_cgr_cscn_targ_clear(&local_opts.cgr, PORTAL_IDX(p), 2398 be32_to_cpu(cgr_state.cgr.cscn_targ)); 2399 2400 ret = qm_modify_cgr(cgr, 0, &local_opts); 2401 if (ret) 2402 /* add back to the list */ 2403 list_add(&cgr->node, &p->cgr_cbs); 2404 release_lock: 2405 spin_unlock_irqrestore(&p->cgr_lock, irqflags); 2406 put_portal: 2407 put_affine_portal(); 2408 return ret; 2409 } 2410 EXPORT_SYMBOL(qman_delete_cgr); 2411 2412 struct cgr_comp { 2413 struct qman_cgr *cgr; 2414 struct completion completion; 2415 }; 2416 2417 static int qman_delete_cgr_thread(void *p) 2418 { 2419 struct cgr_comp *cgr_comp = (struct cgr_comp *)p; 2420 int ret; 2421 2422 ret = qman_delete_cgr(cgr_comp->cgr); 2423 complete(&cgr_comp->completion); 2424 2425 return ret; 2426 } 2427 2428 void qman_delete_cgr_safe(struct qman_cgr *cgr) 2429 { 2430 struct task_struct *thread; 2431 struct cgr_comp cgr_comp; 2432 2433 preempt_disable(); 2434 if (qman_cgr_cpus[cgr->cgrid] != smp_processor_id()) { 2435 init_completion(&cgr_comp.completion); 2436 cgr_comp.cgr = cgr; 2437 thread = kthread_create(qman_delete_cgr_thread, &cgr_comp, 2438 "cgr_del"); 2439 2440 if (IS_ERR(thread)) 2441 goto out; 2442 2443 kthread_bind(thread, qman_cgr_cpus[cgr->cgrid]); 2444 wake_up_process(thread); 2445 wait_for_completion(&cgr_comp.completion); 2446 preempt_enable(); 2447 return; 2448 } 2449 out: 2450 qman_delete_cgr(cgr); 2451 preempt_enable(); 2452 } 2453 EXPORT_SYMBOL(qman_delete_cgr_safe); 2454 2455 /* Cleanup FQs */ 2456 2457 static int _qm_mr_consume_and_match_verb(struct qm_portal *p, int v) 2458 { 2459 const union qm_mr_entry *msg; 2460 int found = 0; 2461 2462 qm_mr_pvb_update(p); 2463 msg = qm_mr_current(p); 2464 while (msg) { 2465 if ((msg->verb & QM_MR_VERB_TYPE_MASK) == v) 2466 found = 1; 2467 qm_mr_next(p); 2468 qm_mr_cci_consume_to_current(p); 2469 qm_mr_pvb_update(p); 2470 msg = qm_mr_current(p); 2471 } 2472 return found; 2473 } 2474 2475 static int _qm_dqrr_consume_and_match(struct qm_portal *p, u32 fqid, int s, 2476 bool wait) 2477 { 2478 const struct qm_dqrr_entry *dqrr; 2479 int found = 0; 2480 2481 do { 2482 qm_dqrr_pvb_update(p); 2483 dqrr = qm_dqrr_current(p); 2484 if (!dqrr) 2485 cpu_relax(); 2486 } while (wait && !dqrr); 2487 2488 while (dqrr) { 2489 if (qm_fqid_get(dqrr) == fqid && (dqrr->stat & s)) 2490 found = 1; 2491 qm_dqrr_cdc_consume_1ptr(p, dqrr, 0); 2492 qm_dqrr_pvb_update(p); 2493 qm_dqrr_next(p); 2494 dqrr = qm_dqrr_current(p); 2495 } 2496 return found; 2497 } 2498 2499 #define qm_mr_drain(p, V) \ 2500 _qm_mr_consume_and_match_verb(p, QM_MR_VERB_##V) 2501 2502 #define qm_dqrr_drain(p, f, S) \ 2503 _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, false) 2504 2505 #define qm_dqrr_drain_wait(p, f, S) \ 2506 _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, true) 2507 2508 #define qm_dqrr_drain_nomatch(p) \ 2509 _qm_dqrr_consume_and_match(p, 0, 0, false) 2510 2511 static int qman_shutdown_fq(u32 fqid) 2512 { 2513 struct qman_portal *p; 2514 struct device *dev; 2515 union qm_mc_command *mcc; 2516 union qm_mc_result *mcr; 2517 int orl_empty, drain = 0, ret = 0; 2518 u32 channel, wq, res; 2519 u8 state; 2520 2521 p = get_affine_portal(); 2522 dev = p->config->dev; 2523 /* Determine the state of the FQID */ 2524 mcc = qm_mc_start(&p->p); 2525 qm_fqid_set(&mcc->fq, fqid); 2526 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP); 2527 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2528 dev_err(dev, "QUERYFQ_NP timeout\n"); 2529 ret = -ETIMEDOUT; 2530 goto out; 2531 } 2532 2533 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP); 2534 state = mcr->queryfq_np.state & QM_MCR_NP_STATE_MASK; 2535 if (state == QM_MCR_NP_STATE_OOS) 2536 goto out; /* Already OOS, no need to do anymore checks */ 2537 2538 /* Query which channel the FQ is using */ 2539 mcc = qm_mc_start(&p->p); 2540 qm_fqid_set(&mcc->fq, fqid); 2541 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ); 2542 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2543 dev_err(dev, "QUERYFQ timeout\n"); 2544 ret = -ETIMEDOUT; 2545 goto out; 2546 } 2547 2548 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ); 2549 /* Need to store these since the MCR gets reused */ 2550 channel = qm_fqd_get_chan(&mcr->queryfq.fqd); 2551 wq = qm_fqd_get_wq(&mcr->queryfq.fqd); 2552 2553 switch (state) { 2554 case QM_MCR_NP_STATE_TEN_SCHED: 2555 case QM_MCR_NP_STATE_TRU_SCHED: 2556 case QM_MCR_NP_STATE_ACTIVE: 2557 case QM_MCR_NP_STATE_PARKED: 2558 orl_empty = 0; 2559 mcc = qm_mc_start(&p->p); 2560 qm_fqid_set(&mcc->fq, fqid); 2561 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE); 2562 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2563 dev_err(dev, "QUERYFQ_NP timeout\n"); 2564 ret = -ETIMEDOUT; 2565 goto out; 2566 } 2567 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == 2568 QM_MCR_VERB_ALTER_RETIRE); 2569 res = mcr->result; /* Make a copy as we reuse MCR below */ 2570 2571 if (res == QM_MCR_RESULT_PENDING) { 2572 /* 2573 * Need to wait for the FQRN in the message ring, which 2574 * will only occur once the FQ has been drained. In 2575 * order for the FQ to drain the portal needs to be set 2576 * to dequeue from the channel the FQ is scheduled on 2577 */ 2578 int found_fqrn = 0; 2579 u16 dequeue_wq = 0; 2580 2581 /* Flag that we need to drain FQ */ 2582 drain = 1; 2583 2584 if (channel >= qm_channel_pool1 && 2585 channel < qm_channel_pool1 + 15) { 2586 /* Pool channel, enable the bit in the portal */ 2587 dequeue_wq = (channel - 2588 qm_channel_pool1 + 1)<<4 | wq; 2589 } else if (channel < qm_channel_pool1) { 2590 /* Dedicated channel */ 2591 dequeue_wq = wq; 2592 } else { 2593 dev_err(dev, "Can't recover FQ 0x%x, ch: 0x%x", 2594 fqid, channel); 2595 ret = -EBUSY; 2596 goto out; 2597 } 2598 /* Set the sdqcr to drain this channel */ 2599 if (channel < qm_channel_pool1) 2600 qm_dqrr_sdqcr_set(&p->p, 2601 QM_SDQCR_TYPE_ACTIVE | 2602 QM_SDQCR_CHANNELS_DEDICATED); 2603 else 2604 qm_dqrr_sdqcr_set(&p->p, 2605 QM_SDQCR_TYPE_ACTIVE | 2606 QM_SDQCR_CHANNELS_POOL_CONV 2607 (channel)); 2608 do { 2609 /* Keep draining DQRR while checking the MR*/ 2610 qm_dqrr_drain_nomatch(&p->p); 2611 /* Process message ring too */ 2612 found_fqrn = qm_mr_drain(&p->p, FQRN); 2613 cpu_relax(); 2614 } while (!found_fqrn); 2615 2616 } 2617 if (res != QM_MCR_RESULT_OK && 2618 res != QM_MCR_RESULT_PENDING) { 2619 dev_err(dev, "retire_fq failed: FQ 0x%x, res=0x%x\n", 2620 fqid, res); 2621 ret = -EIO; 2622 goto out; 2623 } 2624 if (!(mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)) { 2625 /* 2626 * ORL had no entries, no need to wait until the 2627 * ERNs come in 2628 */ 2629 orl_empty = 1; 2630 } 2631 /* 2632 * Retirement succeeded, check to see if FQ needs 2633 * to be drained 2634 */ 2635 if (drain || mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY) { 2636 /* FQ is Not Empty, drain using volatile DQ commands */ 2637 do { 2638 u32 vdqcr = fqid | QM_VDQCR_NUMFRAMES_SET(3); 2639 2640 qm_dqrr_vdqcr_set(&p->p, vdqcr); 2641 /* 2642 * Wait for a dequeue and process the dequeues, 2643 * making sure to empty the ring completely 2644 */ 2645 } while (qm_dqrr_drain_wait(&p->p, fqid, FQ_EMPTY)); 2646 } 2647 qm_dqrr_sdqcr_set(&p->p, 0); 2648 2649 while (!orl_empty) { 2650 /* Wait for the ORL to have been completely drained */ 2651 orl_empty = qm_mr_drain(&p->p, FQRL); 2652 cpu_relax(); 2653 } 2654 mcc = qm_mc_start(&p->p); 2655 qm_fqid_set(&mcc->fq, fqid); 2656 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS); 2657 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2658 ret = -ETIMEDOUT; 2659 goto out; 2660 } 2661 2662 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == 2663 QM_MCR_VERB_ALTER_OOS); 2664 if (mcr->result != QM_MCR_RESULT_OK) { 2665 dev_err(dev, "OOS after drain fail: FQ 0x%x (0x%x)\n", 2666 fqid, mcr->result); 2667 ret = -EIO; 2668 goto out; 2669 } 2670 break; 2671 2672 case QM_MCR_NP_STATE_RETIRED: 2673 /* Send OOS Command */ 2674 mcc = qm_mc_start(&p->p); 2675 qm_fqid_set(&mcc->fq, fqid); 2676 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS); 2677 if (!qm_mc_result_timeout(&p->p, &mcr)) { 2678 ret = -ETIMEDOUT; 2679 goto out; 2680 } 2681 2682 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == 2683 QM_MCR_VERB_ALTER_OOS); 2684 if (mcr->result) { 2685 dev_err(dev, "OOS fail: FQ 0x%x (0x%x)\n", 2686 fqid, mcr->result); 2687 ret = -EIO; 2688 goto out; 2689 } 2690 break; 2691 2692 case QM_MCR_NP_STATE_OOS: 2693 /* Done */ 2694 break; 2695 2696 default: 2697 ret = -EIO; 2698 } 2699 2700 out: 2701 put_affine_portal(); 2702 return ret; 2703 } 2704 2705 const struct qm_portal_config *qman_get_qm_portal_config( 2706 struct qman_portal *portal) 2707 { 2708 return portal->config; 2709 } 2710 EXPORT_SYMBOL(qman_get_qm_portal_config); 2711 2712 struct gen_pool *qm_fqalloc; /* FQID allocator */ 2713 struct gen_pool *qm_qpalloc; /* pool-channel allocator */ 2714 struct gen_pool *qm_cgralloc; /* CGR ID allocator */ 2715 2716 static int qman_alloc_range(struct gen_pool *p, u32 *result, u32 cnt) 2717 { 2718 unsigned long addr; 2719 2720 addr = gen_pool_alloc(p, cnt); 2721 if (!addr) 2722 return -ENOMEM; 2723 2724 *result = addr & ~DPAA_GENALLOC_OFF; 2725 2726 return 0; 2727 } 2728 2729 int qman_alloc_fqid_range(u32 *result, u32 count) 2730 { 2731 return qman_alloc_range(qm_fqalloc, result, count); 2732 } 2733 EXPORT_SYMBOL(qman_alloc_fqid_range); 2734 2735 int qman_alloc_pool_range(u32 *result, u32 count) 2736 { 2737 return qman_alloc_range(qm_qpalloc, result, count); 2738 } 2739 EXPORT_SYMBOL(qman_alloc_pool_range); 2740 2741 int qman_alloc_cgrid_range(u32 *result, u32 count) 2742 { 2743 return qman_alloc_range(qm_cgralloc, result, count); 2744 } 2745 EXPORT_SYMBOL(qman_alloc_cgrid_range); 2746 2747 int qman_release_fqid(u32 fqid) 2748 { 2749 int ret = qman_shutdown_fq(fqid); 2750 2751 if (ret) { 2752 pr_debug("FQID %d leaked\n", fqid); 2753 return ret; 2754 } 2755 2756 gen_pool_free(qm_fqalloc, fqid | DPAA_GENALLOC_OFF, 1); 2757 return 0; 2758 } 2759 EXPORT_SYMBOL(qman_release_fqid); 2760 2761 static int qpool_cleanup(u32 qp) 2762 { 2763 /* 2764 * We query all FQDs starting from 2765 * FQID 1 until we get an "invalid FQID" error, looking for non-OOS FQDs 2766 * whose destination channel is the pool-channel being released. 2767 * When a non-OOS FQD is found we attempt to clean it up 2768 */ 2769 struct qman_fq fq = { 2770 .fqid = QM_FQID_RANGE_START 2771 }; 2772 int err; 2773 2774 do { 2775 struct qm_mcr_queryfq_np np; 2776 2777 err = qman_query_fq_np(&fq, &np); 2778 if (err == -ERANGE) 2779 /* FQID range exceeded, found no problems */ 2780 return 0; 2781 else if (WARN_ON(err)) 2782 return err; 2783 2784 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) { 2785 struct qm_fqd fqd; 2786 2787 err = qman_query_fq(&fq, &fqd); 2788 if (WARN_ON(err)) 2789 return err; 2790 if (qm_fqd_get_chan(&fqd) == qp) { 2791 /* The channel is the FQ's target, clean it */ 2792 err = qman_shutdown_fq(fq.fqid); 2793 if (err) 2794 /* 2795 * Couldn't shut down the FQ 2796 * so the pool must be leaked 2797 */ 2798 return err; 2799 } 2800 } 2801 /* Move to the next FQID */ 2802 fq.fqid++; 2803 } while (1); 2804 } 2805 2806 int qman_release_pool(u32 qp) 2807 { 2808 int ret; 2809 2810 ret = qpool_cleanup(qp); 2811 if (ret) { 2812 pr_debug("CHID %d leaked\n", qp); 2813 return ret; 2814 } 2815 2816 gen_pool_free(qm_qpalloc, qp | DPAA_GENALLOC_OFF, 1); 2817 return 0; 2818 } 2819 EXPORT_SYMBOL(qman_release_pool); 2820 2821 static int cgr_cleanup(u32 cgrid) 2822 { 2823 /* 2824 * query all FQDs starting from FQID 1 until we get an "invalid FQID" 2825 * error, looking for non-OOS FQDs whose CGR is the CGR being released 2826 */ 2827 struct qman_fq fq = { 2828 .fqid = QM_FQID_RANGE_START 2829 }; 2830 int err; 2831 2832 do { 2833 struct qm_mcr_queryfq_np np; 2834 2835 err = qman_query_fq_np(&fq, &np); 2836 if (err == -ERANGE) 2837 /* FQID range exceeded, found no problems */ 2838 return 0; 2839 else if (WARN_ON(err)) 2840 return err; 2841 2842 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) { 2843 struct qm_fqd fqd; 2844 2845 err = qman_query_fq(&fq, &fqd); 2846 if (WARN_ON(err)) 2847 return err; 2848 if (be16_to_cpu(fqd.fq_ctrl) & QM_FQCTRL_CGE && 2849 fqd.cgid == cgrid) { 2850 pr_err("CRGID 0x%x is being used by FQID 0x%x, CGR will be leaked\n", 2851 cgrid, fq.fqid); 2852 return -EIO; 2853 } 2854 } 2855 /* Move to the next FQID */ 2856 fq.fqid++; 2857 } while (1); 2858 } 2859 2860 int qman_release_cgrid(u32 cgrid) 2861 { 2862 int ret; 2863 2864 ret = cgr_cleanup(cgrid); 2865 if (ret) { 2866 pr_debug("CGRID %d leaked\n", cgrid); 2867 return ret; 2868 } 2869 2870 gen_pool_free(qm_cgralloc, cgrid | DPAA_GENALLOC_OFF, 1); 2871 return 0; 2872 } 2873 EXPORT_SYMBOL(qman_release_cgrid); 2874