1*1f9c0a77SClaudiu Manoilmenuconfig FSL_DPAA 2*1f9c0a77SClaudiu Manoil bool "Freescale DPAA 1.x support" 3*1f9c0a77SClaudiu Manoil depends on FSL_SOC_BOOKE 4*1f9c0a77SClaudiu Manoil select GENERIC_ALLOCATOR 5*1f9c0a77SClaudiu Manoil help 6*1f9c0a77SClaudiu Manoil The Freescale Data Path Acceleration Architecture (DPAA) is a set of 7*1f9c0a77SClaudiu Manoil hardware components on specific QorIQ multicore processors. 8*1f9c0a77SClaudiu Manoil This architecture provides the infrastructure to support simplified 9*1f9c0a77SClaudiu Manoil sharing of networking interfaces and accelerators by multiple CPUs. 10*1f9c0a77SClaudiu Manoil The major h/w blocks composing DPAA are BMan and QMan. 11*1f9c0a77SClaudiu Manoil 12*1f9c0a77SClaudiu Manoil The Buffer Manager (BMan) is a hardware buffer pool management block 13*1f9c0a77SClaudiu Manoil that allows software and accelerators on the datapath to acquire and 14*1f9c0a77SClaudiu Manoil release buffers in order to build frames. 15*1f9c0a77SClaudiu Manoil 16*1f9c0a77SClaudiu Manoil The Queue Manager (QMan) is a hardware queue management block 17*1f9c0a77SClaudiu Manoil that allows software and accelerators on the datapath to enqueue and 18*1f9c0a77SClaudiu Manoil dequeue frames in order to communicate. 19*1f9c0a77SClaudiu Manoil 20*1f9c0a77SClaudiu Manoilif FSL_DPAA 21*1f9c0a77SClaudiu Manoil 22*1f9c0a77SClaudiu Manoilconfig FSL_DPAA_CHECKING 23*1f9c0a77SClaudiu Manoil bool "Additional driver checking" 24*1f9c0a77SClaudiu Manoil help 25*1f9c0a77SClaudiu Manoil Compiles in additional checks, to sanity-check the drivers and 26*1f9c0a77SClaudiu Manoil any use of the exported API. Not recommended for performance. 27*1f9c0a77SClaudiu Manoil 28*1f9c0a77SClaudiu Manoilendif # FSL_DPAA 29