1 /* 2 * Definitions for Broadcom STB power management / Always ON (AON) block 3 * 4 * Copyright © 2016-2017 Broadcom 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef __BRCMSTB_PM_H__ 17 #define __BRCMSTB_PM_H__ 18 19 #define AON_CTRL_RESET_CTRL 0x00 20 #define AON_CTRL_PM_CTRL 0x04 21 #define AON_CTRL_PM_STATUS 0x08 22 #define AON_CTRL_PM_CPU_WAIT_COUNT 0x10 23 #define AON_CTRL_PM_INITIATE 0x88 24 #define AON_CTRL_HOST_MISC_CMDS 0x8c 25 #define AON_CTRL_SYSTEM_DATA_RAM_OFS 0x200 26 27 /* MIPS PM constants */ 28 /* MEMC0 offsets */ 29 #define DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x10 30 #define DDR40_PHY_CONTROL_REGS_0_STANDBY_CTRL 0xa4 31 32 /* TIMER offsets */ 33 #define TIMER_TIMER1_CTRL 0x0c 34 #define TIMER_TIMER1_STAT 0x1c 35 36 /* TIMER defines */ 37 #define RESET_TIMER 0x0 38 #define START_TIMER 0xbfffffff 39 #define TIMER_MASK 0x3fffffff 40 41 /* PM_CTRL bitfield (Method #0) */ 42 #define PM_FAST_PWRDOWN (1 << 6) 43 #define PM_WARM_BOOT (1 << 5) 44 #define PM_DEEP_STANDBY (1 << 4) 45 #define PM_CPU_PWR (1 << 3) 46 #define PM_USE_CPU_RDY (1 << 2) 47 #define PM_PLL_PWRDOWN (1 << 1) 48 #define PM_PWR_DOWN (1 << 0) 49 50 /* PM_CTRL bitfield (Method #1) */ 51 #define PM_DPHY_STANDBY_CLEAR (1 << 20) 52 #define PM_MIN_S3_WIDTH_TIMER_BYPASS (1 << 7) 53 54 #define PM_S2_COMMAND (PM_PLL_PWRDOWN | PM_USE_CPU_RDY | PM_PWR_DOWN) 55 56 /* Method 0 bitmasks */ 57 #define PM_COLD_CONFIG (PM_PLL_PWRDOWN | PM_DEEP_STANDBY) 58 #define PM_WARM_CONFIG (PM_COLD_CONFIG | PM_USE_CPU_RDY | PM_WARM_BOOT) 59 60 /* Method 1 bitmask */ 61 #define M1_PM_WARM_CONFIG (PM_DPHY_STANDBY_CLEAR | \ 62 PM_MIN_S3_WIDTH_TIMER_BYPASS | \ 63 PM_WARM_BOOT | PM_DEEP_STANDBY | \ 64 PM_PLL_PWRDOWN | PM_PWR_DOWN) 65 66 #define M1_PM_COLD_CONFIG (PM_DPHY_STANDBY_CLEAR | \ 67 PM_MIN_S3_WIDTH_TIMER_BYPASS | \ 68 PM_DEEP_STANDBY | \ 69 PM_PLL_PWRDOWN | PM_PWR_DOWN) 70 71 #ifndef __ASSEMBLY__ 72 73 #ifndef CONFIG_MIPS 74 extern const unsigned long brcmstb_pm_do_s2_sz; 75 extern asmlinkage int brcmstb_pm_do_s2(void __iomem *aon_ctrl_base, 76 void __iomem *ddr_phy_pll_status); 77 #else 78 /* s2 asm */ 79 extern asmlinkage int brcm_pm_do_s2(u32 *s2_params); 80 81 /* s3 asm */ 82 extern asmlinkage int brcm_pm_do_s3(void __iomem *aon_ctrl_base, 83 int dcache_linesz); 84 extern int s3_reentry; 85 #endif /* CONFIG_MIPS */ 86 87 #endif 88 89 #endif /* __BRCMSTB_PM_H__ */ 90