11802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 20b741b82SBrian Norris /* 30b741b82SBrian Norris * Definitions for Broadcom STB power management / Always ON (AON) block 40b741b82SBrian Norris * 50b741b82SBrian Norris * Copyright © 2016-2017 Broadcom 60b741b82SBrian Norris */ 70b741b82SBrian Norris 80b741b82SBrian Norris #ifndef __BRCMSTB_PM_H__ 90b741b82SBrian Norris #define __BRCMSTB_PM_H__ 100b741b82SBrian Norris 110b741b82SBrian Norris #define AON_CTRL_RESET_CTRL 0x00 120b741b82SBrian Norris #define AON_CTRL_PM_CTRL 0x04 130b741b82SBrian Norris #define AON_CTRL_PM_STATUS 0x08 140b741b82SBrian Norris #define AON_CTRL_PM_CPU_WAIT_COUNT 0x10 150b741b82SBrian Norris #define AON_CTRL_PM_INITIATE 0x88 160b741b82SBrian Norris #define AON_CTRL_HOST_MISC_CMDS 0x8c 170b741b82SBrian Norris #define AON_CTRL_SYSTEM_DATA_RAM_OFS 0x200 180b741b82SBrian Norris 190b741b82SBrian Norris /* MIPS PM constants */ 200b741b82SBrian Norris /* MEMC0 offsets */ 210b741b82SBrian Norris #define DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x10 220b741b82SBrian Norris #define DDR40_PHY_CONTROL_REGS_0_STANDBY_CTRL 0xa4 230b741b82SBrian Norris 240b741b82SBrian Norris /* TIMER offsets */ 250b741b82SBrian Norris #define TIMER_TIMER1_CTRL 0x0c 260b741b82SBrian Norris #define TIMER_TIMER1_STAT 0x1c 270b741b82SBrian Norris 280b741b82SBrian Norris /* TIMER defines */ 290b741b82SBrian Norris #define RESET_TIMER 0x0 300b741b82SBrian Norris #define START_TIMER 0xbfffffff 310b741b82SBrian Norris #define TIMER_MASK 0x3fffffff 320b741b82SBrian Norris 330b741b82SBrian Norris /* PM_CTRL bitfield (Method #0) */ 340b741b82SBrian Norris #define PM_FAST_PWRDOWN (1 << 6) 350b741b82SBrian Norris #define PM_WARM_BOOT (1 << 5) 360b741b82SBrian Norris #define PM_DEEP_STANDBY (1 << 4) 370b741b82SBrian Norris #define PM_CPU_PWR (1 << 3) 380b741b82SBrian Norris #define PM_USE_CPU_RDY (1 << 2) 390b741b82SBrian Norris #define PM_PLL_PWRDOWN (1 << 1) 400b741b82SBrian Norris #define PM_PWR_DOWN (1 << 0) 410b741b82SBrian Norris 420b741b82SBrian Norris /* PM_CTRL bitfield (Method #1) */ 430b741b82SBrian Norris #define PM_DPHY_STANDBY_CLEAR (1 << 20) 440b741b82SBrian Norris #define PM_MIN_S3_WIDTH_TIMER_BYPASS (1 << 7) 450b741b82SBrian Norris 460b741b82SBrian Norris #define PM_S2_COMMAND (PM_PLL_PWRDOWN | PM_USE_CPU_RDY | PM_PWR_DOWN) 470b741b82SBrian Norris 480b741b82SBrian Norris /* Method 0 bitmasks */ 490b741b82SBrian Norris #define PM_COLD_CONFIG (PM_PLL_PWRDOWN | PM_DEEP_STANDBY) 500b741b82SBrian Norris #define PM_WARM_CONFIG (PM_COLD_CONFIG | PM_USE_CPU_RDY | PM_WARM_BOOT) 510b741b82SBrian Norris 520b741b82SBrian Norris /* Method 1 bitmask */ 530b741b82SBrian Norris #define M1_PM_WARM_CONFIG (PM_DPHY_STANDBY_CLEAR | \ 540b741b82SBrian Norris PM_MIN_S3_WIDTH_TIMER_BYPASS | \ 550b741b82SBrian Norris PM_WARM_BOOT | PM_DEEP_STANDBY | \ 560b741b82SBrian Norris PM_PLL_PWRDOWN | PM_PWR_DOWN) 570b741b82SBrian Norris 580b741b82SBrian Norris #define M1_PM_COLD_CONFIG (PM_DPHY_STANDBY_CLEAR | \ 590b741b82SBrian Norris PM_MIN_S3_WIDTH_TIMER_BYPASS | \ 600b741b82SBrian Norris PM_DEEP_STANDBY | \ 610b741b82SBrian Norris PM_PLL_PWRDOWN | PM_PWR_DOWN) 620b741b82SBrian Norris 630b741b82SBrian Norris #ifndef __ASSEMBLY__ 640b741b82SBrian Norris 650e9b1141SJustin Chen #ifndef CONFIG_MIPS 660b741b82SBrian Norris extern const unsigned long brcmstb_pm_do_s2_sz; 670b741b82SBrian Norris extern asmlinkage int brcmstb_pm_do_s2(void __iomem *aon_ctrl_base, 680b741b82SBrian Norris void __iomem *ddr_phy_pll_status); 690e9b1141SJustin Chen #else 700e9b1141SJustin Chen /* s2 asm */ 710e9b1141SJustin Chen extern asmlinkage int brcm_pm_do_s2(u32 *s2_params); 720e9b1141SJustin Chen 730e9b1141SJustin Chen /* s3 asm */ 740e9b1141SJustin Chen extern asmlinkage int brcm_pm_do_s3(void __iomem *aon_ctrl_base, 750e9b1141SJustin Chen int dcache_linesz); 760e9b1141SJustin Chen extern int s3_reentry; 770e9b1141SJustin Chen #endif /* CONFIG_MIPS */ 780e9b1141SJustin Chen 790b741b82SBrian Norris #endif 800b741b82SBrian Norris 810b741b82SBrian Norris #endif /* __BRCMSTB_PM_H__ */ 82