1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom STB SoCs Bus Unit Interface controls 4 * 5 * Copyright (C) 2015, Broadcom Corporation 6 */ 7 8 #define pr_fmt(fmt) "brcmstb: " KBUILD_MODNAME ": " fmt 9 10 #include <linux/kernel.h> 11 #include <linux/io.h> 12 #include <linux/of_address.h> 13 #include <linux/syscore_ops.h> 14 #include <linux/soc/brcmstb/brcmstb.h> 15 16 #define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000 17 #define CPU_CREDIT_REG_MCPx_READ_CRED_MASK 0xf 18 #define CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK 0xf 19 #define CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(x) ((x) * 8) 20 #define CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(x) (((x) * 8) + 4) 21 22 #define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(x) ((x) * 8) 23 #define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK 0xff 24 25 #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK 0xf 26 #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK 0xf 27 #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT 4 28 #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE BIT(8) 29 30 static void __iomem *cpubiuctrl_base; 31 static bool mcp_wr_pairing_en; 32 static const int *cpubiuctrl_regs; 33 34 static inline u32 cbc_readl(int reg) 35 { 36 int offset = cpubiuctrl_regs[reg]; 37 38 if (offset == -1) 39 return (u32)-1; 40 41 return readl_relaxed(cpubiuctrl_base + offset); 42 } 43 44 static inline void cbc_writel(u32 val, int reg) 45 { 46 int offset = cpubiuctrl_regs[reg]; 47 48 if (offset == -1) 49 return; 50 51 writel(val, cpubiuctrl_base + offset); 52 } 53 54 enum cpubiuctrl_regs { 55 CPU_CREDIT_REG = 0, 56 CPU_MCP_FLOW_REG, 57 CPU_WRITEBACK_CTRL_REG 58 }; 59 60 static const int b15_cpubiuctrl_regs[] = { 61 [CPU_CREDIT_REG] = 0x184, 62 [CPU_MCP_FLOW_REG] = -1, 63 [CPU_WRITEBACK_CTRL_REG] = -1, 64 }; 65 66 /* Odd cases, e.g: 7260A0 */ 67 static const int b53_cpubiuctrl_no_wb_regs[] = { 68 [CPU_CREDIT_REG] = 0x0b0, 69 [CPU_MCP_FLOW_REG] = 0x0b4, 70 [CPU_WRITEBACK_CTRL_REG] = -1, 71 }; 72 73 static const int b53_cpubiuctrl_regs[] = { 74 [CPU_CREDIT_REG] = 0x0b0, 75 [CPU_MCP_FLOW_REG] = 0x0b4, 76 [CPU_WRITEBACK_CTRL_REG] = 0x22c, 77 }; 78 79 static const int a72_cpubiuctrl_regs[] = { 80 [CPU_CREDIT_REG] = 0x18, 81 [CPU_MCP_FLOW_REG] = 0x1c, 82 [CPU_WRITEBACK_CTRL_REG] = 0x20, 83 }; 84 85 #define NUM_CPU_BIUCTRL_REGS 3 86 87 static int __init mcp_write_pairing_set(void) 88 { 89 u32 creds = 0; 90 91 if (!cpubiuctrl_base) 92 return -1; 93 94 creds = cbc_readl(CPU_CREDIT_REG); 95 if (mcp_wr_pairing_en) { 96 pr_info("MCP: Enabling write pairing\n"); 97 cbc_writel(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK, 98 CPU_CREDIT_REG); 99 } else if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) { 100 pr_info("MCP: Disabling write pairing\n"); 101 cbc_writel(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK, 102 CPU_CREDIT_REG); 103 } else { 104 pr_info("MCP: Write pairing already disabled\n"); 105 } 106 107 return 0; 108 } 109 110 static const u32 a72_b53_mach_compat[] = { 111 0x7211, 112 0x7216, 113 0x7255, 114 0x7260, 115 0x7268, 116 0x7271, 117 0x7278, 118 }; 119 120 static void __init mcp_a72_b53_set(void) 121 { 122 unsigned int i; 123 u32 reg; 124 125 reg = brcmstb_get_family_id(); 126 127 for (i = 0; i < ARRAY_SIZE(a72_b53_mach_compat); i++) { 128 if (BRCM_ID(reg) == a72_b53_mach_compat[i]) 129 break; 130 } 131 132 if (i == ARRAY_SIZE(a72_b53_mach_compat)) 133 return; 134 135 /* Set all 3 MCP interfaces to 8 credits */ 136 reg = cbc_readl(CPU_CREDIT_REG); 137 for (i = 0; i < 3; i++) { 138 reg &= ~(CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK << 139 CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i)); 140 reg &= ~(CPU_CREDIT_REG_MCPx_READ_CRED_MASK << 141 CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i)); 142 reg |= 8 << CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i); 143 reg |= 8 << CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i); 144 } 145 cbc_writel(reg, CPU_CREDIT_REG); 146 147 /* Max out the number of in-flight Jwords reads on the MCP interface */ 148 reg = cbc_readl(CPU_MCP_FLOW_REG); 149 for (i = 0; i < 3; i++) 150 reg |= CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK << 151 CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(i); 152 cbc_writel(reg, CPU_MCP_FLOW_REG); 153 154 /* Enable writeback throttling, set timeout to 128 cycles, 256 cycles 155 * threshold 156 */ 157 reg = cbc_readl(CPU_WRITEBACK_CTRL_REG); 158 reg |= CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE; 159 reg &= ~CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK; 160 reg &= ~(CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK << 161 CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT); 162 reg |= 8; 163 reg |= 7 << CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT; 164 cbc_writel(reg, CPU_WRITEBACK_CTRL_REG); 165 } 166 167 static int __init setup_hifcpubiuctrl_regs(struct device_node *np) 168 { 169 struct device_node *cpu_dn; 170 u32 family_id; 171 int ret = 0; 172 173 cpubiuctrl_base = of_iomap(np, 0); 174 if (!cpubiuctrl_base) { 175 pr_err("failed to remap BIU control base\n"); 176 ret = -ENOMEM; 177 goto out; 178 } 179 180 mcp_wr_pairing_en = of_property_read_bool(np, "brcm,write-pairing"); 181 182 cpu_dn = of_get_cpu_node(0, NULL); 183 if (!cpu_dn) { 184 pr_err("failed to obtain CPU device node\n"); 185 ret = -ENODEV; 186 goto out; 187 } 188 189 if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15")) 190 cpubiuctrl_regs = b15_cpubiuctrl_regs; 191 else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53")) 192 cpubiuctrl_regs = b53_cpubiuctrl_regs; 193 else if (of_device_is_compatible(cpu_dn, "arm,cortex-a72")) 194 cpubiuctrl_regs = a72_cpubiuctrl_regs; 195 else { 196 pr_err("unsupported CPU\n"); 197 ret = -EINVAL; 198 } 199 of_node_put(cpu_dn); 200 201 family_id = brcmstb_get_family_id(); 202 if (BRCM_ID(family_id) == 0x7260 && BRCM_REV(family_id) == 0) 203 cpubiuctrl_regs = b53_cpubiuctrl_no_wb_regs; 204 out: 205 of_node_put(np); 206 return ret; 207 } 208 209 #ifdef CONFIG_PM_SLEEP 210 static u32 cpubiuctrl_reg_save[NUM_CPU_BIUCTRL_REGS]; 211 212 static int brcmstb_cpu_credit_reg_suspend(void) 213 { 214 unsigned int i; 215 216 if (!cpubiuctrl_base) 217 return 0; 218 219 for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++) 220 cpubiuctrl_reg_save[i] = cbc_readl(i); 221 222 return 0; 223 } 224 225 static void brcmstb_cpu_credit_reg_resume(void) 226 { 227 unsigned int i; 228 229 if (!cpubiuctrl_base) 230 return; 231 232 for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++) 233 cbc_writel(cpubiuctrl_reg_save[i], i); 234 } 235 236 static struct syscore_ops brcmstb_cpu_credit_syscore_ops = { 237 .suspend = brcmstb_cpu_credit_reg_suspend, 238 .resume = brcmstb_cpu_credit_reg_resume, 239 }; 240 #endif 241 242 243 static int __init brcmstb_biuctrl_init(void) 244 { 245 struct device_node *np; 246 int ret; 247 248 /* We might be running on a multi-platform kernel, don't make this a 249 * fatal error, just bail out early 250 */ 251 np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl"); 252 if (!np) 253 return 0; 254 255 ret = setup_hifcpubiuctrl_regs(np); 256 if (ret) 257 return ret; 258 259 ret = mcp_write_pairing_set(); 260 if (ret) { 261 pr_err("MCP: Unable to disable write pairing!\n"); 262 return ret; 263 } 264 265 mcp_a72_b53_set(); 266 #ifdef CONFIG_PM_SLEEP 267 register_syscore_ops(&brcmstb_cpu_credit_syscore_ops); 268 #endif 269 return 0; 270 } 271 early_initcall(brcmstb_biuctrl_init); 272