1# SPDX-License-Identifier: GPL-2.0-only 2 3if ARCH_ASPEED || COMPILE_TEST 4 5menu "ASPEED SoC drivers" 6 7config ASPEED_LPC_CTRL 8 tristate "ASPEED LPC firmware cycle control" 9 select REGMAP 10 select MFD_SYSCON 11 default ARCH_ASPEED 12 help 13 Control LPC firmware cycle mappings through ioctl()s. The driver 14 also provides a read/write interface to a BMC ram region where the 15 host LPC read/write region can be buffered. 16 17config ASPEED_LPC_SNOOP 18 tristate "ASPEED LPC snoop support" 19 select REGMAP 20 select MFD_SYSCON 21 default ARCH_ASPEED 22 help 23 Provides a driver to control the LPC snoop interface which 24 allows the BMC to listen on and save the data written by 25 the host to an arbitrary LPC I/O port. 26 27config ASPEED_UART_ROUTING 28 tristate "ASPEED uart routing control" 29 select REGMAP 30 select MFD_SYSCON 31 default ARCH_ASPEED 32 help 33 Provides a driver to control the UART routing paths, allowing 34 users to perform runtime configuration of the RX muxes among 35 the UART controllers and I/O pins. 36 37config ASPEED_P2A_CTRL 38 tristate "ASPEED P2A (VGA MMIO to BMC) bridge control" 39 select REGMAP 40 select MFD_SYSCON 41 default ARCH_ASPEED 42 help 43 Control ASPEED P2A VGA MMIO to BMC mappings through ioctl()s. The 44 driver also provides an interface for userspace mappings to a 45 pre-defined region. 46 47config ASPEED_SOCINFO 48 bool "ASPEED SoC Information driver" 49 default ARCH_ASPEED 50 select SOC_BUS 51 default ARCH_ASPEED 52 help 53 Say yes to support decoding of ASPEED BMC information. 54 55config ASPEED_XDMA 56 tristate "ASPEED XDMA Engine Driver" 57 select REGMAP 58 select MFD_SYSCON 59 depends on HAS_DMA 60 help 61 Enable support for the XDMA Engine found on the ASPEED BMC 62 SoCs. The XDMA engine can perform PCIe DMA operations between the BMC 63 and a host processor. 64 65endmenu 66 67endif 68